#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
#[doc = "Reset and clock control"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Rcc {
ptr: *mut u8,
}
unsafe impl Send for Rcc {}
unsafe impl Sync for Rcc {}
impl Rcc {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "Clock control register"]
#[inline(always)]
pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "Internal clock sources calibration register"]
#[inline(always)]
pub const fn icscr(self) -> crate::common::Reg<regs::Icscr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "Clock configuration register"]
#[inline(always)]
pub const fn cfgr(self) -> crate::common::Reg<regs::Cfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
}
#[doc = "PLL configuration register"]
#[inline(always)]
pub const fn pllcfgr(self) -> crate::common::Reg<regs::Pllcfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
#[doc = "Clock interrupt enable register"]
#[inline(always)]
pub const fn cier(self) -> crate::common::Reg<regs::Cier, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
}
#[doc = "Clock interrupt flag register"]
#[inline(always)]
pub const fn cifr(self) -> crate::common::Reg<regs::Cifr, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
}
#[doc = "Clock interrupt clear register"]
#[inline(always)]
pub const fn cicr(self) -> crate::common::Reg<regs::Cicr, crate::common::W> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
}
#[doc = "AHB1 peripheral reset register"]
#[inline(always)]
pub const fn ahb1rstr(self) -> crate::common::Reg<regs::Ahb1rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
}
#[doc = "AHB2 peripheral reset register"]
#[inline(always)]
pub const fn ahb2rstr(self) -> crate::common::Reg<regs::Ahb2rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
}
#[doc = "AHB3 peripheral reset register"]
#[inline(always)]
pub const fn ahb3rstr(self) -> crate::common::Reg<regs::Ahb3rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
}
#[doc = "APB1 peripheral reset register 1"]
#[inline(always)]
pub const fn apb1rstr1(self) -> crate::common::Reg<regs::Apb1rstr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
}
#[doc = "APB1 peripheral reset register 2"]
#[inline(always)]
pub const fn apb1rstr2(self) -> crate::common::Reg<regs::Apb1rstr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
}
#[doc = "APB2 peripheral reset register"]
#[inline(always)]
pub const fn apb2rstr(self) -> crate::common::Reg<regs::Apb2rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
}
#[doc = "APB3 peripheral reset register"]
#[inline(always)]
pub const fn apb3rstr(self) -> crate::common::Reg<regs::Apb3rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
}
#[doc = "AHB1 peripheral clock enable register"]
#[inline(always)]
pub const fn ahb1enr(self) -> crate::common::Reg<regs::Ahb1enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
}
#[doc = "AHB2 peripheral clock enable register"]
#[inline(always)]
pub const fn ahb2enr(self) -> crate::common::Reg<regs::Ahb2enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
}
#[doc = "AHB3 peripheral clock enable register"]
#[inline(always)]
pub const fn ahb3enr(self) -> crate::common::Reg<regs::Ahb3enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
}
#[doc = "APB1 peripheral clock enable register 1"]
#[inline(always)]
pub const fn apb1enr1(self) -> crate::common::Reg<regs::Apb1enr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
}
#[doc = "APB1 peripheral clock enable register 2"]
#[inline(always)]
pub const fn apb1enr2(self) -> crate::common::Reg<regs::Apb1enr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
}
#[doc = "APB2 peripheral clock enable register"]
#[inline(always)]
pub const fn apb2enr(self) -> crate::common::Reg<regs::Apb2enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
}
#[doc = "APB3 peripheral clock enable register"]
#[inline(always)]
pub const fn apb3enr(self) -> crate::common::Reg<regs::Apb3enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) }
}
#[doc = "AHB1 peripheral clocks enable in Sleep modes register"]
#[inline(always)]
pub const fn ahb1smenr(self) -> crate::common::Reg<regs::Ahb1smenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
}
#[doc = "AHB2 peripheral clocks enable in Sleep modes register"]
#[inline(always)]
pub const fn ahb2smenr(self) -> crate::common::Reg<regs::Ahb2smenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) }
}
#[doc = "AHB3 peripheral clocks enable in Sleep and Stop modes register"]
#[inline(always)]
pub const fn ahb3smenr(self) -> crate::common::Reg<regs::Ahb3smenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) }
}
#[doc = "APB1 peripheral clocks enable in Sleep mode register 1"]
#[inline(always)]
pub const fn apb1smenr1(self) -> crate::common::Reg<regs::Apb1smenr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) }
}
#[doc = "APB1 peripheral clocks enable in Sleep mode register 2"]
#[inline(always)]
pub const fn apb1smenr2(self) -> crate::common::Reg<regs::Apb1smenr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) }
}
#[doc = "APB2 peripheral clocks enable in Sleep mode register"]
#[inline(always)]
pub const fn apb2smenr(self) -> crate::common::Reg<regs::Apb2smenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
}
#[doc = "APB3 peripheral clock enable in Sleep mode register"]
#[inline(always)]
pub const fn apb3smenr(self) -> crate::common::Reg<regs::Apb3smenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) }
}
#[doc = "Peripherals independent clock configuration register"]
#[inline(always)]
pub const fn ccipr(self) -> crate::common::Reg<regs::Ccipr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) }
}
#[doc = "Backup domain control register"]
#[inline(always)]
pub const fn bdcr(self) -> crate::common::Reg<regs::Bdcr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) }
}
#[doc = "Control/status register"]
#[inline(always)]
pub const fn csr(self) -> crate::common::Reg<regs::Csr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) }
}
#[doc = "Extended clock recovery register"]
#[inline(always)]
pub const fn extcfgr(self) -> crate::common::Reg<regs::Extcfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) }
}
#[doc = "CPU2 AHB1 peripheral clock enable register"]
#[inline(always)]
pub const fn c2ahb1enr(self) -> crate::common::Reg<regs::C2ahb1enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0148usize) as _) }
}
#[doc = "CPU2 AHB2 peripheral clock enable register"]
#[inline(always)]
pub const fn c2ahb2enr(self) -> crate::common::Reg<regs::C2ahb2enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x014cusize) as _) }
}
#[doc = "CPU2 AHB3 peripheral clock enable register \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2ahb3enr(self) -> crate::common::Reg<regs::C2ahb3enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0150usize) as _) }
}
#[doc = "CPU2 APB1 peripheral clock enable register 1 \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2apb1enr1(self) -> crate::common::Reg<regs::C2apb1enr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0158usize) as _) }
}
#[doc = "CPU2 APB1 peripheral clock enable register 2 \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2apb1enr2(self) -> crate::common::Reg<regs::C2apb1enr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x015cusize) as _) }
}
#[doc = "CPU2 APB2 peripheral clock enable register \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2apb2enr(self) -> crate::common::Reg<regs::C2apb2enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0160usize) as _) }
}
#[doc = "CPU2 APB3 peripheral clock enable register \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2apb3enr(self) -> crate::common::Reg<regs::C2apb3enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0164usize) as _) }
}
#[doc = "CPU2 AHB1 peripheral clocks enable in Sleep modes register \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2ahb1smenr(self) -> crate::common::Reg<regs::C2ahb1smenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0168usize) as _) }
}
#[doc = "CPU2 AHB2 peripheral clocks enable in Sleep modes register \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2ahb2smenr(self) -> crate::common::Reg<regs::C2ahb2smenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x016cusize) as _) }
}
#[doc = "CPU2 AHB3 peripheral clocks enable in Sleep mode register \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2ahb3smenr(self) -> crate::common::Reg<regs::C2ahb3smenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0170usize) as _) }
}
#[doc = "CPU2 APB1 peripheral clocks enable in Sleep mode register 1 \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2apb1smenr1(self) -> crate::common::Reg<regs::C2apb1smenr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0178usize) as _) }
}
#[doc = "CPU2 APB1 peripheral clocks enable in Sleep mode register 2 \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2apb1smenr2(self) -> crate::common::Reg<regs::C2apb1smenr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x017cusize) as _) }
}
#[doc = "CPU2 APB2 peripheral clocks enable in Sleep mode register \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2apb2smenr(self) -> crate::common::Reg<regs::C2apb2smenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0180usize) as _) }
}
#[doc = "CPU2 APB3 peripheral clock enable in Sleep mode register \\[dual core device only\\]"]
#[inline(always)]
pub const fn c2apb3smenr(self) -> crate::common::Reg<regs::C2apb3smenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0184usize) as _) }
}
}
pub mod regs {
#[doc = "AHB1 peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb1enr(pub u32);
impl Ahb1enr {
#[doc = "CPU1 DMA1 clock enable"]
#[inline(always)]
pub const fn dma1en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "CPU1 DMA1 clock enable"]
#[inline(always)]
pub fn set_dma1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "CPU1 DMA2 clock enable"]
#[inline(always)]
pub const fn dma2en(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "CPU1 DMA2 clock enable"]
#[inline(always)]
pub fn set_dma2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "CPU1 DMAMUX1 clock enable"]
#[inline(always)]
pub const fn dmamux1en(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "CPU1 DMAMUX1 clock enable"]
#[inline(always)]
pub fn set_dmamux1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "CPU1 CRC clock enable"]
#[inline(always)]
pub const fn crcen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CPU1 CRC clock enable"]
#[inline(always)]
pub fn set_crcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
}
impl Default for Ahb1enr {
#[inline(always)]
fn default() -> Ahb1enr {
Ahb1enr(0)
}
}
impl core::fmt::Debug for Ahb1enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb1enr")
.field("dma1en", &self.dma1en())
.field("dma2en", &self.dma2en())
.field("dmamux1en", &self.dmamux1en())
.field("crcen", &self.crcen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb1enr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ahb1enr {{ dma1en: {=bool:?}, dma2en: {=bool:?}, dmamux1en: {=bool:?}, crcen: {=bool:?} }}",
self.dma1en(),
self.dma2en(),
self.dmamux1en(),
self.crcen()
)
}
}
#[doc = "AHB1 peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb1rstr(pub u32);
impl Ahb1rstr {
#[doc = "DMA1 reset"]
#[inline(always)]
pub const fn dma1rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "DMA1 reset"]
#[inline(always)]
pub fn set_dma1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "DMA2 reset"]
#[inline(always)]
pub const fn dma2rst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "DMA2 reset"]
#[inline(always)]
pub fn set_dma2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "DMAMUX1 reset"]
#[inline(always)]
pub const fn dmamux1rst(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "DMAMUX1 reset"]
#[inline(always)]
pub fn set_dmamux1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "CRC reset"]
#[inline(always)]
pub const fn crcrst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC reset"]
#[inline(always)]
pub fn set_crcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
}
impl Default for Ahb1rstr {
#[inline(always)]
fn default() -> Ahb1rstr {
Ahb1rstr(0)
}
}
impl core::fmt::Debug for Ahb1rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb1rstr")
.field("dma1rst", &self.dma1rst())
.field("dma2rst", &self.dma2rst())
.field("dmamux1rst", &self.dmamux1rst())
.field("crcrst", &self.crcrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb1rstr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ahb1rstr {{ dma1rst: {=bool:?}, dma2rst: {=bool:?}, dmamux1rst: {=bool:?}, crcrst: {=bool:?} }}",
self.dma1rst(),
self.dma2rst(),
self.dmamux1rst(),
self.crcrst()
)
}
}
#[doc = "AHB1 peripheral clocks enable in Sleep modes register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb1smenr(pub u32);
impl Ahb1smenr {
#[doc = "DMA1 clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn dma1smen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "DMA1 clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_dma1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "DMA2 clock enable during CPU1 CSleep mode"]
#[inline(always)]
pub const fn dma2smen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "DMA2 clock enable during CPU1 CSleep mode"]
#[inline(always)]
pub fn set_dma2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "DMAMUX1 clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn dmamux1smen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "DMAMUX1 clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_dmamux1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "CRC clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn crcsmen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_crcsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
}
impl Default for Ahb1smenr {
#[inline(always)]
fn default() -> Ahb1smenr {
Ahb1smenr(0)
}
}
impl core::fmt::Debug for Ahb1smenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb1smenr")
.field("dma1smen", &self.dma1smen())
.field("dma2smen", &self.dma2smen())
.field("dmamux1smen", &self.dmamux1smen())
.field("crcsmen", &self.crcsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb1smenr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ahb1smenr {{ dma1smen: {=bool:?}, dma2smen: {=bool:?}, dmamux1smen: {=bool:?}, crcsmen: {=bool:?} }}",
self.dma1smen(),
self.dma2smen(),
self.dmamux1smen(),
self.crcsmen()
)
}
}
#[doc = "AHB2 peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb2enr(pub u32);
impl Ahb2enr {
#[doc = "CPU1 IO port A clock enable"]
#[inline(always)]
pub const fn gpioaen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "CPU1 IO port A clock enable"]
#[inline(always)]
pub fn set_gpioaen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "CPU1 IO port B clock enable"]
#[inline(always)]
pub const fn gpioben(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "CPU1 IO port B clock enable"]
#[inline(always)]
pub fn set_gpioben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "CPU1 IO port C clock enable"]
#[inline(always)]
pub const fn gpiocen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "CPU1 IO port C clock enable"]
#[inline(always)]
pub fn set_gpiocen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "CPU1 IO port H clock enable"]
#[inline(always)]
pub const fn gpiohen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "CPU1 IO port H clock enable"]
#[inline(always)]
pub fn set_gpiohen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
}
impl Default for Ahb2enr {
#[inline(always)]
fn default() -> Ahb2enr {
Ahb2enr(0)
}
}
impl core::fmt::Debug for Ahb2enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb2enr")
.field("gpioaen", &self.gpioaen())
.field("gpioben", &self.gpioben())
.field("gpiocen", &self.gpiocen())
.field("gpiohen", &self.gpiohen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb2enr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ahb2enr {{ gpioaen: {=bool:?}, gpioben: {=bool:?}, gpiocen: {=bool:?}, gpiohen: {=bool:?} }}",
self.gpioaen(),
self.gpioben(),
self.gpiocen(),
self.gpiohen()
)
}
}
#[doc = "AHB2 peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb2rstr(pub u32);
impl Ahb2rstr {
#[doc = "IO port A reset"]
#[inline(always)]
pub const fn gpioarst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "IO port A reset"]
#[inline(always)]
pub fn set_gpioarst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "IO port B reset"]
#[inline(always)]
pub const fn gpiobrst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "IO port B reset"]
#[inline(always)]
pub fn set_gpiobrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "IO port C reset"]
#[inline(always)]
pub const fn gpiocrst(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "IO port C reset"]
#[inline(always)]
pub fn set_gpiocrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "IO port H reset"]
#[inline(always)]
pub const fn gpiohrst(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "IO port H reset"]
#[inline(always)]
pub fn set_gpiohrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
}
impl Default for Ahb2rstr {
#[inline(always)]
fn default() -> Ahb2rstr {
Ahb2rstr(0)
}
}
impl core::fmt::Debug for Ahb2rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb2rstr")
.field("gpioarst", &self.gpioarst())
.field("gpiobrst", &self.gpiobrst())
.field("gpiocrst", &self.gpiocrst())
.field("gpiohrst", &self.gpiohrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb2rstr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ahb2rstr {{ gpioarst: {=bool:?}, gpiobrst: {=bool:?}, gpiocrst: {=bool:?}, gpiohrst: {=bool:?} }}",
self.gpioarst(),
self.gpiobrst(),
self.gpiocrst(),
self.gpiohrst()
)
}
}
#[doc = "AHB2 peripheral clocks enable in Sleep modes register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb2smenr(pub u32);
impl Ahb2smenr {
#[doc = "IO port A clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn gpioasmen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "IO port A clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_gpioasmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "IO port B clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn gpiobsmen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "IO port B clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_gpiobsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "IO port C clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn gpiocsmen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "IO port C clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_gpiocsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "IO port H clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn gpiohsmen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "IO port H clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_gpiohsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
}
impl Default for Ahb2smenr {
#[inline(always)]
fn default() -> Ahb2smenr {
Ahb2smenr(0)
}
}
impl core::fmt::Debug for Ahb2smenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb2smenr")
.field("gpioasmen", &self.gpioasmen())
.field("gpiobsmen", &self.gpiobsmen())
.field("gpiocsmen", &self.gpiocsmen())
.field("gpiohsmen", &self.gpiohsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb2smenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb2smenr {{ gpioasmen: {=bool:?}, gpiobsmen: {=bool:?}, gpiocsmen: {=bool:?}, gpiohsmen: {=bool:?} }}" , self . gpioasmen () , self . gpiobsmen () , self . gpiocsmen () , self . gpiohsmen ())
}
}
#[doc = "AHB3 peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb3enr(pub u32);
impl Ahb3enr {
#[doc = "PKAEN"]
#[inline(always)]
pub const fn pkaen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "PKAEN"]
#[inline(always)]
pub fn set_pkaen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "AESEN"]
#[inline(always)]
pub const fn aesen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "AESEN"]
#[inline(always)]
pub fn set_aesen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "RNGEN"]
#[inline(always)]
pub const fn rngen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "RNGEN"]
#[inline(always)]
pub fn set_rngen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "HSEMEN"]
#[inline(always)]
pub const fn hsemen(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "HSEMEN"]
#[inline(always)]
pub fn set_hsemen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "IPCCEN"]
#[inline(always)]
pub const fn ipccen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "IPCCEN"]
#[inline(always)]
pub fn set_ipccen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "CPU1 Flash interface clock enable"]
#[inline(always)]
pub const fn flashen(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "CPU1 Flash interface clock enable"]
#[inline(always)]
pub fn set_flashen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for Ahb3enr {
#[inline(always)]
fn default() -> Ahb3enr {
Ahb3enr(0)
}
}
impl core::fmt::Debug for Ahb3enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb3enr")
.field("pkaen", &self.pkaen())
.field("aesen", &self.aesen())
.field("rngen", &self.rngen())
.field("hsemen", &self.hsemen())
.field("ipccen", &self.ipccen())
.field("flashen", &self.flashen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb3enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb3enr {{ pkaen: {=bool:?}, aesen: {=bool:?}, rngen: {=bool:?}, hsemen: {=bool:?}, ipccen: {=bool:?}, flashen: {=bool:?} }}" , self . pkaen () , self . aesen () , self . rngen () , self . hsemen () , self . ipccen () , self . flashen ())
}
}
#[doc = "AHB3 peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb3rstr(pub u32);
impl Ahb3rstr {
#[doc = "PKARST"]
#[inline(always)]
pub const fn pkarst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "PKARST"]
#[inline(always)]
pub fn set_pkarst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "AESRST"]
#[inline(always)]
pub const fn aesrst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "AESRST"]
#[inline(always)]
pub fn set_aesrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "RNGRST"]
#[inline(always)]
pub const fn rngrst(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "RNGRST"]
#[inline(always)]
pub fn set_rngrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "HSEMRST"]
#[inline(always)]
pub const fn hsemrst(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "HSEMRST"]
#[inline(always)]
pub fn set_hsemrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "IPCCRST"]
#[inline(always)]
pub const fn ipccrst(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "IPCCRST"]
#[inline(always)]
pub fn set_ipccrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "Flash interface reset"]
#[inline(always)]
pub const fn flashrst(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Flash interface reset"]
#[inline(always)]
pub fn set_flashrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for Ahb3rstr {
#[inline(always)]
fn default() -> Ahb3rstr {
Ahb3rstr(0)
}
}
impl core::fmt::Debug for Ahb3rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb3rstr")
.field("pkarst", &self.pkarst())
.field("aesrst", &self.aesrst())
.field("rngrst", &self.rngrst())
.field("hsemrst", &self.hsemrst())
.field("ipccrst", &self.ipccrst())
.field("flashrst", &self.flashrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb3rstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb3rstr {{ pkarst: {=bool:?}, aesrst: {=bool:?}, rngrst: {=bool:?}, hsemrst: {=bool:?}, ipccrst: {=bool:?}, flashrst: {=bool:?} }}" , self . pkarst () , self . aesrst () , self . rngrst () , self . hsemrst () , self . ipccrst () , self . flashrst ())
}
}
#[doc = "AHB3 peripheral clocks enable in Sleep and Stop modes register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb3smenr(pub u32);
impl Ahb3smenr {
#[doc = "PKA accelerator clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn pkasmen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "PKA accelerator clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_pkasmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "AES accelerator clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn aessmen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "AES accelerator clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_aessmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "True RNG clocks enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub const fn rngsmen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "True RNG clocks enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub fn set_rngsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "SRAM1 interface clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn sram1smen(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "SRAM1 interface clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_sram1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "SRAM2 memory interface clock enable during CPU1 CSleep mode"]
#[inline(always)]
pub const fn sram2smen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "SRAM2 memory interface clock enable during CPU1 CSleep mode"]
#[inline(always)]
pub fn set_sram2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Flash interface clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn flashsmen(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Flash interface clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_flashsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for Ahb3smenr {
#[inline(always)]
fn default() -> Ahb3smenr {
Ahb3smenr(0)
}
}
impl core::fmt::Debug for Ahb3smenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb3smenr")
.field("pkasmen", &self.pkasmen())
.field("aessmen", &self.aessmen())
.field("rngsmen", &self.rngsmen())
.field("sram1smen", &self.sram1smen())
.field("sram2smen", &self.sram2smen())
.field("flashsmen", &self.flashsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb3smenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb3smenr {{ pkasmen: {=bool:?}, aessmen: {=bool:?}, rngsmen: {=bool:?}, sram1smen: {=bool:?}, sram2smen: {=bool:?}, flashsmen: {=bool:?} }}" , self . pkasmen () , self . aessmen () , self . rngsmen () , self . sram1smen () , self . sram2smen () , self . flashsmen ())
}
}
#[doc = "APB1 peripheral clock enable register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1enr1(pub u32);
impl Apb1enr1 {
#[doc = "CPU1 TIM2 timer clock enable"]
#[inline(always)]
pub const fn tim2en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "CPU1 TIM2 timer clock enable"]
#[inline(always)]
pub fn set_tim2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "CPU1 RTC APB clock enable"]
#[inline(always)]
pub const fn rtcapben(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "CPU1 RTC APB clock enable"]
#[inline(always)]
pub fn set_rtcapben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "CPU1 Window watchdog clock enable"]
#[inline(always)]
pub const fn wwdgen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "CPU1 Window watchdog clock enable"]
#[inline(always)]
pub fn set_wwdgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "CPU1 SPI2 clock enable"]
#[inline(always)]
pub const fn spi2en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "CPU1 SPI2 clock enable"]
#[inline(always)]
pub fn set_spi2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "CPU1 USART2 clock enable"]
#[inline(always)]
pub const fn usart2en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "CPU1 USART2 clock enable"]
#[inline(always)]
pub fn set_usart2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "CPU1 I2C1 clocks enable"]
#[inline(always)]
pub const fn i2c1en(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "CPU1 I2C1 clocks enable"]
#[inline(always)]
pub fn set_i2c1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "CPU1 I2C2 clocks enable"]
#[inline(always)]
pub const fn i2c2en(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "CPU1 I2C2 clocks enable"]
#[inline(always)]
pub fn set_i2c2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "CPU1 I2C3 clocks enable"]
#[inline(always)]
pub const fn i2c3en(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "CPU1 I2C3 clocks enable"]
#[inline(always)]
pub fn set_i2c3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "CPU1 DAC clock enable"]
#[inline(always)]
pub const fn dacen(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "CPU1 DAC clock enable"]
#[inline(always)]
pub fn set_dacen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "CPU1 Low power timer 1 clocks enable"]
#[inline(always)]
pub const fn lptim1en(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "CPU1 Low power timer 1 clocks enable"]
#[inline(always)]
pub fn set_lptim1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apb1enr1 {
#[inline(always)]
fn default() -> Apb1enr1 {
Apb1enr1(0)
}
}
impl core::fmt::Debug for Apb1enr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1enr1")
.field("tim2en", &self.tim2en())
.field("rtcapben", &self.rtcapben())
.field("wwdgen", &self.wwdgen())
.field("spi2en", &self.spi2en())
.field("usart2en", &self.usart2en())
.field("i2c1en", &self.i2c1en())
.field("i2c2en", &self.i2c2en())
.field("i2c3en", &self.i2c3en())
.field("dacen", &self.dacen())
.field("lptim1en", &self.lptim1en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1enr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1enr1 {{ tim2en: {=bool:?}, rtcapben: {=bool:?}, wwdgen: {=bool:?}, spi2en: {=bool:?}, usart2en: {=bool:?}, i2c1en: {=bool:?}, i2c2en: {=bool:?}, i2c3en: {=bool:?}, dacen: {=bool:?}, lptim1en: {=bool:?} }}" , self . tim2en () , self . rtcapben () , self . wwdgen () , self . spi2en () , self . usart2en () , self . i2c1en () , self . i2c2en () , self . i2c3en () , self . dacen () , self . lptim1en ())
}
}
#[doc = "APB1 peripheral clock enable register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1enr2(pub u32);
impl Apb1enr2 {
#[doc = "CPU1 Low power UART 1 clocks enable"]
#[inline(always)]
pub const fn lpuart1en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "CPU1 Low power UART 1 clocks enable"]
#[inline(always)]
pub fn set_lpuart1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "CPU1 Low power timer 2 clocks enable"]
#[inline(always)]
pub const fn lptim2en(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "CPU1 Low power timer 2 clocks enable"]
#[inline(always)]
pub fn set_lptim2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "CPU1 Low power timer 3 clocks enable"]
#[inline(always)]
pub const fn lptim3en(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "CPU1 Low power timer 3 clocks enable"]
#[inline(always)]
pub fn set_lptim3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
}
impl Default for Apb1enr2 {
#[inline(always)]
fn default() -> Apb1enr2 {
Apb1enr2(0)
}
}
impl core::fmt::Debug for Apb1enr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1enr2")
.field("lpuart1en", &self.lpuart1en())
.field("lptim2en", &self.lptim2en())
.field("lptim3en", &self.lptim3en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1enr2 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Apb1enr2 {{ lpuart1en: {=bool:?}, lptim2en: {=bool:?}, lptim3en: {=bool:?} }}",
self.lpuart1en(),
self.lptim2en(),
self.lptim3en()
)
}
}
#[doc = "APB1 peripheral reset register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1rstr1(pub u32);
impl Apb1rstr1 {
#[doc = "TIM2 timer reset"]
#[inline(always)]
pub const fn tim2rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 timer reset"]
#[inline(always)]
pub fn set_tim2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "SPI2 reset"]
#[inline(always)]
pub const fn spi2rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 reset"]
#[inline(always)]
pub fn set_spi2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "USART2 reset"]
#[inline(always)]
pub const fn usart2rst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 reset"]
#[inline(always)]
pub fn set_usart2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "I2C1 reset"]
#[inline(always)]
pub const fn i2c1rst(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 reset"]
#[inline(always)]
pub fn set_i2c1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 reset"]
#[inline(always)]
pub const fn i2c2rst(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 reset"]
#[inline(always)]
pub fn set_i2c2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "I2C3 reset"]
#[inline(always)]
pub const fn i2c3rst(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "I2C3 reset"]
#[inline(always)]
pub fn set_i2c3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "DAC reset"]
#[inline(always)]
pub const fn dacrst(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "DAC reset"]
#[inline(always)]
pub fn set_dacrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Low Power Timer 1 reset"]
#[inline(always)]
pub const fn lptim1rst(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Low Power Timer 1 reset"]
#[inline(always)]
pub fn set_lptim1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apb1rstr1 {
#[inline(always)]
fn default() -> Apb1rstr1 {
Apb1rstr1(0)
}
}
impl core::fmt::Debug for Apb1rstr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1rstr1")
.field("tim2rst", &self.tim2rst())
.field("spi2rst", &self.spi2rst())
.field("usart2rst", &self.usart2rst())
.field("i2c1rst", &self.i2c1rst())
.field("i2c2rst", &self.i2c2rst())
.field("i2c3rst", &self.i2c3rst())
.field("dacrst", &self.dacrst())
.field("lptim1rst", &self.lptim1rst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1rstr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1rstr1 {{ tim2rst: {=bool:?}, spi2rst: {=bool:?}, usart2rst: {=bool:?}, i2c1rst: {=bool:?}, i2c2rst: {=bool:?}, i2c3rst: {=bool:?}, dacrst: {=bool:?}, lptim1rst: {=bool:?} }}" , self . tim2rst () , self . spi2rst () , self . usart2rst () , self . i2c1rst () , self . i2c2rst () , self . i2c3rst () , self . dacrst () , self . lptim1rst ())
}
}
#[doc = "APB1 peripheral reset register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1rstr2(pub u32);
impl Apb1rstr2 {
#[doc = "Low-power UART 1 reset"]
#[inline(always)]
pub const fn lpuart1rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Low-power UART 1 reset"]
#[inline(always)]
pub fn set_lpuart1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Low-power timer 2 reset"]
#[inline(always)]
pub const fn lptim2rst(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Low-power timer 2 reset"]
#[inline(always)]
pub fn set_lptim2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Low-power timer 3 reset"]
#[inline(always)]
pub const fn lptim3rst(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "Low-power timer 3 reset"]
#[inline(always)]
pub fn set_lptim3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
}
impl Default for Apb1rstr2 {
#[inline(always)]
fn default() -> Apb1rstr2 {
Apb1rstr2(0)
}
}
impl core::fmt::Debug for Apb1rstr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1rstr2")
.field("lpuart1rst", &self.lpuart1rst())
.field("lptim2rst", &self.lptim2rst())
.field("lptim3rst", &self.lptim3rst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1rstr2 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Apb1rstr2 {{ lpuart1rst: {=bool:?}, lptim2rst: {=bool:?}, lptim3rst: {=bool:?} }}",
self.lpuart1rst(),
self.lptim2rst(),
self.lptim3rst()
)
}
}
#[doc = "APB1 peripheral clocks enable in Sleep mode register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1smenr1(pub u32);
impl Apb1smenr1 {
#[doc = "TIM2 timer clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn tim2smen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 timer clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_tim2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "RTC bus clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn rtcapbsmen(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "RTC bus clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_rtcapbsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "Window watchdog clocks enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn wwdgsmen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Window watchdog clocks enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_wwdgsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI2 clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn spi2smen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_spi2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "USART2 clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn usart2smen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_usart2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "I2C1 clock enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub const fn i2c1smen(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 clock enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub fn set_i2c1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 clock enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub const fn i2c2smen(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 clock enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub fn set_i2c2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "I2C3 clock enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub const fn i2c3smen(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "I2C3 clock enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub fn set_i2c3smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "DAC clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn dacsmen(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "DAC clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_dacsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Low power timer 1 clock enable during CPU1 Csleep and CStop mode"]
#[inline(always)]
pub const fn lptim1smen(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Low power timer 1 clock enable during CPU1 Csleep and CStop mode"]
#[inline(always)]
pub fn set_lptim1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apb1smenr1 {
#[inline(always)]
fn default() -> Apb1smenr1 {
Apb1smenr1(0)
}
}
impl core::fmt::Debug for Apb1smenr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1smenr1")
.field("tim2smen", &self.tim2smen())
.field("rtcapbsmen", &self.rtcapbsmen())
.field("wwdgsmen", &self.wwdgsmen())
.field("spi2smen", &self.spi2smen())
.field("usart2smen", &self.usart2smen())
.field("i2c1smen", &self.i2c1smen())
.field("i2c2smen", &self.i2c2smen())
.field("i2c3smen", &self.i2c3smen())
.field("dacsmen", &self.dacsmen())
.field("lptim1smen", &self.lptim1smen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1smenr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1smenr1 {{ tim2smen: {=bool:?}, rtcapbsmen: {=bool:?}, wwdgsmen: {=bool:?}, spi2smen: {=bool:?}, usart2smen: {=bool:?}, i2c1smen: {=bool:?}, i2c2smen: {=bool:?}, i2c3smen: {=bool:?}, dacsmen: {=bool:?}, lptim1smen: {=bool:?} }}" , self . tim2smen () , self . rtcapbsmen () , self . wwdgsmen () , self . spi2smen () , self . usart2smen () , self . i2c1smen () , self . i2c2smen () , self . i2c3smen () , self . dacsmen () , self . lptim1smen ())
}
}
#[doc = "APB1 peripheral clocks enable in Sleep mode register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1smenr2(pub u32);
impl Apb1smenr2 {
#[doc = "Low power UART 1 clock enable during CPU1 Csleep and CStop modes."]
#[inline(always)]
pub const fn lpuart1smen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Low power UART 1 clock enable during CPU1 Csleep and CStop modes."]
#[inline(always)]
pub fn set_lpuart1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Low power timer 2 clock enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub const fn lptim2smen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Low power timer 2 clock enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub fn set_lptim2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Low power timer 3 clock enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub const fn lptim3smen(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "Low power timer 3 clock enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub fn set_lptim3smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
}
impl Default for Apb1smenr2 {
#[inline(always)]
fn default() -> Apb1smenr2 {
Apb1smenr2(0)
}
}
impl core::fmt::Debug for Apb1smenr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1smenr2")
.field("lpuart1smen", &self.lpuart1smen())
.field("lptim2smen", &self.lptim2smen())
.field("lptim3smen", &self.lptim3smen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1smenr2 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Apb1smenr2 {{ lpuart1smen: {=bool:?}, lptim2smen: {=bool:?}, lptim3smen: {=bool:?} }}",
self.lpuart1smen(),
self.lptim2smen(),
self.lptim3smen()
)
}
}
#[doc = "APB2 peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb2enr(pub u32);
impl Apb2enr {
#[doc = "CPU1 ADC clocks enable"]
#[inline(always)]
pub const fn adcen(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "CPU1 ADC clocks enable"]
#[inline(always)]
pub fn set_adcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "CPU1 TIM1 timer clock enable"]
#[inline(always)]
pub const fn tim1en(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "CPU1 TIM1 timer clock enable"]
#[inline(always)]
pub fn set_tim1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "CPU1 SPI1 clock enable"]
#[inline(always)]
pub const fn spi1en(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CPU1 SPI1 clock enable"]
#[inline(always)]
pub fn set_spi1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "CPU1 USART1clocks enable"]
#[inline(always)]
pub const fn usart1en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "CPU1 USART1clocks enable"]
#[inline(always)]
pub fn set_usart1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "CPU1 TIM16 timer clock enable"]
#[inline(always)]
pub const fn tim16en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "CPU1 TIM16 timer clock enable"]
#[inline(always)]
pub fn set_tim16en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "CPU1 TIM17 timer clock enable"]
#[inline(always)]
pub const fn tim17en(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "CPU1 TIM17 timer clock enable"]
#[inline(always)]
pub fn set_tim17en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for Apb2enr {
#[inline(always)]
fn default() -> Apb2enr {
Apb2enr(0)
}
}
impl core::fmt::Debug for Apb2enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb2enr")
.field("adcen", &self.adcen())
.field("tim1en", &self.tim1en())
.field("spi1en", &self.spi1en())
.field("usart1en", &self.usart1en())
.field("tim16en", &self.tim16en())
.field("tim17en", &self.tim17en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb2enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb2enr {{ adcen: {=bool:?}, tim1en: {=bool:?}, spi1en: {=bool:?}, usart1en: {=bool:?}, tim16en: {=bool:?}, tim17en: {=bool:?} }}" , self . adcen () , self . tim1en () , self . spi1en () , self . usart1en () , self . tim16en () , self . tim17en ())
}
}
#[doc = "APB2 peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb2rstr(pub u32);
impl Apb2rstr {
#[doc = "ADC reset"]
#[inline(always)]
pub const fn adcrst(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "ADC reset"]
#[inline(always)]
pub fn set_adcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "TIM1 timer reset"]
#[inline(always)]
pub const fn tim1rst(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 timer reset"]
#[inline(always)]
pub fn set_tim1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 reset"]
#[inline(always)]
pub const fn spi1rst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 reset"]
#[inline(always)]
pub fn set_spi1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1 reset"]
#[inline(always)]
pub const fn usart1rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 reset"]
#[inline(always)]
pub fn set_usart1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM16 timer reset"]
#[inline(always)]
pub const fn tim16rst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer reset"]
#[inline(always)]
pub fn set_tim16rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM17 timer reset"]
#[inline(always)]
pub const fn tim17rst(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM17 timer reset"]
#[inline(always)]
pub fn set_tim17rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for Apb2rstr {
#[inline(always)]
fn default() -> Apb2rstr {
Apb2rstr(0)
}
}
impl core::fmt::Debug for Apb2rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb2rstr")
.field("adcrst", &self.adcrst())
.field("tim1rst", &self.tim1rst())
.field("spi1rst", &self.spi1rst())
.field("usart1rst", &self.usart1rst())
.field("tim16rst", &self.tim16rst())
.field("tim17rst", &self.tim17rst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb2rstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb2rstr {{ adcrst: {=bool:?}, tim1rst: {=bool:?}, spi1rst: {=bool:?}, usart1rst: {=bool:?}, tim16rst: {=bool:?}, tim17rst: {=bool:?} }}" , self . adcrst () , self . tim1rst () , self . spi1rst () , self . usart1rst () , self . tim16rst () , self . tim17rst ())
}
}
#[doc = "APB2 peripheral clocks enable in Sleep mode register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb2smenr(pub u32);
impl Apb2smenr {
#[doc = "ADC clocks enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub const fn adcsmen(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "ADC clocks enable during CPU1 Csleep and CStop modes"]
#[inline(always)]
pub fn set_adcsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "TIM1 timer clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn tim1smen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 timer clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_tim1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn spi1smen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_spi1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1 clock enable during CPU1 Csleep and CStop modes."]
#[inline(always)]
pub const fn usart1smen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 clock enable during CPU1 Csleep and CStop modes."]
#[inline(always)]
pub fn set_usart1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM16 timer clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn tim16smen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_tim16smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM17 timer clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub const fn tim17smen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM17 timer clock enable during CPU1 CSleep mode."]
#[inline(always)]
pub fn set_tim17smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for Apb2smenr {
#[inline(always)]
fn default() -> Apb2smenr {
Apb2smenr(0)
}
}
impl core::fmt::Debug for Apb2smenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb2smenr")
.field("adcsmen", &self.adcsmen())
.field("tim1smen", &self.tim1smen())
.field("spi1smen", &self.spi1smen())
.field("usart1smen", &self.usart1smen())
.field("tim16smen", &self.tim16smen())
.field("tim17smen", &self.tim17smen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb2smenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb2smenr {{ adcsmen: {=bool:?}, tim1smen: {=bool:?}, spi1smen: {=bool:?}, usart1smen: {=bool:?}, tim16smen: {=bool:?}, tim17smen: {=bool:?} }}" , self . adcsmen () , self . tim1smen () , self . spi1smen () , self . usart1smen () , self . tim16smen () , self . tim17smen ())
}
}
#[doc = "APB3 peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb3enr(pub u32);
impl Apb3enr {
#[doc = "sub-GHz radio SPI clock enable"]
#[inline(always)]
pub const fn subghzspien(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "sub-GHz radio SPI clock enable"]
#[inline(always)]
pub fn set_subghzspien(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
}
impl Default for Apb3enr {
#[inline(always)]
fn default() -> Apb3enr {
Apb3enr(0)
}
}
impl core::fmt::Debug for Apb3enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb3enr")
.field("subghzspien", &self.subghzspien())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb3enr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Apb3enr {{ subghzspien: {=bool:?} }}", self.subghzspien())
}
}
#[doc = "APB3 peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb3rstr(pub u32);
impl Apb3rstr {
#[doc = "Sub-GHz radio SPI reset"]
#[inline(always)]
pub const fn subghzspirst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Sub-GHz radio SPI reset"]
#[inline(always)]
pub fn set_subghzspirst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
}
impl Default for Apb3rstr {
#[inline(always)]
fn default() -> Apb3rstr {
Apb3rstr(0)
}
}
impl core::fmt::Debug for Apb3rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb3rstr")
.field("subghzspirst", &self.subghzspirst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb3rstr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Apb3rstr {{ subghzspirst: {=bool:?} }}", self.subghzspirst())
}
}
#[doc = "APB3 peripheral clock enable in Sleep mode register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb3smenr(pub u32);
impl Apb3smenr {
#[doc = "Sub-GHz radio SPI clock enable during Sleep and Stop modes"]
#[inline(always)]
pub const fn subghzspismen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Sub-GHz radio SPI clock enable during Sleep and Stop modes"]
#[inline(always)]
pub fn set_subghzspismen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
}
impl Default for Apb3smenr {
#[inline(always)]
fn default() -> Apb3smenr {
Apb3smenr(0)
}
}
impl core::fmt::Debug for Apb3smenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb3smenr")
.field("subghzspismen", &self.subghzspismen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb3smenr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Apb3smenr {{ subghzspismen: {=bool:?} }}", self.subghzspismen())
}
}
#[doc = "Backup domain control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Bdcr(pub u32);
impl Bdcr {
#[doc = "LSE oscillator enable"]
#[inline(always)]
pub const fn lseon(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator enable"]
#[inline(always)]
pub fn set_lseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE oscillator ready"]
#[inline(always)]
pub const fn lserdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator ready"]
#[inline(always)]
pub fn set_lserdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "LSE oscillator bypass"]
#[inline(always)]
pub const fn lsebyp(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator bypass"]
#[inline(always)]
pub fn set_lsebyp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "LSE oscillator drive capability"]
#[inline(always)]
pub const fn lsedrv(&self) -> super::vals::Lsedrv {
let val = (self.0 >> 3usize) & 0x03;
super::vals::Lsedrv::from_bits(val as u8)
}
#[doc = "LSE oscillator drive capability"]
#[inline(always)]
pub fn set_lsedrv(&mut self, val: super::vals::Lsedrv) {
self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
}
#[doc = "CSS on LSE enable"]
#[inline(always)]
pub const fn lsecsson(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "CSS on LSE enable"]
#[inline(always)]
pub fn set_lsecsson(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "CSS on LSE failure Detection"]
#[inline(always)]
pub const fn lsecssd(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "CSS on LSE failure Detection"]
#[inline(always)]
pub fn set_lsecssd(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "LSE system clock enable"]
#[inline(always)]
pub const fn lsesysen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "LSE system clock enable"]
#[inline(always)]
pub fn set_lsesysen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "RTC clock source selection"]
#[inline(always)]
pub const fn rtcsel(&self) -> super::vals::Rtcsel {
let val = (self.0 >> 8usize) & 0x03;
super::vals::Rtcsel::from_bits(val as u8)
}
#[doc = "RTC clock source selection"]
#[inline(always)]
pub fn set_rtcsel(&mut self, val: super::vals::Rtcsel) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
}
#[doc = "LSE system clock ready"]
#[inline(always)]
pub const fn lsesysrdy(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "LSE system clock ready"]
#[inline(always)]
pub fn set_lsesysrdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "RTC clock enable"]
#[inline(always)]
pub const fn rtcen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "RTC clock enable"]
#[inline(always)]
pub fn set_rtcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "Backup domain software reset"]
#[inline(always)]
pub const fn bdrst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Backup domain software reset"]
#[inline(always)]
pub fn set_bdrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Low speed clock output enable"]
#[inline(always)]
pub const fn lscoen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Low speed clock output enable"]
#[inline(always)]
pub fn set_lscoen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Low speed clock output selection"]
#[inline(always)]
pub const fn lscosel(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Low speed clock output selection"]
#[inline(always)]
pub fn set_lscosel(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for Bdcr {
#[inline(always)]
fn default() -> Bdcr {
Bdcr(0)
}
}
impl core::fmt::Debug for Bdcr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Bdcr")
.field("lseon", &self.lseon())
.field("lserdy", &self.lserdy())
.field("lsebyp", &self.lsebyp())
.field("lsedrv", &self.lsedrv())
.field("lsecsson", &self.lsecsson())
.field("lsecssd", &self.lsecssd())
.field("lsesysen", &self.lsesysen())
.field("rtcsel", &self.rtcsel())
.field("lsesysrdy", &self.lsesysrdy())
.field("rtcen", &self.rtcen())
.field("bdrst", &self.bdrst())
.field("lscoen", &self.lscoen())
.field("lscosel", &self.lscosel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Bdcr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Bdcr {{ lseon: {=bool:?}, lserdy: {=bool:?}, lsebyp: {=bool:?}, lsedrv: {:?}, lsecsson: {=bool:?}, lsecssd: {=bool:?}, lsesysen: {=bool:?}, rtcsel: {:?}, lsesysrdy: {=bool:?}, rtcen: {=bool:?}, bdrst: {=bool:?}, lscoen: {=bool:?}, lscosel: {=bool:?} }}" , self . lseon () , self . lserdy () , self . lsebyp () , self . lsedrv () , self . lsecsson () , self . lsecssd () , self . lsesysen () , self . rtcsel () , self . lsesysrdy () , self . rtcen () , self . bdrst () , self . lscoen () , self . lscosel ())
}
}
#[doc = "CPU2 AHB1 peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2ahb1enr(pub u32);
impl C2ahb1enr {
#[doc = "CPU2 DMA1 clock enable"]
#[inline(always)]
pub const fn dma1en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "CPU2 DMA1 clock enable"]
#[inline(always)]
pub fn set_dma1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "CPU2 DMA2 clock enable"]
#[inline(always)]
pub const fn dma2en(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "CPU2 DMA2 clock enable"]
#[inline(always)]
pub fn set_dma2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "CPU2 DMAMUX1 clock enable"]
#[inline(always)]
pub const fn dmamux1en(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "CPU2 DMAMUX1 clock enable"]
#[inline(always)]
pub fn set_dmamux1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "CPU2 CRC clock enable"]
#[inline(always)]
pub const fn crcen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CPU2 CRC clock enable"]
#[inline(always)]
pub fn set_crcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
}
impl Default for C2ahb1enr {
#[inline(always)]
fn default() -> C2ahb1enr {
C2ahb1enr(0)
}
}
impl core::fmt::Debug for C2ahb1enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2ahb1enr")
.field("dma1en", &self.dma1en())
.field("dma2en", &self.dma2en())
.field("dmamux1en", &self.dmamux1en())
.field("crcen", &self.crcen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2ahb1enr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"C2ahb1enr {{ dma1en: {=bool:?}, dma2en: {=bool:?}, dmamux1en: {=bool:?}, crcen: {=bool:?} }}",
self.dma1en(),
self.dma2en(),
self.dmamux1en(),
self.crcen()
)
}
}
#[doc = "CPU2 AHB1 peripheral clocks enable in Sleep modes register \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2ahb1smenr(pub u32);
impl C2ahb1smenr {
#[doc = "DMA1 clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn dma1smen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "DMA1 clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_dma1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "DMA2 clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn dma2smen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "DMA2 clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_dma2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "DMAMUX1 clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn dmamux1smen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "DMAMUX1 clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_dmamux1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "CRC clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn crcsmen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_crcsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
}
impl Default for C2ahb1smenr {
#[inline(always)]
fn default() -> C2ahb1smenr {
C2ahb1smenr(0)
}
}
impl core::fmt::Debug for C2ahb1smenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2ahb1smenr")
.field("dma1smen", &self.dma1smen())
.field("dma2smen", &self.dma2smen())
.field("dmamux1smen", &self.dmamux1smen())
.field("crcsmen", &self.crcsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2ahb1smenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "C2ahb1smenr {{ dma1smen: {=bool:?}, dma2smen: {=bool:?}, dmamux1smen: {=bool:?}, crcsmen: {=bool:?} }}" , self . dma1smen () , self . dma2smen () , self . dmamux1smen () , self . crcsmen ())
}
}
#[doc = "CPU2 AHB2 peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2ahb2enr(pub u32);
impl C2ahb2enr {
#[doc = "CPU2 IO port A clock enable"]
#[inline(always)]
pub const fn gpioaen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "CPU2 IO port A clock enable"]
#[inline(always)]
pub fn set_gpioaen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "CPU2 IO port B clock enable"]
#[inline(always)]
pub const fn gpioben(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "CPU2 IO port B clock enable"]
#[inline(always)]
pub fn set_gpioben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "CPU2 IO port C clock enable"]
#[inline(always)]
pub const fn gpiocen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "CPU2 IO port C clock enable"]
#[inline(always)]
pub fn set_gpiocen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "CPU2 IO port H clock enable"]
#[inline(always)]
pub const fn gpiohen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "CPU2 IO port H clock enable"]
#[inline(always)]
pub fn set_gpiohen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
}
impl Default for C2ahb2enr {
#[inline(always)]
fn default() -> C2ahb2enr {
C2ahb2enr(0)
}
}
impl core::fmt::Debug for C2ahb2enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2ahb2enr")
.field("gpioaen", &self.gpioaen())
.field("gpioben", &self.gpioben())
.field("gpiocen", &self.gpiocen())
.field("gpiohen", &self.gpiohen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2ahb2enr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"C2ahb2enr {{ gpioaen: {=bool:?}, gpioben: {=bool:?}, gpiocen: {=bool:?}, gpiohen: {=bool:?} }}",
self.gpioaen(),
self.gpioben(),
self.gpiocen(),
self.gpiohen()
)
}
}
#[doc = "CPU2 AHB2 peripheral clocks enable in Sleep modes register \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2ahb2smenr(pub u32);
impl C2ahb2smenr {
#[doc = "IO port A clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn gpioasmen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "IO port A clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_gpioasmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "IO port B clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn gpiobsmen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "IO port B clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_gpiobsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "IO port C clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn gpiocsmen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "IO port C clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_gpiocsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "IO port H clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn gpiohsmen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "IO port H clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_gpiohsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
}
impl Default for C2ahb2smenr {
#[inline(always)]
fn default() -> C2ahb2smenr {
C2ahb2smenr(0)
}
}
impl core::fmt::Debug for C2ahb2smenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2ahb2smenr")
.field("gpioasmen", &self.gpioasmen())
.field("gpiobsmen", &self.gpiobsmen())
.field("gpiocsmen", &self.gpiocsmen())
.field("gpiohsmen", &self.gpiohsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2ahb2smenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "C2ahb2smenr {{ gpioasmen: {=bool:?}, gpiobsmen: {=bool:?}, gpiocsmen: {=bool:?}, gpiohsmen: {=bool:?} }}" , self . gpioasmen () , self . gpiobsmen () , self . gpiocsmen () , self . gpiohsmen ())
}
}
#[doc = "CPU2 AHB3 peripheral clock enable register \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2ahb3enr(pub u32);
impl C2ahb3enr {
#[doc = "CPU2 PKA accelerator clock enable"]
#[inline(always)]
pub const fn pkaen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "CPU2 PKA accelerator clock enable"]
#[inline(always)]
pub fn set_pkaen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "CPU2 AES accelerator clock enable"]
#[inline(always)]
pub const fn aesen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "CPU2 AES accelerator clock enable"]
#[inline(always)]
pub fn set_aesen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "CPU2 True RNG clocks enable"]
#[inline(always)]
pub const fn rngen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "CPU2 True RNG clocks enable"]
#[inline(always)]
pub fn set_rngen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "CPU2 HSEM clock enable"]
#[inline(always)]
pub const fn hsemen(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "CPU2 HSEM clock enable"]
#[inline(always)]
pub fn set_hsemen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "CPU2 IPCC interface clock enable"]
#[inline(always)]
pub const fn ipccen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "CPU2 IPCC interface clock enable"]
#[inline(always)]
pub fn set_ipccen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "CPU2 Flash interface clock enable"]
#[inline(always)]
pub const fn flashen(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "CPU2 Flash interface clock enable"]
#[inline(always)]
pub fn set_flashen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for C2ahb3enr {
#[inline(always)]
fn default() -> C2ahb3enr {
C2ahb3enr(0)
}
}
impl core::fmt::Debug for C2ahb3enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2ahb3enr")
.field("pkaen", &self.pkaen())
.field("aesen", &self.aesen())
.field("rngen", &self.rngen())
.field("hsemen", &self.hsemen())
.field("ipccen", &self.ipccen())
.field("flashen", &self.flashen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2ahb3enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "C2ahb3enr {{ pkaen: {=bool:?}, aesen: {=bool:?}, rngen: {=bool:?}, hsemen: {=bool:?}, ipccen: {=bool:?}, flashen: {=bool:?} }}" , self . pkaen () , self . aesen () , self . rngen () , self . hsemen () , self . ipccen () , self . flashen ())
}
}
#[doc = "CPU2 AHB3 peripheral clocks enable in Sleep mode register \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2ahb3smenr(pub u32);
impl C2ahb3smenr {
#[doc = "PKA accelerator clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn pkasmen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "PKA accelerator clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_pkasmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "AES accelerator clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn aessmen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "AES accelerator clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_aessmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "True RNG clock enable during CPU2 CSleep and CStop mode."]
#[inline(always)]
pub const fn rngsmen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "True RNG clock enable during CPU2 CSleep and CStop mode."]
#[inline(always)]
pub fn set_rngsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "SRAM1 interface clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn sram1smen(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "SRAM1 interface clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_sram1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "SRAM2 memory interface clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn sram2smen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "SRAM2 memory interface clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_sram2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Flash interface clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn flashsmen(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Flash interface clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_flashsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for C2ahb3smenr {
#[inline(always)]
fn default() -> C2ahb3smenr {
C2ahb3smenr(0)
}
}
impl core::fmt::Debug for C2ahb3smenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2ahb3smenr")
.field("pkasmen", &self.pkasmen())
.field("aessmen", &self.aessmen())
.field("rngsmen", &self.rngsmen())
.field("sram1smen", &self.sram1smen())
.field("sram2smen", &self.sram2smen())
.field("flashsmen", &self.flashsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2ahb3smenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "C2ahb3smenr {{ pkasmen: {=bool:?}, aessmen: {=bool:?}, rngsmen: {=bool:?}, sram1smen: {=bool:?}, sram2smen: {=bool:?}, flashsmen: {=bool:?} }}" , self . pkasmen () , self . aessmen () , self . rngsmen () , self . sram1smen () , self . sram2smen () , self . flashsmen ())
}
}
#[doc = "CPU2 APB1 peripheral clock enable register 1 \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2apb1enr1(pub u32);
impl C2apb1enr1 {
#[doc = "CPU2 TIM2 timer clock enable"]
#[inline(always)]
pub const fn tim2en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "CPU2 TIM2 timer clock enable"]
#[inline(always)]
pub fn set_tim2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "CPU2 RTC APB clock enable"]
#[inline(always)]
pub const fn rtcapben(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "CPU2 RTC APB clock enable"]
#[inline(always)]
pub fn set_rtcapben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "CPU2 SPI2 clock enable"]
#[inline(always)]
pub const fn spi2en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "CPU2 SPI2 clock enable"]
#[inline(always)]
pub fn set_spi2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "CPU2 USART2 clock enable"]
#[inline(always)]
pub const fn usart2en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "CPU2 USART2 clock enable"]
#[inline(always)]
pub fn set_usart2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "CPU2 I2C1 clocks enable"]
#[inline(always)]
pub const fn i2c1en(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "CPU2 I2C1 clocks enable"]
#[inline(always)]
pub fn set_i2c1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "CPU2 I2C2 clocks enable"]
#[inline(always)]
pub const fn i2c2en(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "CPU2 I2C2 clocks enable"]
#[inline(always)]
pub fn set_i2c2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "CPU2 I2C3 clocks enable"]
#[inline(always)]
pub const fn i2c3en(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "CPU2 I2C3 clocks enable"]
#[inline(always)]
pub fn set_i2c3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "CPU2 DAC clock enable"]
#[inline(always)]
pub const fn dacen(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "CPU2 DAC clock enable"]
#[inline(always)]
pub fn set_dacen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "CPU2 Low power timer 1 clocks enable"]
#[inline(always)]
pub const fn lptim1en(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "CPU2 Low power timer 1 clocks enable"]
#[inline(always)]
pub fn set_lptim1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for C2apb1enr1 {
#[inline(always)]
fn default() -> C2apb1enr1 {
C2apb1enr1(0)
}
}
impl core::fmt::Debug for C2apb1enr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2apb1enr1")
.field("tim2en", &self.tim2en())
.field("rtcapben", &self.rtcapben())
.field("spi2en", &self.spi2en())
.field("usart2en", &self.usart2en())
.field("i2c1en", &self.i2c1en())
.field("i2c2en", &self.i2c2en())
.field("i2c3en", &self.i2c3en())
.field("dacen", &self.dacen())
.field("lptim1en", &self.lptim1en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2apb1enr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "C2apb1enr1 {{ tim2en: {=bool:?}, rtcapben: {=bool:?}, spi2en: {=bool:?}, usart2en: {=bool:?}, i2c1en: {=bool:?}, i2c2en: {=bool:?}, i2c3en: {=bool:?}, dacen: {=bool:?}, lptim1en: {=bool:?} }}" , self . tim2en () , self . rtcapben () , self . spi2en () , self . usart2en () , self . i2c1en () , self . i2c2en () , self . i2c3en () , self . dacen () , self . lptim1en ())
}
}
#[doc = "CPU2 APB1 peripheral clock enable register 2 \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2apb1enr2(pub u32);
impl C2apb1enr2 {
#[doc = "CPU2 Low power UART 1 clocks enable"]
#[inline(always)]
pub const fn lpuart1en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "CPU2 Low power UART 1 clocks enable"]
#[inline(always)]
pub fn set_lpuart1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "CPU2 Low power timer 2 clocks enable"]
#[inline(always)]
pub const fn lptim2en(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "CPU2 Low power timer 2 clocks enable"]
#[inline(always)]
pub fn set_lptim2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "CPU2 Low power timer 3 clocks enable"]
#[inline(always)]
pub const fn lptim3en(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "CPU2 Low power timer 3 clocks enable"]
#[inline(always)]
pub fn set_lptim3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
}
impl Default for C2apb1enr2 {
#[inline(always)]
fn default() -> C2apb1enr2 {
C2apb1enr2(0)
}
}
impl core::fmt::Debug for C2apb1enr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2apb1enr2")
.field("lpuart1en", &self.lpuart1en())
.field("lptim2en", &self.lptim2en())
.field("lptim3en", &self.lptim3en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2apb1enr2 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"C2apb1enr2 {{ lpuart1en: {=bool:?}, lptim2en: {=bool:?}, lptim3en: {=bool:?} }}",
self.lpuart1en(),
self.lptim2en(),
self.lptim3en()
)
}
}
#[doc = "CPU2 APB1 peripheral clocks enable in Sleep mode register 1 \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2apb1smenr1(pub u32);
impl C2apb1smenr1 {
#[doc = "TIM2 timer clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn tim2smen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 timer clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_tim2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "RTC bus clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn rtcapbsmen(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "RTC bus clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_rtcapbsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "SPI2 clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn spi2smen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_spi2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "USART2 clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn usart2smen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_usart2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "I2C1 clock enable during CPU2 CSleep and CStop modes"]
#[inline(always)]
pub const fn i2c1smen(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 clock enable during CPU2 CSleep and CStop modes"]
#[inline(always)]
pub fn set_i2c1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 clock enable during CPU2 CSleep and CStop modes"]
#[inline(always)]
pub const fn i2c2smen(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 clock enable during CPU2 CSleep and CStop modes"]
#[inline(always)]
pub fn set_i2c2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "I2C3 clock enable during CPU2 CSleep and CStop modes"]
#[inline(always)]
pub const fn i2c3smen(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "I2C3 clock enable during CPU2 CSleep and CStop modes"]
#[inline(always)]
pub fn set_i2c3smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "DAC clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub const fn dacsmen(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "DAC clock enable during CPU2 CSleep mode."]
#[inline(always)]
pub fn set_dacsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Low power timer 1 clock enable during CPU2 CSleep and CStop mode"]
#[inline(always)]
pub const fn lptim1smen(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Low power timer 1 clock enable during CPU2 CSleep and CStop mode"]
#[inline(always)]
pub fn set_lptim1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for C2apb1smenr1 {
#[inline(always)]
fn default() -> C2apb1smenr1 {
C2apb1smenr1(0)
}
}
impl core::fmt::Debug for C2apb1smenr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2apb1smenr1")
.field("tim2smen", &self.tim2smen())
.field("rtcapbsmen", &self.rtcapbsmen())
.field("spi2smen", &self.spi2smen())
.field("usart2smen", &self.usart2smen())
.field("i2c1smen", &self.i2c1smen())
.field("i2c2smen", &self.i2c2smen())
.field("i2c3smen", &self.i2c3smen())
.field("dacsmen", &self.dacsmen())
.field("lptim1smen", &self.lptim1smen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2apb1smenr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "C2apb1smenr1 {{ tim2smen: {=bool:?}, rtcapbsmen: {=bool:?}, spi2smen: {=bool:?}, usart2smen: {=bool:?}, i2c1smen: {=bool:?}, i2c2smen: {=bool:?}, i2c3smen: {=bool:?}, dacsmen: {=bool:?}, lptim1smen: {=bool:?} }}" , self . tim2smen () , self . rtcapbsmen () , self . spi2smen () , self . usart2smen () , self . i2c1smen () , self . i2c2smen () , self . i2c3smen () , self . dacsmen () , self . lptim1smen ())
}
}
#[doc = "CPU2 APB1 peripheral clocks enable in Sleep mode register 2 \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2apb1smenr2(pub u32);
impl C2apb1smenr2 {
#[doc = "Low power UART 1 clock enable during CPU2 CSleep and CStop mode"]
#[inline(always)]
pub const fn lpuart1smen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Low power UART 1 clock enable during CPU2 CSleep and CStop mode"]
#[inline(always)]
pub fn set_lpuart1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Low power timer 2 clocks enable during CPU2 CSleep and CStop modes."]
#[inline(always)]
pub const fn lptim2smen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Low power timer 2 clocks enable during CPU2 CSleep and CStop modes."]
#[inline(always)]
pub fn set_lptim2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Low power timer 3 clocks enable during CPU2 CSleep and CStop modes."]
#[inline(always)]
pub const fn lptim3smen(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "Low power timer 3 clocks enable during CPU2 CSleep and CStop modes."]
#[inline(always)]
pub fn set_lptim3smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
}
impl Default for C2apb1smenr2 {
#[inline(always)]
fn default() -> C2apb1smenr2 {
C2apb1smenr2(0)
}
}
impl core::fmt::Debug for C2apb1smenr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2apb1smenr2")
.field("lpuart1smen", &self.lpuart1smen())
.field("lptim2smen", &self.lptim2smen())
.field("lptim3smen", &self.lptim3smen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2apb1smenr2 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"C2apb1smenr2 {{ lpuart1smen: {=bool:?}, lptim2smen: {=bool:?}, lptim3smen: {=bool:?} }}",
self.lpuart1smen(),
self.lptim2smen(),
self.lptim3smen()
)
}
}
#[doc = "CPU2 APB2 peripheral clock enable register \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2apb2enr(pub u32);
impl C2apb2enr {
#[doc = "ADC clocks enable"]
#[inline(always)]
pub const fn adcen(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "ADC clocks enable"]
#[inline(always)]
pub fn set_adcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "CPU2 TIM1 timer clock enable"]
#[inline(always)]
pub const fn tim1en(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "CPU2 TIM1 timer clock enable"]
#[inline(always)]
pub fn set_tim1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "CPU2 SPI1 clock enable"]
#[inline(always)]
pub const fn spi1en(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CPU2 SPI1 clock enable"]
#[inline(always)]
pub fn set_spi1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "CPU2 USART1clocks enable"]
#[inline(always)]
pub const fn usart1en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "CPU2 USART1clocks enable"]
#[inline(always)]
pub fn set_usart1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "CPU2 TIM16 timer clock enable"]
#[inline(always)]
pub const fn tim16en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "CPU2 TIM16 timer clock enable"]
#[inline(always)]
pub fn set_tim16en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "CPU2 TIM17 timer clock enable"]
#[inline(always)]
pub const fn tim17en(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "CPU2 TIM17 timer clock enable"]
#[inline(always)]
pub fn set_tim17en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for C2apb2enr {
#[inline(always)]
fn default() -> C2apb2enr {
C2apb2enr(0)
}
}
impl core::fmt::Debug for C2apb2enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2apb2enr")
.field("adcen", &self.adcen())
.field("tim1en", &self.tim1en())
.field("spi1en", &self.spi1en())
.field("usart1en", &self.usart1en())
.field("tim16en", &self.tim16en())
.field("tim17en", &self.tim17en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2apb2enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "C2apb2enr {{ adcen: {=bool:?}, tim1en: {=bool:?}, spi1en: {=bool:?}, usart1en: {=bool:?}, tim16en: {=bool:?}, tim17en: {=bool:?} }}" , self . adcen () , self . tim1en () , self . spi1en () , self . usart1en () , self . tim16en () , self . tim17en ())
}
}
#[doc = "CPU2 APB2 peripheral clocks enable in Sleep mode register \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2apb2smenr(pub u32);
impl C2apb2smenr {
#[doc = "ADC clocks enable during CPU2 Csleep and CStop modes"]
#[inline(always)]
pub const fn adcsmen(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "ADC clocks enable during CPU2 Csleep and CStop modes"]
#[inline(always)]
pub fn set_adcsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "TIM1 timer clock enable during CPU2 CSleep mode"]
#[inline(always)]
pub const fn tim1smen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 timer clock enable during CPU2 CSleep mode"]
#[inline(always)]
pub fn set_tim1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 clock enable during CPU2 CSleep mode"]
#[inline(always)]
pub const fn spi1smen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 clock enable during CPU2 CSleep mode"]
#[inline(always)]
pub fn set_spi1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1clock enable during CPU2 CSleep and CStop mode"]
#[inline(always)]
pub const fn usart1smen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1clock enable during CPU2 CSleep and CStop mode"]
#[inline(always)]
pub fn set_usart1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM16 timer clock enable during CPU2 CSleep mode"]
#[inline(always)]
pub const fn tim16smen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer clock enable during CPU2 CSleep mode"]
#[inline(always)]
pub fn set_tim16smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM17 timer clock enable during CPU2 CSleep mode"]
#[inline(always)]
pub const fn tim17smen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM17 timer clock enable during CPU2 CSleep mode"]
#[inline(always)]
pub fn set_tim17smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for C2apb2smenr {
#[inline(always)]
fn default() -> C2apb2smenr {
C2apb2smenr(0)
}
}
impl core::fmt::Debug for C2apb2smenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2apb2smenr")
.field("adcsmen", &self.adcsmen())
.field("tim1smen", &self.tim1smen())
.field("spi1smen", &self.spi1smen())
.field("usart1smen", &self.usart1smen())
.field("tim16smen", &self.tim16smen())
.field("tim17smen", &self.tim17smen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2apb2smenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "C2apb2smenr {{ adcsmen: {=bool:?}, tim1smen: {=bool:?}, spi1smen: {=bool:?}, usart1smen: {=bool:?}, tim16smen: {=bool:?}, tim17smen: {=bool:?} }}" , self . adcsmen () , self . tim1smen () , self . spi1smen () , self . usart1smen () , self . tim16smen () , self . tim17smen ())
}
}
#[doc = "CPU2 APB3 peripheral clock enable register \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2apb3enr(pub u32);
impl C2apb3enr {
#[doc = "CPU2 sub-GHz radio SPI clock enable"]
#[inline(always)]
pub const fn subghzspien(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "CPU2 sub-GHz radio SPI clock enable"]
#[inline(always)]
pub fn set_subghzspien(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
}
impl Default for C2apb3enr {
#[inline(always)]
fn default() -> C2apb3enr {
C2apb3enr(0)
}
}
impl core::fmt::Debug for C2apb3enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2apb3enr")
.field("subghzspien", &self.subghzspien())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2apb3enr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "C2apb3enr {{ subghzspien: {=bool:?} }}", self.subghzspien())
}
}
#[doc = "CPU2 APB3 peripheral clock enable in Sleep mode register \\[dual core device only\\]"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct C2apb3smenr(pub u32);
impl C2apb3smenr {
#[doc = "sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes"]
#[inline(always)]
pub const fn subghzspismen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes"]
#[inline(always)]
pub fn set_subghzspismen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
}
impl Default for C2apb3smenr {
#[inline(always)]
fn default() -> C2apb3smenr {
C2apb3smenr(0)
}
}
impl core::fmt::Debug for C2apb3smenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("C2apb3smenr")
.field("subghzspismen", &self.subghzspismen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for C2apb3smenr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "C2apb3smenr {{ subghzspismen: {=bool:?} }}", self.subghzspismen())
}
}
#[doc = "Peripherals independent clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ccipr(pub u32);
impl Ccipr {
#[doc = "USART1 clock source selection"]
#[inline(always)]
pub const fn usart1sel(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x03;
val as u8
}
#[doc = "USART1 clock source selection"]
#[inline(always)]
pub fn set_usart1sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
}
#[doc = "USART2 clock source selection"]
#[inline(always)]
pub const fn usart2sel(&self) -> u8 {
let val = (self.0 >> 2usize) & 0x03;
val as u8
}
#[doc = "USART2 clock source selection"]
#[inline(always)]
pub fn set_usart2sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize);
}
#[doc = "SPI2 I2S clock source selection"]
#[inline(always)]
pub const fn spi2sel(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x03;
val as u8
}
#[doc = "SPI2 I2S clock source selection"]
#[inline(always)]
pub fn set_spi2sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
}
#[doc = "LPUART1 clock source selection"]
#[inline(always)]
pub const fn lpuart1sel(&self) -> u8 {
let val = (self.0 >> 10usize) & 0x03;
val as u8
}
#[doc = "LPUART1 clock source selection"]
#[inline(always)]
pub fn set_lpuart1sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
}
#[doc = "I2C1 clock source selection"]
#[inline(always)]
pub const fn i2c1sel(&self) -> u8 {
let val = (self.0 >> 12usize) & 0x03;
val as u8
}
#[doc = "I2C1 clock source selection"]
#[inline(always)]
pub fn set_i2c1sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 12usize)) | (((val as u32) & 0x03) << 12usize);
}
#[doc = "I2C2 clock source selection"]
#[inline(always)]
pub const fn i2c2sel(&self) -> u8 {
let val = (self.0 >> 14usize) & 0x03;
val as u8
}
#[doc = "I2C2 clock source selection"]
#[inline(always)]
pub fn set_i2c2sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize);
}
#[doc = "I2C3 clock source selection"]
#[inline(always)]
pub const fn i2c3sel(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x03;
val as u8
}
#[doc = "I2C3 clock source selection"]
#[inline(always)]
pub fn set_i2c3sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
}
#[doc = "Low power timer 1 clock source selection"]
#[inline(always)]
pub const fn lptim1sel(&self) -> u8 {
let val = (self.0 >> 18usize) & 0x03;
val as u8
}
#[doc = "Low power timer 1 clock source selection"]
#[inline(always)]
pub fn set_lptim1sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 18usize)) | (((val as u32) & 0x03) << 18usize);
}
#[doc = "Low power timer 2 clock source selection"]
#[inline(always)]
pub const fn lptim2sel(&self) -> u8 {
let val = (self.0 >> 20usize) & 0x03;
val as u8
}
#[doc = "Low power timer 2 clock source selection"]
#[inline(always)]
pub fn set_lptim2sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
}
#[doc = "Low power timer 3 clock source selection"]
#[inline(always)]
pub const fn lptim3sel(&self) -> u8 {
let val = (self.0 >> 22usize) & 0x03;
val as u8
}
#[doc = "Low power timer 3 clock source selection"]
#[inline(always)]
pub fn set_lptim3sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 22usize)) | (((val as u32) & 0x03) << 22usize);
}
#[doc = "ADC clock source selection"]
#[inline(always)]
pub const fn adcsel(&self) -> super::vals::Adcsel {
let val = (self.0 >> 28usize) & 0x03;
super::vals::Adcsel::from_bits(val as u8)
}
#[doc = "ADC clock source selection"]
#[inline(always)]
pub fn set_adcsel(&mut self, val: super::vals::Adcsel) {
self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize);
}
#[doc = "RNG clock source selection"]
#[inline(always)]
pub const fn rngsel(&self) -> super::vals::Rngsel {
let val = (self.0 >> 30usize) & 0x03;
super::vals::Rngsel::from_bits(val as u8)
}
#[doc = "RNG clock source selection"]
#[inline(always)]
pub fn set_rngsel(&mut self, val: super::vals::Rngsel) {
self.0 = (self.0 & !(0x03 << 30usize)) | (((val.to_bits() as u32) & 0x03) << 30usize);
}
}
impl Default for Ccipr {
#[inline(always)]
fn default() -> Ccipr {
Ccipr(0)
}
}
impl core::fmt::Debug for Ccipr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ccipr")
.field("usart1sel", &self.usart1sel())
.field("usart2sel", &self.usart2sel())
.field("spi2sel", &self.spi2sel())
.field("lpuart1sel", &self.lpuart1sel())
.field("i2c1sel", &self.i2c1sel())
.field("i2c2sel", &self.i2c2sel())
.field("i2c3sel", &self.i2c3sel())
.field("lptim1sel", &self.lptim1sel())
.field("lptim2sel", &self.lptim2sel())
.field("lptim3sel", &self.lptim3sel())
.field("adcsel", &self.adcsel())
.field("rngsel", &self.rngsel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ccipr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ccipr {{ usart1sel: {=u8:?}, usart2sel: {=u8:?}, spi2sel: {=u8:?}, lpuart1sel: {=u8:?}, i2c1sel: {=u8:?}, i2c2sel: {=u8:?}, i2c3sel: {=u8:?}, lptim1sel: {=u8:?}, lptim2sel: {=u8:?}, lptim3sel: {=u8:?}, adcsel: {:?}, rngsel: {:?} }}" , self . usart1sel () , self . usart2sel () , self . spi2sel () , self . lpuart1sel () , self . i2c1sel () , self . i2c2sel () , self . i2c3sel () , self . lptim1sel () , self . lptim2sel () , self . lptim3sel () , self . adcsel () , self . rngsel ())
}
}
#[doc = "Clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfgr(pub u32);
impl Cfgr {
#[doc = "System clock switch"]
#[inline(always)]
pub const fn sw(&self) -> super::vals::Sw {
let val = (self.0 >> 0usize) & 0x03;
super::vals::Sw::from_bits(val as u8)
}
#[doc = "System clock switch"]
#[inline(always)]
pub fn set_sw(&mut self, val: super::vals::Sw) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "System clock switch status"]
#[inline(always)]
pub const fn sws(&self) -> super::vals::Sw {
let val = (self.0 >> 2usize) & 0x03;
super::vals::Sw::from_bits(val as u8)
}
#[doc = "System clock switch status"]
#[inline(always)]
pub fn set_sws(&mut self, val: super::vals::Sw) {
self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
}
#[doc = "HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)"]
#[inline(always)]
pub const fn hpre(&self) -> super::vals::Hpre {
let val = (self.0 >> 4usize) & 0x0f;
super::vals::Hpre::from_bits(val as u8)
}
#[doc = "HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)"]
#[inline(always)]
pub fn set_hpre(&mut self, val: super::vals::Hpre) {
self.0 = (self.0 & !(0x0f << 4usize)) | (((val.to_bits() as u32) & 0x0f) << 4usize);
}
#[doc = "PCLK1 low-speed prescaler (APB1)"]
#[inline(always)]
pub const fn ppre1(&self) -> super::vals::Ppre {
let val = (self.0 >> 8usize) & 0x07;
super::vals::Ppre::from_bits(val as u8)
}
#[doc = "PCLK1 low-speed prescaler (APB1)"]
#[inline(always)]
pub fn set_ppre1(&mut self, val: super::vals::Ppre) {
self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
}
#[doc = "PCLK2 high-speed prescaler (APB2)"]
#[inline(always)]
pub const fn ppre2(&self) -> super::vals::Ppre {
let val = (self.0 >> 11usize) & 0x07;
super::vals::Ppre::from_bits(val as u8)
}
#[doc = "PCLK2 high-speed prescaler (APB2)"]
#[inline(always)]
pub fn set_ppre2(&mut self, val: super::vals::Ppre) {
self.0 = (self.0 & !(0x07 << 11usize)) | (((val.to_bits() as u32) & 0x07) << 11usize);
}
#[doc = "Wakeup from Stop and CSS backup clock selection"]
#[inline(always)]
pub const fn stopwuck(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "Wakeup from Stop and CSS backup clock selection"]
#[inline(always)]
pub fn set_stopwuck(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)"]
#[inline(always)]
pub const fn hpref(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)"]
#[inline(always)]
pub fn set_hpref(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "PCLK1 prescaler flag (APB1)"]
#[inline(always)]
pub const fn ppre1f(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "PCLK1 prescaler flag (APB1)"]
#[inline(always)]
pub fn set_ppre1f(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "PCLK2 prescaler flag (APB2)"]
#[inline(always)]
pub const fn ppre2f(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "PCLK2 prescaler flag (APB2)"]
#[inline(always)]
pub fn set_ppre2f(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "Microcontroller clock output"]
#[inline(always)]
pub const fn mcosel(&self) -> super::vals::Mcosel {
let val = (self.0 >> 24usize) & 0x0f;
super::vals::Mcosel::from_bits(val as u8)
}
#[doc = "Microcontroller clock output"]
#[inline(always)]
pub fn set_mcosel(&mut self, val: super::vals::Mcosel) {
self.0 = (self.0 & !(0x0f << 24usize)) | (((val.to_bits() as u32) & 0x0f) << 24usize);
}
#[doc = "Microcontroller clock output prescaler"]
#[inline(always)]
pub const fn mcopre(&self) -> super::vals::Mcopre {
let val = (self.0 >> 28usize) & 0x07;
super::vals::Mcopre::from_bits(val as u8)
}
#[doc = "Microcontroller clock output prescaler"]
#[inline(always)]
pub fn set_mcopre(&mut self, val: super::vals::Mcopre) {
self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize);
}
}
impl Default for Cfgr {
#[inline(always)]
fn default() -> Cfgr {
Cfgr(0)
}
}
impl core::fmt::Debug for Cfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cfgr")
.field("sw", &self.sw())
.field("sws", &self.sws())
.field("hpre", &self.hpre())
.field("ppre1", &self.ppre1())
.field("ppre2", &self.ppre2())
.field("stopwuck", &self.stopwuck())
.field("hpref", &self.hpref())
.field("ppre1f", &self.ppre1f())
.field("ppre2f", &self.ppre2f())
.field("mcosel", &self.mcosel())
.field("mcopre", &self.mcopre())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cfgr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cfgr {{ sw: {:?}, sws: {:?}, hpre: {:?}, ppre1: {:?}, ppre2: {:?}, stopwuck: {=bool:?}, hpref: {=bool:?}, ppre1f: {=bool:?}, ppre2f: {=bool:?}, mcosel: {:?}, mcopre: {:?} }}" , self . sw () , self . sws () , self . hpre () , self . ppre1 () , self . ppre2 () , self . stopwuck () , self . hpref () , self . ppre1f () , self . ppre2f () , self . mcosel () , self . mcopre ())
}
}
#[doc = "Clock interrupt clear register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cicr(pub u32);
impl Cicr {
#[doc = "LSI ready interrupt clear"]
#[inline(always)]
pub const fn lsirdyc(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt clear"]
#[inline(always)]
pub fn set_lsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt clear"]
#[inline(always)]
pub const fn lserdyc(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt clear"]
#[inline(always)]
pub fn set_lserdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "MSI ready interrupt clear"]
#[inline(always)]
pub const fn msirdyc(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "MSI ready interrupt clear"]
#[inline(always)]
pub fn set_msirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "HSI ready interrupt clear"]
#[inline(always)]
pub const fn hsirdyc(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt clear"]
#[inline(always)]
pub fn set_hsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt clear"]
#[inline(always)]
pub const fn hserdyc(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt clear"]
#[inline(always)]
pub fn set_hserdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "PLL ready interrupt clear"]
#[inline(always)]
pub const fn pllrdyc(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "PLL ready interrupt clear"]
#[inline(always)]
pub fn set_pllrdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "HSE Clock security system interrupt clear"]
#[inline(always)]
pub const fn cssc(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "HSE Clock security system interrupt clear"]
#[inline(always)]
pub fn set_cssc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "LSE Clock security system interrupt clear"]
#[inline(always)]
pub const fn lsecssc(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LSE Clock security system interrupt clear"]
#[inline(always)]
pub fn set_lsecssc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
}
impl Default for Cicr {
#[inline(always)]
fn default() -> Cicr {
Cicr(0)
}
}
impl core::fmt::Debug for Cicr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cicr")
.field("lsirdyc", &self.lsirdyc())
.field("lserdyc", &self.lserdyc())
.field("msirdyc", &self.msirdyc())
.field("hsirdyc", &self.hsirdyc())
.field("hserdyc", &self.hserdyc())
.field("pllrdyc", &self.pllrdyc())
.field("cssc", &self.cssc())
.field("lsecssc", &self.lsecssc())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cicr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cicr {{ lsirdyc: {=bool:?}, lserdyc: {=bool:?}, msirdyc: {=bool:?}, hsirdyc: {=bool:?}, hserdyc: {=bool:?}, pllrdyc: {=bool:?}, cssc: {=bool:?}, lsecssc: {=bool:?} }}" , self . lsirdyc () , self . lserdyc () , self . msirdyc () , self . hsirdyc () , self . hserdyc () , self . pllrdyc () , self . cssc () , self . lsecssc ())
}
}
#[doc = "Clock interrupt enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cier(pub u32);
impl Cier {
#[doc = "LSI ready interrupt enable"]
#[inline(always)]
pub const fn lsirdyie(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt enable"]
#[inline(always)]
pub fn set_lsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt enable"]
#[inline(always)]
pub const fn lserdyie(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt enable"]
#[inline(always)]
pub fn set_lserdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "MSI ready interrupt enable"]
#[inline(always)]
pub const fn msirdyie(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "MSI ready interrupt enable"]
#[inline(always)]
pub fn set_msirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "HSI ready interrupt enable"]
#[inline(always)]
pub const fn hsirdyie(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt enable"]
#[inline(always)]
pub fn set_hsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt enable"]
#[inline(always)]
pub const fn hserdyie(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt enable"]
#[inline(always)]
pub fn set_hserdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "PLL ready interrupt enable"]
#[inline(always)]
pub const fn pllrdyie(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "PLL ready interrupt enable"]
#[inline(always)]
pub fn set_pllrdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "LSE clock security system interrupt enable"]
#[inline(always)]
pub const fn lsecssie(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LSE clock security system interrupt enable"]
#[inline(always)]
pub fn set_lsecssie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
}
impl Default for Cier {
#[inline(always)]
fn default() -> Cier {
Cier(0)
}
}
impl core::fmt::Debug for Cier {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cier")
.field("lsirdyie", &self.lsirdyie())
.field("lserdyie", &self.lserdyie())
.field("msirdyie", &self.msirdyie())
.field("hsirdyie", &self.hsirdyie())
.field("hserdyie", &self.hserdyie())
.field("pllrdyie", &self.pllrdyie())
.field("lsecssie", &self.lsecssie())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cier {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cier {{ lsirdyie: {=bool:?}, lserdyie: {=bool:?}, msirdyie: {=bool:?}, hsirdyie: {=bool:?}, hserdyie: {=bool:?}, pllrdyie: {=bool:?}, lsecssie: {=bool:?} }}" , self . lsirdyie () , self . lserdyie () , self . msirdyie () , self . hsirdyie () , self . hserdyie () , self . pllrdyie () , self . lsecssie ())
}
}
#[doc = "Clock interrupt flag register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cifr(pub u32);
impl Cifr {
#[doc = "LSI ready interrupt flag"]
#[inline(always)]
pub const fn lsirdyf(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt flag"]
#[inline(always)]
pub fn set_lsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt flag"]
#[inline(always)]
pub const fn lserdyf(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt flag"]
#[inline(always)]
pub fn set_lserdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "MSI ready interrupt flag"]
#[inline(always)]
pub const fn msirdyf(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "MSI ready interrupt flag"]
#[inline(always)]
pub fn set_msirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "HSI ready interrupt flag"]
#[inline(always)]
pub const fn hsirdyf(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt flag"]
#[inline(always)]
pub fn set_hsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt flag"]
#[inline(always)]
pub const fn hserdyf(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt flag"]
#[inline(always)]
pub fn set_hserdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "PLL ready interrupt flag"]
#[inline(always)]
pub const fn pllrdyf(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "PLL ready interrupt flag"]
#[inline(always)]
pub fn set_pllrdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "HSE Clock security system interrupt flag"]
#[inline(always)]
pub const fn cssf(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "HSE Clock security system interrupt flag"]
#[inline(always)]
pub fn set_cssf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "LSE Clock security system interrupt flag"]
#[inline(always)]
pub const fn lsecssf(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LSE Clock security system interrupt flag"]
#[inline(always)]
pub fn set_lsecssf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
}
impl Default for Cifr {
#[inline(always)]
fn default() -> Cifr {
Cifr(0)
}
}
impl core::fmt::Debug for Cifr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cifr")
.field("lsirdyf", &self.lsirdyf())
.field("lserdyf", &self.lserdyf())
.field("msirdyf", &self.msirdyf())
.field("hsirdyf", &self.hsirdyf())
.field("hserdyf", &self.hserdyf())
.field("pllrdyf", &self.pllrdyf())
.field("cssf", &self.cssf())
.field("lsecssf", &self.lsecssf())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cifr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cifr {{ lsirdyf: {=bool:?}, lserdyf: {=bool:?}, msirdyf: {=bool:?}, hsirdyf: {=bool:?}, hserdyf: {=bool:?}, pllrdyf: {=bool:?}, cssf: {=bool:?}, lsecssf: {=bool:?} }}" , self . lsirdyf () , self . lserdyf () , self . msirdyf () , self . hsirdyf () , self . hserdyf () , self . pllrdyf () , self . cssf () , self . lsecssf ())
}
}
#[doc = "Clock control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr(pub u32);
impl Cr {
#[doc = "MSI clock enable"]
#[inline(always)]
pub const fn msion(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "MSI clock enable"]
#[inline(always)]
pub fn set_msion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready)"]
#[inline(always)]
pub const fn msirdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready)"]
#[inline(always)]
pub fn set_msirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "MSI clock PLL enable"]
#[inline(always)]
pub const fn msipllen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "MSI clock PLL enable"]
#[inline(always)]
pub fn set_msipllen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "MSI range control selection"]
#[inline(always)]
pub const fn msirgsel(&self) -> super::vals::Msirgsel {
let val = (self.0 >> 3usize) & 0x01;
super::vals::Msirgsel::from_bits(val as u8)
}
#[doc = "MSI range control selection"]
#[inline(always)]
pub fn set_msirgsel(&mut self, val: super::vals::Msirgsel) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize);
}
#[doc = "MSI clock ranges"]
#[inline(always)]
pub const fn msirange(&self) -> super::vals::Msirange {
let val = (self.0 >> 4usize) & 0x0f;
super::vals::Msirange::from_bits(val as u8)
}
#[doc = "MSI clock ranges"]
#[inline(always)]
pub fn set_msirange(&mut self, val: super::vals::Msirange) {
self.0 = (self.0 & !(0x0f << 4usize)) | (((val.to_bits() as u32) & 0x0f) << 4usize);
}
#[doc = "HSI clock enable"]
#[inline(always)]
pub const fn hsion(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "HSI clock enable"]
#[inline(always)]
pub fn set_hsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "HSI always enable for peripheral kernel clocks."]
#[inline(always)]
pub const fn hsikeron(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "HSI always enable for peripheral kernel clocks."]
#[inline(always)]
pub fn set_hsikeron(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "HSI clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI is ready)"]
#[inline(always)]
pub const fn hsirdy(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "HSI clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI is ready)"]
#[inline(always)]
pub fn set_hsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "HSI automatic start from Stop"]
#[inline(always)]
pub const fn hsiasfs(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "HSI automatic start from Stop"]
#[inline(always)]
pub fn set_hsiasfs(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "HSI kernel clock ready flag for peripherals requests."]
#[inline(always)]
pub const fn hsikerdy(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "HSI kernel clock ready flag for peripherals requests."]
#[inline(always)]
pub fn set_hsikerdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "HSE clock enable"]
#[inline(always)]
pub const fn hseon(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "HSE clock enable"]
#[inline(always)]
pub fn set_hseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "HSE clock ready flag"]
#[inline(always)]
pub const fn hserdy(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "HSE clock ready flag"]
#[inline(always)]
pub fn set_hserdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "HSE Clock security system enable"]
#[inline(always)]
pub const fn csson(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "HSE Clock security system enable"]
#[inline(always)]
pub fn set_csson(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "HSE sysclk prescaler"]
#[inline(always)]
pub const fn hsepre(&self) -> super::vals::Hsepre {
let val = (self.0 >> 20usize) & 0x01;
super::vals::Hsepre::from_bits(val as u8)
}
#[doc = "HSE sysclk prescaler"]
#[inline(always)]
pub fn set_hsepre(&mut self, val: super::vals::Hsepre) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val.to_bits() as u32) & 0x01) << 20usize);
}
#[doc = "Enable HSE VDDTCXO output on package pin PB0-VDDTCXO."]
#[inline(always)]
pub const fn hsebyppwr(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "Enable HSE VDDTCXO output on package pin PB0-VDDTCXO."]
#[inline(always)]
pub fn set_hsebyppwr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "Main PLL enable"]
#[inline(always)]
pub const fn pllon(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Main PLL enable"]
#[inline(always)]
pub fn set_pllon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Main PLL clock ready flag"]
#[inline(always)]
pub const fn pllrdy(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Main PLL clock ready flag"]
#[inline(always)]
pub fn set_pllrdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for Cr {
#[inline(always)]
fn default() -> Cr {
Cr(0)
}
}
impl core::fmt::Debug for Cr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cr")
.field("msion", &self.msion())
.field("msirdy", &self.msirdy())
.field("msipllen", &self.msipllen())
.field("msirgsel", &self.msirgsel())
.field("msirange", &self.msirange())
.field("hsion", &self.hsion())
.field("hsikeron", &self.hsikeron())
.field("hsirdy", &self.hsirdy())
.field("hsiasfs", &self.hsiasfs())
.field("hsikerdy", &self.hsikerdy())
.field("hseon", &self.hseon())
.field("hserdy", &self.hserdy())
.field("csson", &self.csson())
.field("hsepre", &self.hsepre())
.field("hsebyppwr", &self.hsebyppwr())
.field("pllon", &self.pllon())
.field("pllrdy", &self.pllrdy())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cr {{ msion: {=bool:?}, msirdy: {=bool:?}, msipllen: {=bool:?}, msirgsel: {:?}, msirange: {:?}, hsion: {=bool:?}, hsikeron: {=bool:?}, hsirdy: {=bool:?}, hsiasfs: {=bool:?}, hsikerdy: {=bool:?}, hseon: {=bool:?}, hserdy: {=bool:?}, csson: {=bool:?}, hsepre: {:?}, hsebyppwr: {=bool:?}, pllon: {=bool:?}, pllrdy: {=bool:?} }}" , self . msion () , self . msirdy () , self . msipllen () , self . msirgsel () , self . msirange () , self . hsion () , self . hsikeron () , self . hsirdy () , self . hsiasfs () , self . hsikerdy () , self . hseon () , self . hserdy () , self . csson () , self . hsepre () , self . hsebyppwr () , self . pllon () , self . pllrdy ())
}
}
#[doc = "Control/status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csr(pub u32);
impl Csr {
#[doc = "LSI oscillator enable"]
#[inline(always)]
pub const fn lsion(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI oscillator enable"]
#[inline(always)]
pub fn set_lsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSI oscillator ready"]
#[inline(always)]
pub const fn lsirdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSI oscillator ready"]
#[inline(always)]
pub fn set_lsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "LSI frequency prescaler"]
#[inline(always)]
pub const fn lsipre(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "LSI frequency prescaler"]
#[inline(always)]
pub fn set_lsipre(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "MSI clock ranges"]
#[inline(always)]
pub const fn msisrange(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x0f;
val as u8
}
#[doc = "MSI clock ranges"]
#[inline(always)]
pub fn set_msisrange(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
}
#[doc = "Radio in reset status flag"]
#[inline(always)]
pub const fn rfrstf(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "Radio in reset status flag"]
#[inline(always)]
pub fn set_rfrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "Radio reset"]
#[inline(always)]
pub const fn rfrst(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "Radio reset"]
#[inline(always)]
pub fn set_rfrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "Remove reset flag"]
#[inline(always)]
pub const fn rmvf(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Remove reset flag"]
#[inline(always)]
pub fn set_rmvf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "Radio illegal access flag"]
#[inline(always)]
pub const fn rfilarstf(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Radio illegal access flag"]
#[inline(always)]
pub fn set_rfilarstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Option byte loader reset flag"]
#[inline(always)]
pub const fn oblrstf(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Option byte loader reset flag"]
#[inline(always)]
pub fn set_oblrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "Pin reset flag"]
#[inline(always)]
pub const fn pinrstf(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "Pin reset flag"]
#[inline(always)]
pub fn set_pinrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "BOR flag"]
#[inline(always)]
pub const fn borrstf(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "BOR flag"]
#[inline(always)]
pub fn set_borrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Software reset flag"]
#[inline(always)]
pub const fn sftrstf(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Software reset flag"]
#[inline(always)]
pub fn set_sftrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "Independent window watchdog reset flag"]
#[inline(always)]
pub const fn iwdgrstf(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "Independent window watchdog reset flag"]
#[inline(always)]
pub fn set_iwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Window watchdog reset flag"]
#[inline(always)]
pub const fn wwdgrstf(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Window watchdog reset flag"]
#[inline(always)]
pub fn set_wwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "Low-power reset flag"]
#[inline(always)]
pub const fn lpwrrstf(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Low-power reset flag"]
#[inline(always)]
pub fn set_lpwrrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Csr {
#[inline(always)]
fn default() -> Csr {
Csr(0)
}
}
impl core::fmt::Debug for Csr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Csr")
.field("lsion", &self.lsion())
.field("lsirdy", &self.lsirdy())
.field("lsipre", &self.lsipre())
.field("msisrange", &self.msisrange())
.field("rfrstf", &self.rfrstf())
.field("rfrst", &self.rfrst())
.field("rmvf", &self.rmvf())
.field("rfilarstf", &self.rfilarstf())
.field("oblrstf", &self.oblrstf())
.field("pinrstf", &self.pinrstf())
.field("borrstf", &self.borrstf())
.field("sftrstf", &self.sftrstf())
.field("iwdgrstf", &self.iwdgrstf())
.field("wwdgrstf", &self.wwdgrstf())
.field("lpwrrstf", &self.lpwrrstf())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Csr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Csr {{ lsion: {=bool:?}, lsirdy: {=bool:?}, lsipre: {=bool:?}, msisrange: {=u8:?}, rfrstf: {=bool:?}, rfrst: {=bool:?}, rmvf: {=bool:?}, rfilarstf: {=bool:?}, oblrstf: {=bool:?}, pinrstf: {=bool:?}, borrstf: {=bool:?}, sftrstf: {=bool:?}, iwdgrstf: {=bool:?}, wwdgrstf: {=bool:?}, lpwrrstf: {=bool:?} }}" , self . lsion () , self . lsirdy () , self . lsipre () , self . msisrange () , self . rfrstf () , self . rfrst () , self . rmvf () , self . rfilarstf () , self . oblrstf () , self . pinrstf () , self . borrstf () , self . sftrstf () , self . iwdgrstf () , self . wwdgrstf () , self . lpwrrstf ())
}
}
#[doc = "Extended clock recovery register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Extcfgr(pub u32);
impl Extcfgr {
#[doc = "HCLK3 shared prescaler (AHB3, Flash, and SRAM2)"]
#[inline(always)]
pub const fn shdhpre(&self) -> super::vals::Hpre {
let val = (self.0 >> 0usize) & 0x0f;
super::vals::Hpre::from_bits(val as u8)
}
#[doc = "HCLK3 shared prescaler (AHB3, Flash, and SRAM2)"]
#[inline(always)]
pub fn set_shdhpre(&mut self, val: super::vals::Hpre) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize);
}
#[doc = "dual core device only\\]
HCLK2 prescaler (CPU2)"]
#[inline(always)]
pub const fn c2hpre(&self) -> super::vals::Hpre {
let val = (self.0 >> 4usize) & 0x0f;
super::vals::Hpre::from_bits(val as u8)
}
#[doc = "dual core device only\\]
HCLK2 prescaler (CPU2)"]
#[inline(always)]
pub fn set_c2hpre(&mut self, val: super::vals::Hpre) {
self.0 = (self.0 & !(0x0f << 4usize)) | (((val.to_bits() as u32) & 0x0f) << 4usize);
}
#[doc = "HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)"]
#[inline(always)]
pub const fn shdhpref(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)"]
#[inline(always)]
pub fn set_shdhpref(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "CLK2 prescaler flag (CPU2)"]
#[inline(always)]
pub const fn c2hpref(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "CLK2 prescaler flag (CPU2)"]
#[inline(always)]
pub fn set_c2hpref(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
}
impl Default for Extcfgr {
#[inline(always)]
fn default() -> Extcfgr {
Extcfgr(0)
}
}
impl core::fmt::Debug for Extcfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Extcfgr")
.field("shdhpre", &self.shdhpre())
.field("c2hpre", &self.c2hpre())
.field("shdhpref", &self.shdhpref())
.field("c2hpref", &self.c2hpref())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Extcfgr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Extcfgr {{ shdhpre: {:?}, c2hpre: {:?}, shdhpref: {=bool:?}, c2hpref: {=bool:?} }}",
self.shdhpre(),
self.c2hpre(),
self.shdhpref(),
self.c2hpref()
)
}
}
#[doc = "Internal clock sources calibration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Icscr(pub u32);
impl Icscr {
#[doc = "MSI clock calibration"]
#[inline(always)]
pub const fn msical(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[doc = "MSI clock calibration"]
#[inline(always)]
pub fn set_msical(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
#[doc = "MSI clock trimming"]
#[inline(always)]
pub const fn msitrim(&self) -> u8 {
let val = (self.0 >> 8usize) & 0xff;
val as u8
}
#[doc = "MSI clock trimming"]
#[inline(always)]
pub fn set_msitrim(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
}
#[doc = "HSI clock calibration"]
#[inline(always)]
pub const fn hsical(&self) -> u8 {
let val = (self.0 >> 16usize) & 0xff;
val as u8
}
#[doc = "HSI clock calibration"]
#[inline(always)]
pub fn set_hsical(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
}
#[doc = "HSI clock trimming"]
#[inline(always)]
pub const fn hsitrim(&self) -> u8 {
let val = (self.0 >> 24usize) & 0x7f;
val as u8
}
#[doc = "HSI clock trimming"]
#[inline(always)]
pub fn set_hsitrim(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 24usize)) | (((val as u32) & 0x7f) << 24usize);
}
}
impl Default for Icscr {
#[inline(always)]
fn default() -> Icscr {
Icscr(0)
}
}
impl core::fmt::Debug for Icscr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Icscr")
.field("msical", &self.msical())
.field("msitrim", &self.msitrim())
.field("hsical", &self.hsical())
.field("hsitrim", &self.hsitrim())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Icscr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Icscr {{ msical: {=u8:?}, msitrim: {=u8:?}, hsical: {=u8:?}, hsitrim: {=u8:?} }}",
self.msical(),
self.msitrim(),
self.hsical(),
self.hsitrim()
)
}
}
#[doc = "PLL configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pllcfgr(pub u32);
impl Pllcfgr {
#[doc = "Main PLL entry clock source"]
#[inline(always)]
pub const fn pllsrc(&self) -> super::vals::Pllsrc {
let val = (self.0 >> 0usize) & 0x03;
super::vals::Pllsrc::from_bits(val as u8)
}
#[doc = "Main PLL entry clock source"]
#[inline(always)]
pub fn set_pllsrc(&mut self, val: super::vals::Pllsrc) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "Division factor for the main PLL input clock"]
#[inline(always)]
pub const fn pllm(&self) -> super::vals::Pllm {
let val = (self.0 >> 4usize) & 0x07;
super::vals::Pllm::from_bits(val as u8)
}
#[doc = "Division factor for the main PLL input clock"]
#[inline(always)]
pub fn set_pllm(&mut self, val: super::vals::Pllm) {
self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
}
#[doc = "Main PLL multiplication factor for VCO"]
#[inline(always)]
pub const fn plln(&self) -> super::vals::Plln {
let val = (self.0 >> 8usize) & 0x7f;
super::vals::Plln::from_bits(val as u8)
}
#[doc = "Main PLL multiplication factor for VCO"]
#[inline(always)]
pub fn set_plln(&mut self, val: super::vals::Plln) {
self.0 = (self.0 & !(0x7f << 8usize)) | (((val.to_bits() as u32) & 0x7f) << 8usize);
}
#[doc = "Main PLL PLLPCLK output enable"]
#[inline(always)]
pub const fn pllpen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Main PLL PLLPCLK output enable"]
#[inline(always)]
pub fn set_pllpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Main PLL division factor for PLLPCLK."]
#[inline(always)]
pub const fn pllp(&self) -> super::vals::Pllp {
let val = (self.0 >> 17usize) & 0x1f;
super::vals::Pllp::from_bits(val as u8)
}
#[doc = "Main PLL division factor for PLLPCLK."]
#[inline(always)]
pub fn set_pllp(&mut self, val: super::vals::Pllp) {
self.0 = (self.0 & !(0x1f << 17usize)) | (((val.to_bits() as u32) & 0x1f) << 17usize);
}
#[doc = "Main PLL PLLQCLK output enable"]
#[inline(always)]
pub const fn pllqen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Main PLL PLLQCLK output enable"]
#[inline(always)]
pub fn set_pllqen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Main PLL division factor for PLLQCLK"]
#[inline(always)]
pub const fn pllq(&self) -> super::vals::Pllq {
let val = (self.0 >> 25usize) & 0x07;
super::vals::Pllq::from_bits(val as u8)
}
#[doc = "Main PLL division factor for PLLQCLK"]
#[inline(always)]
pub fn set_pllq(&mut self, val: super::vals::Pllq) {
self.0 = (self.0 & !(0x07 << 25usize)) | (((val.to_bits() as u32) & 0x07) << 25usize);
}
#[doc = "Main PLL PLLRCLK output enable"]
#[inline(always)]
pub const fn pllren(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Main PLL PLLRCLK output enable"]
#[inline(always)]
pub fn set_pllren(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "Main PLL division factor for PLLRCLK"]
#[inline(always)]
pub const fn pllr(&self) -> super::vals::Pllr {
let val = (self.0 >> 29usize) & 0x07;
super::vals::Pllr::from_bits(val as u8)
}
#[doc = "Main PLL division factor for PLLRCLK"]
#[inline(always)]
pub fn set_pllr(&mut self, val: super::vals::Pllr) {
self.0 = (self.0 & !(0x07 << 29usize)) | (((val.to_bits() as u32) & 0x07) << 29usize);
}
}
impl Default for Pllcfgr {
#[inline(always)]
fn default() -> Pllcfgr {
Pllcfgr(0)
}
}
impl core::fmt::Debug for Pllcfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pllcfgr")
.field("pllsrc", &self.pllsrc())
.field("pllm", &self.pllm())
.field("plln", &self.plln())
.field("pllpen", &self.pllpen())
.field("pllp", &self.pllp())
.field("pllqen", &self.pllqen())
.field("pllq", &self.pllq())
.field("pllren", &self.pllren())
.field("pllr", &self.pllr())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pllcfgr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Pllcfgr {{ pllsrc: {:?}, pllm: {:?}, plln: {:?}, pllpen: {=bool:?}, pllp: {:?}, pllqen: {=bool:?}, pllq: {:?}, pllren: {=bool:?}, pllr: {:?} }}" , self . pllsrc () , self . pllm () , self . plln () , self . pllpen () , self . pllp () , self . pllqen () , self . pllq () , self . pllren () , self . pllr ())
}
}
}
pub mod vals {
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Adcsel {
_RESERVED_0 = 0x0,
#[doc = "HSI used as ADC clock source"]
HSI = 0x01,
#[doc = "PLLPCLK used as ADC clock source"]
PLL1_P = 0x02,
#[doc = "SYSCLK used as ADC clock source"]
SYS = 0x03,
}
impl Adcsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Adcsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Adcsel {
#[inline(always)]
fn from(val: u8) -> Adcsel {
Adcsel::from_bits(val)
}
}
impl From<Adcsel> for u8 {
#[inline(always)]
fn from(val: Adcsel) -> u8 {
Adcsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Hpre {
#[doc = "DCLK not divided"]
DIV1 = 0x0,
#[doc = "hclk = SYSCLK divided by 3"]
DIV3 = 0x01,
#[doc = "hclk = SYSCLK divided by 5"]
DIV5 = 0x02,
_RESERVED_3 = 0x03,
_RESERVED_4 = 0x04,
#[doc = "hclk = SYSCLK divided by 6"]
DIV6 = 0x05,
#[doc = "hclk = SYSCLK divided by 8"]
DIV10 = 0x06,
#[doc = "hclk = SYSCLK divided by 32"]
DIV32 = 0x07,
#[doc = "hclk = SYSCLK divided by 2"]
DIV2 = 0x08,
#[doc = "hclk = SYSCLK divided by 4"]
DIV4 = 0x09,
#[doc = "hclk = SYSCLK divided by 8"]
DIV8 = 0x0a,
#[doc = "hclk = SYSCLK divided by 16"]
DIV16 = 0x0b,
#[doc = "hclk = SYSCLK divided by 64"]
DIV64 = 0x0c,
#[doc = "hclk = SYSCLK divided by 128"]
DIV128 = 0x0d,
#[doc = "hclk = SYSCLK divided by 256"]
DIV256 = 0x0e,
#[doc = "hclk = SYSCLK divided by 256"]
DIV512 = 0x0f,
}
impl Hpre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Hpre {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Hpre {
#[inline(always)]
fn from(val: u8) -> Hpre {
Hpre::from_bits(val)
}
}
impl From<Hpre> for u8 {
#[inline(always)]
fn from(val: Hpre) -> u8 {
Hpre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Hsepre {
DIV1 = 0x0,
DIV2 = 0x01,
}
impl Hsepre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Hsepre {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Hsepre {
#[inline(always)]
fn from(val: u8) -> Hsepre {
Hsepre::from_bits(val)
}
}
impl From<Hsepre> for u8 {
#[inline(always)]
fn from(val: Hsepre) -> u8 {
Hsepre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lsedrv {
#[doc = "Low driving capability"]
LOW = 0x0,
#[doc = "Medium low driving capability"]
MEDIUM_LOW = 0x01,
#[doc = "Medium high driving capability"]
MEDIUM_HIGH = 0x02,
#[doc = "High driving capability"]
HIGH = 0x03,
}
impl Lsedrv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lsedrv {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lsedrv {
#[inline(always)]
fn from(val: u8) -> Lsedrv {
Lsedrv::from_bits(val)
}
}
impl From<Lsedrv> for u8 {
#[inline(always)]
fn from(val: Lsedrv) -> u8 {
Lsedrv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Mcopre {
#[doc = "No division"]
DIV1 = 0x0,
#[doc = "Division by 2"]
DIV2 = 0x01,
#[doc = "Division by 4"]
DIV4 = 0x02,
#[doc = "Division by 8"]
DIV8 = 0x03,
#[doc = "Division by 16"]
DIV16 = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Mcopre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Mcopre {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Mcopre {
#[inline(always)]
fn from(val: u8) -> Mcopre {
Mcopre::from_bits(val)
}
}
impl From<Mcopre> for u8 {
#[inline(always)]
fn from(val: Mcopre) -> u8 {
Mcopre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Mcosel {
#[doc = "No clock"]
DISABLE = 0x0,
#[doc = "SYSCLK clock selected"]
SYS = 0x01,
#[doc = "MSI oscillator clock selected"]
MSI = 0x02,
#[doc = "HSI oscillator clock selected"]
HSI = 0x03,
#[doc = "HSE oscillator clock selected"]
HSE = 0x04,
#[doc = "Main PLLRCLK clock selected"]
PLL1_R = 0x05,
#[doc = "LSI oscillator clock selected"]
LSI = 0x06,
_RESERVED_7 = 0x07,
#[doc = "LSE oscillator clock selected"]
LSE = 0x08,
_RESERVED_9 = 0x09,
_RESERVED_a = 0x0a,
_RESERVED_b = 0x0b,
_RESERVED_c = 0x0c,
#[doc = "Main PLLCLK oscillator clock selected"]
PLL1_P = 0x0d,
#[doc = "Main PLLQCLK oscillator clock selected"]
PLL1_Q = 0x0e,
_RESERVED_f = 0x0f,
}
impl Mcosel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Mcosel {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Mcosel {
#[inline(always)]
fn from(val: u8) -> Mcosel {
Mcosel::from_bits(val)
}
}
impl From<Mcosel> for u8 {
#[inline(always)]
fn from(val: Mcosel) -> u8 {
Mcosel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Msirange {
#[doc = "range 0 around 100 kHz"]
RANGE100K = 0x0,
#[doc = "range 1 around 200 kHz"]
RANGE200K = 0x01,
#[doc = "range 2 around 400 kHz"]
RANGE400K = 0x02,
#[doc = "range 3 around 800 kHz"]
RANGE800K = 0x03,
#[doc = "range 4 around 1 MHz"]
RANGE1M = 0x04,
#[doc = "range 5 around 2 MHz"]
RANGE2M = 0x05,
#[doc = "range 6 around 4 MHz"]
RANGE4M = 0x06,
#[doc = "range 7 around 8 MHz"]
RANGE8M = 0x07,
#[doc = "range 8 around 16 MHz"]
RANGE16M = 0x08,
#[doc = "range 9 around 24 MHz"]
RANGE24M = 0x09,
#[doc = "range 10 around 32 MHz"]
RANGE32M = 0x0a,
#[doc = "range 11 around 48 MHz"]
RANGE48M = 0x0b,
_RESERVED_c = 0x0c,
_RESERVED_d = 0x0d,
_RESERVED_e = 0x0e,
_RESERVED_f = 0x0f,
}
impl Msirange {
#[inline(always)]
pub const fn from_bits(val: u8) -> Msirange {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Msirange {
#[inline(always)]
fn from(val: u8) -> Msirange {
Msirange::from_bits(val)
}
}
impl From<Msirange> for u8 {
#[inline(always)]
fn from(val: Msirange) -> u8 {
Msirange::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Msirgsel {
#[doc = "MSI Range is provided by MSISRANGE\\[3:0\\]
in RCC_CSR register"]
CSR = 0x0,
#[doc = "MSI Range is provided by MSIRANGE\\[3:0\\]
in the RCC_CR register"]
CR = 0x01,
}
impl Msirgsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Msirgsel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Msirgsel {
#[inline(always)]
fn from(val: u8) -> Msirgsel {
Msirgsel::from_bits(val)
}
}
impl From<Msirgsel> for u8 {
#[inline(always)]
fn from(val: Msirgsel) -> u8 {
Msirgsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllm {
DIV1 = 0x0,
DIV2 = 0x01,
DIV3 = 0x02,
DIV4 = 0x03,
DIV5 = 0x04,
DIV6 = 0x05,
DIV7 = 0x06,
DIV8 = 0x07,
}
impl Pllm {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllm {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllm {
#[inline(always)]
fn from(val: u8) -> Pllm {
Pllm::from_bits(val)
}
}
impl From<Pllm> for u8 {
#[inline(always)]
fn from(val: Pllm) -> u8 {
Pllm::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Plln {
_RESERVED_0 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
_RESERVED_3 = 0x03,
_RESERVED_4 = 0x04,
_RESERVED_5 = 0x05,
MUL6 = 0x06,
MUL7 = 0x07,
MUL8 = 0x08,
MUL9 = 0x09,
MUL10 = 0x0a,
MUL11 = 0x0b,
MUL12 = 0x0c,
MUL13 = 0x0d,
MUL14 = 0x0e,
MUL15 = 0x0f,
MUL16 = 0x10,
MUL17 = 0x11,
MUL18 = 0x12,
MUL19 = 0x13,
MUL20 = 0x14,
MUL21 = 0x15,
MUL22 = 0x16,
MUL23 = 0x17,
MUL24 = 0x18,
MUL25 = 0x19,
MUL26 = 0x1a,
MUL27 = 0x1b,
MUL28 = 0x1c,
MUL29 = 0x1d,
MUL30 = 0x1e,
MUL31 = 0x1f,
MUL32 = 0x20,
MUL33 = 0x21,
MUL34 = 0x22,
MUL35 = 0x23,
MUL36 = 0x24,
MUL37 = 0x25,
MUL38 = 0x26,
MUL39 = 0x27,
MUL40 = 0x28,
MUL41 = 0x29,
MUL42 = 0x2a,
MUL43 = 0x2b,
MUL44 = 0x2c,
MUL45 = 0x2d,
MUL46 = 0x2e,
MUL47 = 0x2f,
MUL48 = 0x30,
MUL49 = 0x31,
MUL50 = 0x32,
MUL51 = 0x33,
MUL52 = 0x34,
MUL53 = 0x35,
MUL54 = 0x36,
MUL55 = 0x37,
MUL56 = 0x38,
MUL57 = 0x39,
MUL58 = 0x3a,
MUL59 = 0x3b,
MUL60 = 0x3c,
MUL61 = 0x3d,
MUL62 = 0x3e,
MUL63 = 0x3f,
MUL64 = 0x40,
MUL65 = 0x41,
MUL66 = 0x42,
MUL67 = 0x43,
MUL68 = 0x44,
MUL69 = 0x45,
MUL70 = 0x46,
MUL71 = 0x47,
MUL72 = 0x48,
MUL73 = 0x49,
MUL74 = 0x4a,
MUL75 = 0x4b,
MUL76 = 0x4c,
MUL77 = 0x4d,
MUL78 = 0x4e,
MUL79 = 0x4f,
MUL80 = 0x50,
MUL81 = 0x51,
MUL82 = 0x52,
MUL83 = 0x53,
MUL84 = 0x54,
MUL85 = 0x55,
MUL86 = 0x56,
MUL87 = 0x57,
MUL88 = 0x58,
MUL89 = 0x59,
MUL90 = 0x5a,
MUL91 = 0x5b,
MUL92 = 0x5c,
MUL93 = 0x5d,
MUL94 = 0x5e,
MUL95 = 0x5f,
MUL96 = 0x60,
MUL97 = 0x61,
MUL98 = 0x62,
MUL99 = 0x63,
MUL100 = 0x64,
MUL101 = 0x65,
MUL102 = 0x66,
MUL103 = 0x67,
MUL104 = 0x68,
MUL105 = 0x69,
MUL106 = 0x6a,
MUL107 = 0x6b,
MUL108 = 0x6c,
MUL109 = 0x6d,
MUL110 = 0x6e,
MUL111 = 0x6f,
MUL112 = 0x70,
MUL113 = 0x71,
MUL114 = 0x72,
MUL115 = 0x73,
MUL116 = 0x74,
MUL117 = 0x75,
MUL118 = 0x76,
MUL119 = 0x77,
MUL120 = 0x78,
MUL121 = 0x79,
MUL122 = 0x7a,
MUL123 = 0x7b,
MUL124 = 0x7c,
MUL125 = 0x7d,
MUL126 = 0x7e,
MUL127 = 0x7f,
}
impl Plln {
#[inline(always)]
pub const fn from_bits(val: u8) -> Plln {
unsafe { core::mem::transmute(val & 0x7f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Plln {
#[inline(always)]
fn from(val: u8) -> Plln {
Plln::from_bits(val)
}
}
impl From<Plln> for u8 {
#[inline(always)]
fn from(val: Plln) -> u8 {
Plln::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllp {
_RESERVED_0 = 0x0,
DIV2 = 0x01,
DIV3 = 0x02,
DIV4 = 0x03,
DIV5 = 0x04,
DIV6 = 0x05,
DIV7 = 0x06,
DIV8 = 0x07,
DIV9 = 0x08,
DIV10 = 0x09,
DIV11 = 0x0a,
DIV12 = 0x0b,
DIV13 = 0x0c,
DIV14 = 0x0d,
DIV15 = 0x0e,
DIV16 = 0x0f,
DIV17 = 0x10,
DIV18 = 0x11,
DIV19 = 0x12,
DIV20 = 0x13,
DIV21 = 0x14,
DIV22 = 0x15,
DIV23 = 0x16,
DIV24 = 0x17,
DIV25 = 0x18,
DIV26 = 0x19,
DIV27 = 0x1a,
DIV28 = 0x1b,
DIV29 = 0x1c,
DIV30 = 0x1d,
DIV31 = 0x1e,
_RESERVED_1f = 0x1f,
}
impl Pllp {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllp {
unsafe { core::mem::transmute(val & 0x1f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllp {
#[inline(always)]
fn from(val: u8) -> Pllp {
Pllp::from_bits(val)
}
}
impl From<Pllp> for u8 {
#[inline(always)]
fn from(val: Pllp) -> u8 {
Pllp::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllq {
_RESERVED_0 = 0x0,
DIV2 = 0x01,
DIV3 = 0x02,
DIV4 = 0x03,
DIV5 = 0x04,
DIV6 = 0x05,
DIV7 = 0x06,
_RESERVED_7 = 0x07,
}
impl Pllq {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllq {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllq {
#[inline(always)]
fn from(val: u8) -> Pllq {
Pllq::from_bits(val)
}
}
impl From<Pllq> for u8 {
#[inline(always)]
fn from(val: Pllq) -> u8 {
Pllq::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllr {
_RESERVED_0 = 0x0,
DIV2 = 0x01,
DIV3 = 0x02,
DIV4 = 0x03,
DIV5 = 0x04,
DIV6 = 0x05,
DIV7 = 0x06,
_RESERVED_7 = 0x07,
}
impl Pllr {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllr {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllr {
#[inline(always)]
fn from(val: u8) -> Pllr {
Pllr::from_bits(val)
}
}
impl From<Pllr> for u8 {
#[inline(always)]
fn from(val: Pllr) -> u8 {
Pllr::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllsrc {
#[doc = "No clock selected as PLL entry clock source"]
DISABLE = 0x0,
#[doc = "MSI selected as PLL entry clock source"]
MSI = 0x01,
#[doc = "HSI selected as PLL entry clock source"]
HSI = 0x02,
#[doc = "HSE selected as PLL entry clock source"]
HSE = 0x03,
}
impl Pllsrc {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllsrc {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllsrc {
#[inline(always)]
fn from(val: u8) -> Pllsrc {
Pllsrc::from_bits(val)
}
}
impl From<Pllsrc> for u8 {
#[inline(always)]
fn from(val: Pllsrc) -> u8 {
Pllsrc::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Ppre {
#[doc = "HCLK not divided"]
DIV1 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
_RESERVED_3 = 0x03,
#[doc = "HCLK divided by 2"]
DIV2 = 0x04,
#[doc = "HCLK divided by 4"]
DIV4 = 0x05,
#[doc = "HCLK divided by 8"]
DIV8 = 0x06,
#[doc = "HCLK divided by 16"]
DIV16 = 0x07,
}
impl Ppre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Ppre {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Ppre {
#[inline(always)]
fn from(val: u8) -> Ppre {
Ppre::from_bits(val)
}
}
impl From<Ppre> for u8 {
#[inline(always)]
fn from(val: Ppre) -> u8 {
Ppre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Rngsel {
PLL1_Q = 0x0,
LSI = 0x01,
LSE = 0x02,
MSI = 0x03,
}
impl Rngsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Rngsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Rngsel {
#[inline(always)]
fn from(val: u8) -> Rngsel {
Rngsel::from_bits(val)
}
}
impl From<Rngsel> for u8 {
#[inline(always)]
fn from(val: Rngsel) -> u8 {
Rngsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Rtcsel {
#[doc = "No clock selected"]
DISABLE = 0x0,
#[doc = "LSE oscillator clock selected"]
LSE = 0x01,
#[doc = "LSI oscillator clock selected"]
LSI = 0x02,
#[doc = "HSE oscillator clock divided by 32 selected"]
HSE = 0x03,
}
impl Rtcsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Rtcsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Rtcsel {
#[inline(always)]
fn from(val: u8) -> Rtcsel {
Rtcsel::from_bits(val)
}
}
impl From<Rtcsel> for u8 {
#[inline(always)]
fn from(val: Rtcsel) -> u8 {
Rtcsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Sw {
MSI = 0x0,
HSI = 0x01,
HSE = 0x02,
PLL1_R = 0x03,
}
impl Sw {
#[inline(always)]
pub const fn from_bits(val: u8) -> Sw {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Sw {
#[inline(always)]
fn from(val: u8) -> Sw {
Sw::from_bits(val)
}
}
impl From<Sw> for u8 {
#[inline(always)]
fn from(val: Sw) -> u8 {
Sw::to_bits(val)
}
}
}