#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
#[doc = "Reset and clock control"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Rcc {
ptr: *mut u8,
}
unsafe impl Send for Rcc {}
unsafe impl Sync for Rcc {}
impl Rcc {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "Clock control register"]
#[inline(always)]
pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "Internal clock sources calibration register"]
#[inline(always)]
pub const fn icscr(self) -> crate::common::Reg<regs::Icscr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "Clock configuration register"]
#[inline(always)]
pub const fn cfgr(self) -> crate::common::Reg<regs::Cfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
}
#[doc = "Clock interrupt register"]
#[inline(always)]
pub const fn cir(self) -> crate::common::Reg<regs::Cir, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
#[doc = "AHB peripheral reset register"]
#[inline(always)]
pub const fn ahbrstr(self) -> crate::common::Reg<regs::Ahbrstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
}
#[doc = "APB2 peripheral reset register"]
#[inline(always)]
pub const fn apb2rstr(self) -> crate::common::Reg<regs::Apb2rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
}
#[doc = "APB1 peripheral reset register"]
#[inline(always)]
pub const fn apb1rstr(self) -> crate::common::Reg<regs::Apb1rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
}
#[doc = "AHB peripheral clock enable register"]
#[inline(always)]
pub const fn ahbenr(self) -> crate::common::Reg<regs::Ahbenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
}
#[doc = "APB2 peripheral clock enable register"]
#[inline(always)]
pub const fn apb2enr(self) -> crate::common::Reg<regs::Apb2enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
}
#[doc = "APB1 peripheral clock enable register"]
#[inline(always)]
pub const fn apb1enr(self) -> crate::common::Reg<regs::Apb1enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
}
#[doc = "AHB peripheral clock enable in low power mode register"]
#[inline(always)]
pub const fn ahblpenr(self) -> crate::common::Reg<regs::Ahblpenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
}
#[doc = "APB2 peripheral clock enable in low power mode register"]
#[inline(always)]
pub const fn apb2lpenr(self) -> crate::common::Reg<regs::Apb2lpenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
}
#[doc = "APB1 peripheral clock enable in low power mode register"]
#[inline(always)]
pub const fn apb1lpenr(self) -> crate::common::Reg<regs::Apb1lpenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
}
#[doc = "Control/status register"]
#[inline(always)]
pub const fn csr(self) -> crate::common::Reg<regs::Csr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
}
}
pub mod regs {
#[doc = "AHB peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahbenr(pub u32);
impl Ahbenr {
#[doc = "IO port A clock enable"]
#[inline(always)]
pub const fn gpioaen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "IO port A clock enable"]
#[inline(always)]
pub fn set_gpioaen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "IO port B clock enable"]
#[inline(always)]
pub const fn gpioben(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "IO port B clock enable"]
#[inline(always)]
pub fn set_gpioben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "IO port C clock enable"]
#[inline(always)]
pub const fn gpiocen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "IO port C clock enable"]
#[inline(always)]
pub fn set_gpiocen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "IO port D clock enable"]
#[inline(always)]
pub const fn gpioden(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "IO port D clock enable"]
#[inline(always)]
pub fn set_gpioden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "IO port E clock enable"]
#[inline(always)]
pub const fn gpioeen(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "IO port E clock enable"]
#[inline(always)]
pub fn set_gpioeen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "IO port H clock enable"]
#[inline(always)]
pub const fn gpiohen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "IO port H clock enable"]
#[inline(always)]
pub fn set_gpiohen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "IO port F clock enable"]
#[inline(always)]
pub const fn gpiofen(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "IO port F clock enable"]
#[inline(always)]
pub fn set_gpiofen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "IO port G clock enable"]
#[inline(always)]
pub const fn gpiogen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "IO port G clock enable"]
#[inline(always)]
pub fn set_gpiogen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "CRC clock enable"]
#[inline(always)]
pub const fn crcen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC clock enable"]
#[inline(always)]
pub fn set_crcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "FLASH clock enable"]
#[inline(always)]
pub const fn flashen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "FLASH clock enable"]
#[inline(always)]
pub fn set_flashen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "DMA1 clock enable"]
#[inline(always)]
pub const fn dma1en(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "DMA1 clock enable"]
#[inline(always)]
pub fn set_dma1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "DMA2 clock enable"]
#[inline(always)]
pub const fn dma2en(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "DMA2 clock enable"]
#[inline(always)]
pub fn set_dma2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "FSMCEN"]
#[inline(always)]
pub const fn fsmcen(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "FSMCEN"]
#[inline(always)]
pub fn set_fsmcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
}
impl Default for Ahbenr {
#[inline(always)]
fn default() -> Ahbenr {
Ahbenr(0)
}
}
impl core::fmt::Debug for Ahbenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahbenr")
.field("gpioaen", &self.gpioaen())
.field("gpioben", &self.gpioben())
.field("gpiocen", &self.gpiocen())
.field("gpioden", &self.gpioden())
.field("gpioeen", &self.gpioeen())
.field("gpiohen", &self.gpiohen())
.field("gpiofen", &self.gpiofen())
.field("gpiogen", &self.gpiogen())
.field("crcen", &self.crcen())
.field("flashen", &self.flashen())
.field("dma1en", &self.dma1en())
.field("dma2en", &self.dma2en())
.field("fsmcen", &self.fsmcen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahbenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahbenr {{ gpioaen: {=bool:?}, gpioben: {=bool:?}, gpiocen: {=bool:?}, gpioden: {=bool:?}, gpioeen: {=bool:?}, gpiohen: {=bool:?}, gpiofen: {=bool:?}, gpiogen: {=bool:?}, crcen: {=bool:?}, flashen: {=bool:?}, dma1en: {=bool:?}, dma2en: {=bool:?}, fsmcen: {=bool:?} }}" , self . gpioaen () , self . gpioben () , self . gpiocen () , self . gpioden () , self . gpioeen () , self . gpiohen () , self . gpiofen () , self . gpiogen () , self . crcen () , self . flashen () , self . dma1en () , self . dma2en () , self . fsmcen ())
}
}
#[doc = "AHB peripheral clock enable in low power mode register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahblpenr(pub u32);
impl Ahblpenr {
#[doc = "IO port A clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpioalpen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "IO port A clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpioalpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "IO port B clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpioblpen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "IO port B clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpioblpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "IO port C clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpioclpen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "IO port C clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpioclpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "IO port D clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpiodlpen(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "IO port D clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpiodlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "IO port E clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpioelpen(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "IO port E clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpioelpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "IO port H clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpiohlpen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "IO port H clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpiohlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "IO port F clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpioflpen(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "IO port F clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpioflpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "IO port G clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpioglpen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "IO port G clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpioglpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "CRC clock enable during Sleep mode"]
#[inline(always)]
pub const fn crclpen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC clock enable during Sleep mode"]
#[inline(always)]
pub fn set_crclpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "FLASH clock enable during Sleep mode"]
#[inline(always)]
pub const fn flashlpen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "FLASH clock enable during Sleep mode"]
#[inline(always)]
pub fn set_flashlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "SRAM clock enable during Sleep mode"]
#[inline(always)]
pub const fn sramlpen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "SRAM clock enable during Sleep mode"]
#[inline(always)]
pub fn set_sramlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "DMA1 clock enable during Sleep mode"]
#[inline(always)]
pub const fn dma1lpen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "DMA1 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_dma1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "DMA2 clock enable during Sleep mode"]
#[inline(always)]
pub const fn dma2lpen(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "DMA2 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_dma2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for Ahblpenr {
#[inline(always)]
fn default() -> Ahblpenr {
Ahblpenr(0)
}
}
impl core::fmt::Debug for Ahblpenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahblpenr")
.field("gpioalpen", &self.gpioalpen())
.field("gpioblpen", &self.gpioblpen())
.field("gpioclpen", &self.gpioclpen())
.field("gpiodlpen", &self.gpiodlpen())
.field("gpioelpen", &self.gpioelpen())
.field("gpiohlpen", &self.gpiohlpen())
.field("gpioflpen", &self.gpioflpen())
.field("gpioglpen", &self.gpioglpen())
.field("crclpen", &self.crclpen())
.field("flashlpen", &self.flashlpen())
.field("sramlpen", &self.sramlpen())
.field("dma1lpen", &self.dma1lpen())
.field("dma2lpen", &self.dma2lpen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahblpenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahblpenr {{ gpioalpen: {=bool:?}, gpioblpen: {=bool:?}, gpioclpen: {=bool:?}, gpiodlpen: {=bool:?}, gpioelpen: {=bool:?}, gpiohlpen: {=bool:?}, gpioflpen: {=bool:?}, gpioglpen: {=bool:?}, crclpen: {=bool:?}, flashlpen: {=bool:?}, sramlpen: {=bool:?}, dma1lpen: {=bool:?}, dma2lpen: {=bool:?} }}" , self . gpioalpen () , self . gpioblpen () , self . gpioclpen () , self . gpiodlpen () , self . gpioelpen () , self . gpiohlpen () , self . gpioflpen () , self . gpioglpen () , self . crclpen () , self . flashlpen () , self . sramlpen () , self . dma1lpen () , self . dma2lpen ())
}
}
#[doc = "AHB peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahbrstr(pub u32);
impl Ahbrstr {
#[doc = "IO port A reset"]
#[inline(always)]
pub const fn gpioarst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "IO port A reset"]
#[inline(always)]
pub fn set_gpioarst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "IO port B reset"]
#[inline(always)]
pub const fn gpiobrst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "IO port B reset"]
#[inline(always)]
pub fn set_gpiobrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "IO port C reset"]
#[inline(always)]
pub const fn gpiocrst(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "IO port C reset"]
#[inline(always)]
pub fn set_gpiocrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "IO port D reset"]
#[inline(always)]
pub const fn gpiodrst(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "IO port D reset"]
#[inline(always)]
pub fn set_gpiodrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "IO port E reset"]
#[inline(always)]
pub const fn gpioerst(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "IO port E reset"]
#[inline(always)]
pub fn set_gpioerst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "IO port H reset"]
#[inline(always)]
pub const fn gpiohrst(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "IO port H reset"]
#[inline(always)]
pub fn set_gpiohrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "IO port F reset"]
#[inline(always)]
pub const fn gpiofrst(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "IO port F reset"]
#[inline(always)]
pub fn set_gpiofrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "IO port G reset"]
#[inline(always)]
pub const fn gpiogrst(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "IO port G reset"]
#[inline(always)]
pub fn set_gpiogrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "CRC reset"]
#[inline(always)]
pub const fn crcrst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC reset"]
#[inline(always)]
pub fn set_crcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "FLASH reset"]
#[inline(always)]
pub const fn flashrst(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "FLASH reset"]
#[inline(always)]
pub fn set_flashrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "DMA1 reset"]
#[inline(always)]
pub const fn dma1rst(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "DMA1 reset"]
#[inline(always)]
pub fn set_dma1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "DMA2 reset"]
#[inline(always)]
pub const fn dma2rst(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "DMA2 reset"]
#[inline(always)]
pub fn set_dma2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "FSMC reset"]
#[inline(always)]
pub const fn fsmcrst(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "FSMC reset"]
#[inline(always)]
pub fn set_fsmcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
}
impl Default for Ahbrstr {
#[inline(always)]
fn default() -> Ahbrstr {
Ahbrstr(0)
}
}
impl core::fmt::Debug for Ahbrstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahbrstr")
.field("gpioarst", &self.gpioarst())
.field("gpiobrst", &self.gpiobrst())
.field("gpiocrst", &self.gpiocrst())
.field("gpiodrst", &self.gpiodrst())
.field("gpioerst", &self.gpioerst())
.field("gpiohrst", &self.gpiohrst())
.field("gpiofrst", &self.gpiofrst())
.field("gpiogrst", &self.gpiogrst())
.field("crcrst", &self.crcrst())
.field("flashrst", &self.flashrst())
.field("dma1rst", &self.dma1rst())
.field("dma2rst", &self.dma2rst())
.field("fsmcrst", &self.fsmcrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahbrstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahbrstr {{ gpioarst: {=bool:?}, gpiobrst: {=bool:?}, gpiocrst: {=bool:?}, gpiodrst: {=bool:?}, gpioerst: {=bool:?}, gpiohrst: {=bool:?}, gpiofrst: {=bool:?}, gpiogrst: {=bool:?}, crcrst: {=bool:?}, flashrst: {=bool:?}, dma1rst: {=bool:?}, dma2rst: {=bool:?}, fsmcrst: {=bool:?} }}" , self . gpioarst () , self . gpiobrst () , self . gpiocrst () , self . gpiodrst () , self . gpioerst () , self . gpiohrst () , self . gpiofrst () , self . gpiogrst () , self . crcrst () , self . flashrst () , self . dma1rst () , self . dma2rst () , self . fsmcrst ())
}
}
#[doc = "APB1 peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1enr(pub u32);
impl Apb1enr {
#[doc = "Timer 2 clock enable"]
#[inline(always)]
pub const fn tim2en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Timer 2 clock enable"]
#[inline(always)]
pub fn set_tim2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Timer 3 clock enable"]
#[inline(always)]
pub const fn tim3en(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Timer 3 clock enable"]
#[inline(always)]
pub fn set_tim3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Timer 4 clock enable"]
#[inline(always)]
pub const fn tim4en(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Timer 4 clock enable"]
#[inline(always)]
pub fn set_tim4en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Timer 5 clock enable"]
#[inline(always)]
pub const fn tim5en(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Timer 5 clock enable"]
#[inline(always)]
pub fn set_tim5en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "Timer 6 clock enable"]
#[inline(always)]
pub const fn tim6en(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "Timer 6 clock enable"]
#[inline(always)]
pub fn set_tim6en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "Timer 7 clock enable"]
#[inline(always)]
pub const fn tim7en(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Timer 7 clock enable"]
#[inline(always)]
pub fn set_tim7en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "LCD clock enable"]
#[inline(always)]
pub const fn lcden(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LCD clock enable"]
#[inline(always)]
pub fn set_lcden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "Window watchdog clock enable"]
#[inline(always)]
pub const fn wwdgen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Window watchdog clock enable"]
#[inline(always)]
pub fn set_wwdgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI 2 clock enable"]
#[inline(always)]
pub const fn spi2en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI 2 clock enable"]
#[inline(always)]
pub fn set_spi2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "SPI 3 clock enable"]
#[inline(always)]
pub const fn spi3en(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "SPI 3 clock enable"]
#[inline(always)]
pub fn set_spi3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "USART 2 clock enable"]
#[inline(always)]
pub const fn usart2en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART 2 clock enable"]
#[inline(always)]
pub fn set_usart2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART 3 clock enable"]
#[inline(always)]
pub const fn usart3en(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART 3 clock enable"]
#[inline(always)]
pub fn set_usart3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "UART 4 clock enable"]
#[inline(always)]
pub const fn usart4en(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "UART 4 clock enable"]
#[inline(always)]
pub fn set_usart4en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "UART 5 clock enable"]
#[inline(always)]
pub const fn usart5en(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "UART 5 clock enable"]
#[inline(always)]
pub fn set_usart5en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "I2C 1 clock enable"]
#[inline(always)]
pub const fn i2c1en(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C 1 clock enable"]
#[inline(always)]
pub fn set_i2c1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C 2 clock enable"]
#[inline(always)]
pub const fn i2c2en(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C 2 clock enable"]
#[inline(always)]
pub fn set_i2c2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "USB clock enable"]
#[inline(always)]
pub const fn usben(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "USB clock enable"]
#[inline(always)]
pub fn set_usben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "Power interface clock enable"]
#[inline(always)]
pub const fn pwren(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Power interface clock enable"]
#[inline(always)]
pub fn set_pwren(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "DAC interface clock enable"]
#[inline(always)]
pub const fn dacen(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "DAC interface clock enable"]
#[inline(always)]
pub fn set_dacen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "COMP interface clock enable"]
#[inline(always)]
pub const fn compen(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "COMP interface clock enable"]
#[inline(always)]
pub fn set_compen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apb1enr {
#[inline(always)]
fn default() -> Apb1enr {
Apb1enr(0)
}
}
impl core::fmt::Debug for Apb1enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1enr")
.field("tim2en", &self.tim2en())
.field("tim3en", &self.tim3en())
.field("tim4en", &self.tim4en())
.field("tim5en", &self.tim5en())
.field("tim6en", &self.tim6en())
.field("tim7en", &self.tim7en())
.field("lcden", &self.lcden())
.field("wwdgen", &self.wwdgen())
.field("spi2en", &self.spi2en())
.field("spi3en", &self.spi3en())
.field("usart2en", &self.usart2en())
.field("usart3en", &self.usart3en())
.field("usart4en", &self.usart4en())
.field("usart5en", &self.usart5en())
.field("i2c1en", &self.i2c1en())
.field("i2c2en", &self.i2c2en())
.field("usben", &self.usben())
.field("pwren", &self.pwren())
.field("dacen", &self.dacen())
.field("compen", &self.compen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1enr {{ tim2en: {=bool:?}, tim3en: {=bool:?}, tim4en: {=bool:?}, tim5en: {=bool:?}, tim6en: {=bool:?}, tim7en: {=bool:?}, lcden: {=bool:?}, wwdgen: {=bool:?}, spi2en: {=bool:?}, spi3en: {=bool:?}, usart2en: {=bool:?}, usart3en: {=bool:?}, usart4en: {=bool:?}, usart5en: {=bool:?}, i2c1en: {=bool:?}, i2c2en: {=bool:?}, usben: {=bool:?}, pwren: {=bool:?}, dacen: {=bool:?}, compen: {=bool:?} }}" , self . tim2en () , self . tim3en () , self . tim4en () , self . tim5en () , self . tim6en () , self . tim7en () , self . lcden () , self . wwdgen () , self . spi2en () , self . spi3en () , self . usart2en () , self . usart3en () , self . usart4en () , self . usart5en () , self . i2c1en () , self . i2c2en () , self . usben () , self . pwren () , self . dacen () , self . compen ())
}
}
#[doc = "APB1 peripheral clock enable in low power mode register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1lpenr(pub u32);
impl Apb1lpenr {
#[doc = "Timer 2 clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim2lpen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Timer 2 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Timer 3 clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim3lpen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Timer 3 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim3lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Timer 4 clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim4lpen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Timer 4 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim4lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Timer 6 clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim6lpen(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "Timer 6 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim6lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "Timer 7 clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim7lpen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Timer 7 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim7lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "LCD clock enable during Sleep mode"]
#[inline(always)]
pub const fn lcdlpen(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LCD clock enable during Sleep mode"]
#[inline(always)]
pub fn set_lcdlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "Window watchdog clock enable during Sleep mode"]
#[inline(always)]
pub const fn wwdglpen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Window watchdog clock enable during Sleep mode"]
#[inline(always)]
pub fn set_wwdglpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI 2 clock enable during Sleep mode"]
#[inline(always)]
pub const fn spi2lpen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI 2 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_spi2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "USART 2 clock enable during Sleep mode"]
#[inline(always)]
pub const fn usart2lpen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART 2 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_usart2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART 3 clock enable during Sleep mode"]
#[inline(always)]
pub const fn usart3lpen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART 3 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_usart3lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "I2C 1 clock enable during Sleep mode"]
#[inline(always)]
pub const fn i2c1lpen(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C 1 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_i2c1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C 2 clock enable during Sleep mode"]
#[inline(always)]
pub const fn i2c2lpen(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C 2 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_i2c2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "USB clock enable during Sleep mode"]
#[inline(always)]
pub const fn usblpen(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "USB clock enable during Sleep mode"]
#[inline(always)]
pub fn set_usblpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "Power interface clock enable during Sleep mode"]
#[inline(always)]
pub const fn pwrlpen(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Power interface clock enable during Sleep mode"]
#[inline(always)]
pub fn set_pwrlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "DAC interface clock enable during Sleep mode"]
#[inline(always)]
pub const fn daclpen(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "DAC interface clock enable during Sleep mode"]
#[inline(always)]
pub fn set_daclpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "COMP interface clock enable during Sleep mode"]
#[inline(always)]
pub const fn complpen(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "COMP interface clock enable during Sleep mode"]
#[inline(always)]
pub fn set_complpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apb1lpenr {
#[inline(always)]
fn default() -> Apb1lpenr {
Apb1lpenr(0)
}
}
impl core::fmt::Debug for Apb1lpenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1lpenr")
.field("tim2lpen", &self.tim2lpen())
.field("tim3lpen", &self.tim3lpen())
.field("tim4lpen", &self.tim4lpen())
.field("tim6lpen", &self.tim6lpen())
.field("tim7lpen", &self.tim7lpen())
.field("lcdlpen", &self.lcdlpen())
.field("wwdglpen", &self.wwdglpen())
.field("spi2lpen", &self.spi2lpen())
.field("usart2lpen", &self.usart2lpen())
.field("usart3lpen", &self.usart3lpen())
.field("i2c1lpen", &self.i2c1lpen())
.field("i2c2lpen", &self.i2c2lpen())
.field("usblpen", &self.usblpen())
.field("pwrlpen", &self.pwrlpen())
.field("daclpen", &self.daclpen())
.field("complpen", &self.complpen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1lpenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1lpenr {{ tim2lpen: {=bool:?}, tim3lpen: {=bool:?}, tim4lpen: {=bool:?}, tim6lpen: {=bool:?}, tim7lpen: {=bool:?}, lcdlpen: {=bool:?}, wwdglpen: {=bool:?}, spi2lpen: {=bool:?}, usart2lpen: {=bool:?}, usart3lpen: {=bool:?}, i2c1lpen: {=bool:?}, i2c2lpen: {=bool:?}, usblpen: {=bool:?}, pwrlpen: {=bool:?}, daclpen: {=bool:?}, complpen: {=bool:?} }}" , self . tim2lpen () , self . tim3lpen () , self . tim4lpen () , self . tim6lpen () , self . tim7lpen () , self . lcdlpen () , self . wwdglpen () , self . spi2lpen () , self . usart2lpen () , self . usart3lpen () , self . i2c1lpen () , self . i2c2lpen () , self . usblpen () , self . pwrlpen () , self . daclpen () , self . complpen ())
}
}
#[doc = "APB1 peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1rstr(pub u32);
impl Apb1rstr {
#[doc = "Timer 2 reset"]
#[inline(always)]
pub const fn tim2rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Timer 2 reset"]
#[inline(always)]
pub fn set_tim2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Timer 3 reset"]
#[inline(always)]
pub const fn tim3rst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Timer 3 reset"]
#[inline(always)]
pub fn set_tim3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Timer 4 reset"]
#[inline(always)]
pub const fn tim4rst(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Timer 4 reset"]
#[inline(always)]
pub fn set_tim4rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Timer 5 reset"]
#[inline(always)]
pub const fn tim5rst(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Timer 5 reset"]
#[inline(always)]
pub fn set_tim5rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "Timer 6reset"]
#[inline(always)]
pub const fn tim6rst(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "Timer 6reset"]
#[inline(always)]
pub fn set_tim6rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "Timer 7 reset"]
#[inline(always)]
pub const fn tim7rst(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Timer 7 reset"]
#[inline(always)]
pub fn set_tim7rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "LCD reset"]
#[inline(always)]
pub const fn lcdrst(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LCD reset"]
#[inline(always)]
pub fn set_lcdrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "Window watchdog reset"]
#[inline(always)]
pub const fn wwdrst(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Window watchdog reset"]
#[inline(always)]
pub fn set_wwdrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI 2 reset"]
#[inline(always)]
pub const fn spi2rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI 2 reset"]
#[inline(always)]
pub fn set_spi2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "SPI 3 reset"]
#[inline(always)]
pub const fn spi3rst(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "SPI 3 reset"]
#[inline(always)]
pub fn set_spi3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "USART 2 reset"]
#[inline(always)]
pub const fn usart2rst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART 2 reset"]
#[inline(always)]
pub fn set_usart2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART 3 reset"]
#[inline(always)]
pub const fn usart3rst(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART 3 reset"]
#[inline(always)]
pub fn set_usart3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "UART 4 reset"]
#[inline(always)]
pub const fn uart4rst(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "UART 4 reset"]
#[inline(always)]
pub fn set_uart4rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "UART 5 reset"]
#[inline(always)]
pub const fn uart5rst(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "UART 5 reset"]
#[inline(always)]
pub fn set_uart5rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "I2C 1 reset"]
#[inline(always)]
pub const fn i2c1rst(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C 1 reset"]
#[inline(always)]
pub fn set_i2c1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C 2 reset"]
#[inline(always)]
pub const fn i2c2rst(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C 2 reset"]
#[inline(always)]
pub fn set_i2c2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "USB reset"]
#[inline(always)]
pub const fn usbrst(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "USB reset"]
#[inline(always)]
pub fn set_usbrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "Power interface reset"]
#[inline(always)]
pub const fn pwrrst(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Power interface reset"]
#[inline(always)]
pub fn set_pwrrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "DAC interface reset"]
#[inline(always)]
pub const fn dacrst(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "DAC interface reset"]
#[inline(always)]
pub fn set_dacrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "COMP interface reset"]
#[inline(always)]
pub const fn comprst(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "COMP interface reset"]
#[inline(always)]
pub fn set_comprst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apb1rstr {
#[inline(always)]
fn default() -> Apb1rstr {
Apb1rstr(0)
}
}
impl core::fmt::Debug for Apb1rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1rstr")
.field("tim2rst", &self.tim2rst())
.field("tim3rst", &self.tim3rst())
.field("tim4rst", &self.tim4rst())
.field("tim5rst", &self.tim5rst())
.field("tim6rst", &self.tim6rst())
.field("tim7rst", &self.tim7rst())
.field("lcdrst", &self.lcdrst())
.field("wwdrst", &self.wwdrst())
.field("spi2rst", &self.spi2rst())
.field("spi3rst", &self.spi3rst())
.field("usart2rst", &self.usart2rst())
.field("usart3rst", &self.usart3rst())
.field("uart4rst", &self.uart4rst())
.field("uart5rst", &self.uart5rst())
.field("i2c1rst", &self.i2c1rst())
.field("i2c2rst", &self.i2c2rst())
.field("usbrst", &self.usbrst())
.field("pwrrst", &self.pwrrst())
.field("dacrst", &self.dacrst())
.field("comprst", &self.comprst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1rstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1rstr {{ tim2rst: {=bool:?}, tim3rst: {=bool:?}, tim4rst: {=bool:?}, tim5rst: {=bool:?}, tim6rst: {=bool:?}, tim7rst: {=bool:?}, lcdrst: {=bool:?}, wwdrst: {=bool:?}, spi2rst: {=bool:?}, spi3rst: {=bool:?}, usart2rst: {=bool:?}, usart3rst: {=bool:?}, uart4rst: {=bool:?}, uart5rst: {=bool:?}, i2c1rst: {=bool:?}, i2c2rst: {=bool:?}, usbrst: {=bool:?}, pwrrst: {=bool:?}, dacrst: {=bool:?}, comprst: {=bool:?} }}" , self . tim2rst () , self . tim3rst () , self . tim4rst () , self . tim5rst () , self . tim6rst () , self . tim7rst () , self . lcdrst () , self . wwdrst () , self . spi2rst () , self . spi3rst () , self . usart2rst () , self . usart3rst () , self . uart4rst () , self . uart5rst () , self . i2c1rst () , self . i2c2rst () , self . usbrst () , self . pwrrst () , self . dacrst () , self . comprst ())
}
}
#[doc = "APB2 peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb2enr(pub u32);
impl Apb2enr {
#[doc = "System configuration controller clock enable"]
#[inline(always)]
pub const fn syscfgen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "System configuration controller clock enable"]
#[inline(always)]
pub fn set_syscfgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM9 timer clock enable"]
#[inline(always)]
pub const fn tim9en(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "TIM9 timer clock enable"]
#[inline(always)]
pub fn set_tim9en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "TIM10 timer clock enable"]
#[inline(always)]
pub const fn tim10en(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "TIM10 timer clock enable"]
#[inline(always)]
pub fn set_tim10en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "TIM11 timer clock enable"]
#[inline(always)]
pub const fn tim11en(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "TIM11 timer clock enable"]
#[inline(always)]
pub fn set_tim11en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "ADC1 interface clock enable"]
#[inline(always)]
pub const fn adc1en(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "ADC1 interface clock enable"]
#[inline(always)]
pub fn set_adc1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "SDIO clock enable"]
#[inline(always)]
pub const fn sdioen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "SDIO clock enable"]
#[inline(always)]
pub fn set_sdioen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI 1 clock enable"]
#[inline(always)]
pub const fn spi1en(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI 1 clock enable"]
#[inline(always)]
pub fn set_spi1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1 clock enable"]
#[inline(always)]
pub const fn usart1en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 clock enable"]
#[inline(always)]
pub fn set_usart1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
}
impl Default for Apb2enr {
#[inline(always)]
fn default() -> Apb2enr {
Apb2enr(0)
}
}
impl core::fmt::Debug for Apb2enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb2enr")
.field("syscfgen", &self.syscfgen())
.field("tim9en", &self.tim9en())
.field("tim10en", &self.tim10en())
.field("tim11en", &self.tim11en())
.field("adc1en", &self.adc1en())
.field("sdioen", &self.sdioen())
.field("spi1en", &self.spi1en())
.field("usart1en", &self.usart1en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb2enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb2enr {{ syscfgen: {=bool:?}, tim9en: {=bool:?}, tim10en: {=bool:?}, tim11en: {=bool:?}, adc1en: {=bool:?}, sdioen: {=bool:?}, spi1en: {=bool:?}, usart1en: {=bool:?} }}" , self . syscfgen () , self . tim9en () , self . tim10en () , self . tim11en () , self . adc1en () , self . sdioen () , self . spi1en () , self . usart1en ())
}
}
#[doc = "APB2 peripheral clock enable in low power mode register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb2lpenr(pub u32);
impl Apb2lpenr {
#[doc = "System configuration controller clock enable during Sleep mode"]
#[inline(always)]
pub const fn syscfglpen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "System configuration controller clock enable during Sleep mode"]
#[inline(always)]
pub fn set_syscfglpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM9 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim9lpen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "TIM9 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim9lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "TIM10 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim10lpen(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "TIM10 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim10lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "TIM11 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim11lpen(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "TIM11 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim11lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "ADC1 interface clock enable during Sleep mode"]
#[inline(always)]
pub const fn adc1lpen(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "ADC1 interface clock enable during Sleep mode"]
#[inline(always)]
pub fn set_adc1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "SDIO clock enable during Sleep mode"]
#[inline(always)]
pub const fn sdiolpen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "SDIO clock enable during Sleep mode"]
#[inline(always)]
pub fn set_sdiolpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI 1 clock enable during Sleep mode"]
#[inline(always)]
pub const fn spi1lpen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI 1 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_spi1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1 clock enable during Sleep mode"]
#[inline(always)]
pub const fn usart1lpen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_usart1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
}
impl Default for Apb2lpenr {
#[inline(always)]
fn default() -> Apb2lpenr {
Apb2lpenr(0)
}
}
impl core::fmt::Debug for Apb2lpenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb2lpenr")
.field("syscfglpen", &self.syscfglpen())
.field("tim9lpen", &self.tim9lpen())
.field("tim10lpen", &self.tim10lpen())
.field("tim11lpen", &self.tim11lpen())
.field("adc1lpen", &self.adc1lpen())
.field("sdiolpen", &self.sdiolpen())
.field("spi1lpen", &self.spi1lpen())
.field("usart1lpen", &self.usart1lpen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb2lpenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb2lpenr {{ syscfglpen: {=bool:?}, tim9lpen: {=bool:?}, tim10lpen: {=bool:?}, tim11lpen: {=bool:?}, adc1lpen: {=bool:?}, sdiolpen: {=bool:?}, spi1lpen: {=bool:?}, usart1lpen: {=bool:?} }}" , self . syscfglpen () , self . tim9lpen () , self . tim10lpen () , self . tim11lpen () , self . adc1lpen () , self . sdiolpen () , self . spi1lpen () , self . usart1lpen ())
}
}
#[doc = "APB2 peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb2rstr(pub u32);
impl Apb2rstr {
#[doc = "SYSCFGRST"]
#[inline(always)]
pub const fn syscfgrst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "SYSCFGRST"]
#[inline(always)]
pub fn set_syscfgrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM9RST"]
#[inline(always)]
pub const fn tim9rst(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "TIM9RST"]
#[inline(always)]
pub fn set_tim9rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "TM10RST"]
#[inline(always)]
pub const fn tm10rst(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "TM10RST"]
#[inline(always)]
pub fn set_tm10rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "TM11RST"]
#[inline(always)]
pub const fn tm11rst(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "TM11RST"]
#[inline(always)]
pub fn set_tm11rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "ADC1RST"]
#[inline(always)]
pub const fn adc1rst(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "ADC1RST"]
#[inline(always)]
pub fn set_adc1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "SDIORST"]
#[inline(always)]
pub const fn sdiorst(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "SDIORST"]
#[inline(always)]
pub fn set_sdiorst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1RST"]
#[inline(always)]
pub const fn spi1rst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1RST"]
#[inline(always)]
pub fn set_spi1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1RST"]
#[inline(always)]
pub const fn usart1rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1RST"]
#[inline(always)]
pub fn set_usart1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
}
impl Default for Apb2rstr {
#[inline(always)]
fn default() -> Apb2rstr {
Apb2rstr(0)
}
}
impl core::fmt::Debug for Apb2rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb2rstr")
.field("syscfgrst", &self.syscfgrst())
.field("tim9rst", &self.tim9rst())
.field("tm10rst", &self.tm10rst())
.field("tm11rst", &self.tm11rst())
.field("adc1rst", &self.adc1rst())
.field("sdiorst", &self.sdiorst())
.field("spi1rst", &self.spi1rst())
.field("usart1rst", &self.usart1rst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb2rstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb2rstr {{ syscfgrst: {=bool:?}, tim9rst: {=bool:?}, tm10rst: {=bool:?}, tm11rst: {=bool:?}, adc1rst: {=bool:?}, sdiorst: {=bool:?}, spi1rst: {=bool:?}, usart1rst: {=bool:?} }}" , self . syscfgrst () , self . tim9rst () , self . tm10rst () , self . tm11rst () , self . adc1rst () , self . sdiorst () , self . spi1rst () , self . usart1rst ())
}
}
#[doc = "Clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfgr(pub u32);
impl Cfgr {
#[doc = "System clock switch"]
#[inline(always)]
pub const fn sw(&self) -> super::vals::Sw {
let val = (self.0 >> 0usize) & 0x03;
super::vals::Sw::from_bits(val as u8)
}
#[doc = "System clock switch"]
#[inline(always)]
pub fn set_sw(&mut self, val: super::vals::Sw) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "System clock switch status"]
#[inline(always)]
pub const fn sws(&self) -> super::vals::Sw {
let val = (self.0 >> 2usize) & 0x03;
super::vals::Sw::from_bits(val as u8)
}
#[doc = "System clock switch status"]
#[inline(always)]
pub fn set_sws(&mut self, val: super::vals::Sw) {
self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
}
#[doc = "AHB prescaler"]
#[inline(always)]
pub const fn hpre(&self) -> super::vals::Hpre {
let val = (self.0 >> 4usize) & 0x0f;
super::vals::Hpre::from_bits(val as u8)
}
#[doc = "AHB prescaler"]
#[inline(always)]
pub fn set_hpre(&mut self, val: super::vals::Hpre) {
self.0 = (self.0 & !(0x0f << 4usize)) | (((val.to_bits() as u32) & 0x0f) << 4usize);
}
#[doc = "APB low-speed prescaler (APB1)"]
#[inline(always)]
pub const fn ppre1(&self) -> super::vals::Ppre {
let val = (self.0 >> 8usize) & 0x07;
super::vals::Ppre::from_bits(val as u8)
}
#[doc = "APB low-speed prescaler (APB1)"]
#[inline(always)]
pub fn set_ppre1(&mut self, val: super::vals::Ppre) {
self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
}
#[doc = "APB high-speed prescaler (APB2)"]
#[inline(always)]
pub const fn ppre2(&self) -> super::vals::Ppre {
let val = (self.0 >> 11usize) & 0x07;
super::vals::Ppre::from_bits(val as u8)
}
#[doc = "APB high-speed prescaler (APB2)"]
#[inline(always)]
pub fn set_ppre2(&mut self, val: super::vals::Ppre) {
self.0 = (self.0 & !(0x07 << 11usize)) | (((val.to_bits() as u32) & 0x07) << 11usize);
}
#[doc = "PLL entry clock source"]
#[inline(always)]
pub const fn pllsrc(&self) -> super::vals::Pllsrc {
let val = (self.0 >> 16usize) & 0x01;
super::vals::Pllsrc::from_bits(val as u8)
}
#[doc = "PLL entry clock source"]
#[inline(always)]
pub fn set_pllsrc(&mut self, val: super::vals::Pllsrc) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32) & 0x01) << 16usize);
}
#[doc = "PLL multiplication factor"]
#[inline(always)]
pub const fn pllmul(&self) -> super::vals::Pllmul {
let val = (self.0 >> 18usize) & 0x0f;
super::vals::Pllmul::from_bits(val as u8)
}
#[doc = "PLL multiplication factor"]
#[inline(always)]
pub fn set_pllmul(&mut self, val: super::vals::Pllmul) {
self.0 = (self.0 & !(0x0f << 18usize)) | (((val.to_bits() as u32) & 0x0f) << 18usize);
}
#[doc = "PLL output division"]
#[inline(always)]
pub const fn plldiv(&self) -> super::vals::Plldiv {
let val = (self.0 >> 22usize) & 0x03;
super::vals::Plldiv::from_bits(val as u8)
}
#[doc = "PLL output division"]
#[inline(always)]
pub fn set_plldiv(&mut self, val: super::vals::Plldiv) {
self.0 = (self.0 & !(0x03 << 22usize)) | (((val.to_bits() as u32) & 0x03) << 22usize);
}
#[doc = "Microcontroller clock output selection"]
#[inline(always)]
pub const fn mcosel(&self) -> super::vals::Mcosel {
let val = (self.0 >> 24usize) & 0x07;
super::vals::Mcosel::from_bits(val as u8)
}
#[doc = "Microcontroller clock output selection"]
#[inline(always)]
pub fn set_mcosel(&mut self, val: super::vals::Mcosel) {
self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize);
}
#[doc = "Microcontroller clock output prescaler"]
#[inline(always)]
pub const fn mcopre(&self) -> super::vals::Mcopre {
let val = (self.0 >> 28usize) & 0x07;
super::vals::Mcopre::from_bits(val as u8)
}
#[doc = "Microcontroller clock output prescaler"]
#[inline(always)]
pub fn set_mcopre(&mut self, val: super::vals::Mcopre) {
self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize);
}
}
impl Default for Cfgr {
#[inline(always)]
fn default() -> Cfgr {
Cfgr(0)
}
}
impl core::fmt::Debug for Cfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cfgr")
.field("sw", &self.sw())
.field("sws", &self.sws())
.field("hpre", &self.hpre())
.field("ppre1", &self.ppre1())
.field("ppre2", &self.ppre2())
.field("pllsrc", &self.pllsrc())
.field("pllmul", &self.pllmul())
.field("plldiv", &self.plldiv())
.field("mcosel", &self.mcosel())
.field("mcopre", &self.mcopre())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cfgr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cfgr {{ sw: {:?}, sws: {:?}, hpre: {:?}, ppre1: {:?}, ppre2: {:?}, pllsrc: {:?}, pllmul: {:?}, plldiv: {:?}, mcosel: {:?}, mcopre: {:?} }}" , self . sw () , self . sws () , self . hpre () , self . ppre1 () , self . ppre2 () , self . pllsrc () , self . pllmul () , self . plldiv () , self . mcosel () , self . mcopre ())
}
}
#[doc = "Clock interrupt register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cir(pub u32);
impl Cir {
#[doc = "LSI ready interrupt flag"]
#[inline(always)]
pub const fn lsirdyf(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt flag"]
#[inline(always)]
pub fn set_lsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt flag"]
#[inline(always)]
pub const fn lserdyf(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt flag"]
#[inline(always)]
pub fn set_lserdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "HSI ready interrupt flag"]
#[inline(always)]
pub const fn hsirdyf(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt flag"]
#[inline(always)]
pub fn set_hsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "HSE ready interrupt flag"]
#[inline(always)]
pub const fn hserdyf(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt flag"]
#[inline(always)]
pub fn set_hserdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "PLL ready interrupt flag"]
#[inline(always)]
pub const fn pllrdyf(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "PLL ready interrupt flag"]
#[inline(always)]
pub fn set_pllrdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "MSI ready interrupt flag"]
#[inline(always)]
pub const fn msirdyf(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "MSI ready interrupt flag"]
#[inline(always)]
pub fn set_msirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Clock security system interrupt flag"]
#[inline(always)]
pub const fn cssf(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "Clock security system interrupt flag"]
#[inline(always)]
pub fn set_cssf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "LSI ready interrupt enable"]
#[inline(always)]
pub const fn lsirdyie(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt enable"]
#[inline(always)]
pub fn set_lsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "LSE ready interrupt enable"]
#[inline(always)]
pub const fn lserdyie(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt enable"]
#[inline(always)]
pub fn set_lserdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "HSI ready interrupt enable"]
#[inline(always)]
pub const fn hsirdyie(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt enable"]
#[inline(always)]
pub fn set_hsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "HSE ready interrupt enable"]
#[inline(always)]
pub const fn hserdyie(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt enable"]
#[inline(always)]
pub fn set_hserdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "PLL ready interrupt enable"]
#[inline(always)]
pub const fn pllrdyie(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "PLL ready interrupt enable"]
#[inline(always)]
pub fn set_pllrdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "MSI ready interrupt enable"]
#[inline(always)]
pub const fn msirdyie(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "MSI ready interrupt enable"]
#[inline(always)]
pub fn set_msirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "LSI ready interrupt clear"]
#[inline(always)]
pub const fn lsirdyc(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt clear"]
#[inline(always)]
pub fn set_lsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "LSE ready interrupt clear"]
#[inline(always)]
pub const fn lserdyc(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt clear"]
#[inline(always)]
pub fn set_lserdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "HSI ready interrupt clear"]
#[inline(always)]
pub const fn hsirdyc(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt clear"]
#[inline(always)]
pub fn set_hsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "HSE ready interrupt clear"]
#[inline(always)]
pub const fn hserdyc(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt clear"]
#[inline(always)]
pub fn set_hserdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "PLL ready interrupt clear"]
#[inline(always)]
pub const fn pllrdyc(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "PLL ready interrupt clear"]
#[inline(always)]
pub fn set_pllrdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "MSI ready interrupt clear"]
#[inline(always)]
pub const fn msirdyc(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "MSI ready interrupt clear"]
#[inline(always)]
pub fn set_msirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "Clock security system interrupt clear"]
#[inline(always)]
pub const fn cssc(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Clock security system interrupt clear"]
#[inline(always)]
pub fn set_cssc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
}
impl Default for Cir {
#[inline(always)]
fn default() -> Cir {
Cir(0)
}
}
impl core::fmt::Debug for Cir {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cir")
.field("lsirdyf", &self.lsirdyf())
.field("lserdyf", &self.lserdyf())
.field("hsirdyf", &self.hsirdyf())
.field("hserdyf", &self.hserdyf())
.field("pllrdyf", &self.pllrdyf())
.field("msirdyf", &self.msirdyf())
.field("cssf", &self.cssf())
.field("lsirdyie", &self.lsirdyie())
.field("lserdyie", &self.lserdyie())
.field("hsirdyie", &self.hsirdyie())
.field("hserdyie", &self.hserdyie())
.field("pllrdyie", &self.pllrdyie())
.field("msirdyie", &self.msirdyie())
.field("lsirdyc", &self.lsirdyc())
.field("lserdyc", &self.lserdyc())
.field("hsirdyc", &self.hsirdyc())
.field("hserdyc", &self.hserdyc())
.field("pllrdyc", &self.pllrdyc())
.field("msirdyc", &self.msirdyc())
.field("cssc", &self.cssc())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cir {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cir {{ lsirdyf: {=bool:?}, lserdyf: {=bool:?}, hsirdyf: {=bool:?}, hserdyf: {=bool:?}, pllrdyf: {=bool:?}, msirdyf: {=bool:?}, cssf: {=bool:?}, lsirdyie: {=bool:?}, lserdyie: {=bool:?}, hsirdyie: {=bool:?}, hserdyie: {=bool:?}, pllrdyie: {=bool:?}, msirdyie: {=bool:?}, lsirdyc: {=bool:?}, lserdyc: {=bool:?}, hsirdyc: {=bool:?}, hserdyc: {=bool:?}, pllrdyc: {=bool:?}, msirdyc: {=bool:?}, cssc: {=bool:?} }}" , self . lsirdyf () , self . lserdyf () , self . hsirdyf () , self . hserdyf () , self . pllrdyf () , self . msirdyf () , self . cssf () , self . lsirdyie () , self . lserdyie () , self . hsirdyie () , self . hserdyie () , self . pllrdyie () , self . msirdyie () , self . lsirdyc () , self . lserdyc () , self . hsirdyc () , self . hserdyc () , self . pllrdyc () , self . msirdyc () , self . cssc ())
}
}
#[doc = "Clock control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr(pub u32);
impl Cr {
#[doc = "Internal high-speed clock enable"]
#[inline(always)]
pub const fn hsion(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Internal high-speed clock enable"]
#[inline(always)]
pub fn set_hsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Internal high-speed clock ready flag"]
#[inline(always)]
pub const fn hsirdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Internal high-speed clock ready flag"]
#[inline(always)]
pub fn set_hsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "MSI clock enable"]
#[inline(always)]
pub const fn msion(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "MSI clock enable"]
#[inline(always)]
pub fn set_msion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "MSI clock ready flag"]
#[inline(always)]
pub const fn msirdy(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "MSI clock ready flag"]
#[inline(always)]
pub fn set_msirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "HSE clock enable"]
#[inline(always)]
pub const fn hseon(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "HSE clock enable"]
#[inline(always)]
pub fn set_hseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "HSE clock ready flag"]
#[inline(always)]
pub const fn hserdy(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "HSE clock ready flag"]
#[inline(always)]
pub fn set_hserdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "HSE clock bypass"]
#[inline(always)]
pub const fn hsebyp(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "HSE clock bypass"]
#[inline(always)]
pub fn set_hsebyp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "PLL enable"]
#[inline(always)]
pub const fn pllon(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "PLL enable"]
#[inline(always)]
pub fn set_pllon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "PLL clock ready flag"]
#[inline(always)]
pub const fn pllrdy(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "PLL clock ready flag"]
#[inline(always)]
pub fn set_pllrdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "Clock security system enable"]
#[inline(always)]
pub const fn csson(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Clock security system enable"]
#[inline(always)]
pub fn set_csson(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "RTC/LCD prescaler"]
#[inline(always)]
pub const fn rtcpre(&self) -> super::vals::Rtcpre {
let val = (self.0 >> 29usize) & 0x03;
super::vals::Rtcpre::from_bits(val as u8)
}
#[doc = "RTC/LCD prescaler"]
#[inline(always)]
pub fn set_rtcpre(&mut self, val: super::vals::Rtcpre) {
self.0 = (self.0 & !(0x03 << 29usize)) | (((val.to_bits() as u32) & 0x03) << 29usize);
}
}
impl Default for Cr {
#[inline(always)]
fn default() -> Cr {
Cr(0)
}
}
impl core::fmt::Debug for Cr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cr")
.field("hsion", &self.hsion())
.field("hsirdy", &self.hsirdy())
.field("msion", &self.msion())
.field("msirdy", &self.msirdy())
.field("hseon", &self.hseon())
.field("hserdy", &self.hserdy())
.field("hsebyp", &self.hsebyp())
.field("pllon", &self.pllon())
.field("pllrdy", &self.pllrdy())
.field("csson", &self.csson())
.field("rtcpre", &self.rtcpre())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cr {{ hsion: {=bool:?}, hsirdy: {=bool:?}, msion: {=bool:?}, msirdy: {=bool:?}, hseon: {=bool:?}, hserdy: {=bool:?}, hsebyp: {=bool:?}, pllon: {=bool:?}, pllrdy: {=bool:?}, csson: {=bool:?}, rtcpre: {:?} }}" , self . hsion () , self . hsirdy () , self . msion () , self . msirdy () , self . hseon () , self . hserdy () , self . hsebyp () , self . pllon () , self . pllrdy () , self . csson () , self . rtcpre ())
}
}
#[doc = "Control and status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csr(pub u32);
impl Csr {
#[doc = "Internal low-speed oscillator enable"]
#[inline(always)]
pub const fn lsion(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Internal low-speed oscillator enable"]
#[inline(always)]
pub fn set_lsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Internal low-speed oscillator ready"]
#[inline(always)]
pub const fn lsirdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Internal low-speed oscillator ready"]
#[inline(always)]
pub fn set_lsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "External low-speed oscillator enable"]
#[inline(always)]
pub const fn lseon(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "External low-speed oscillator enable"]
#[inline(always)]
pub fn set_lseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "External low-speed oscillator ready"]
#[inline(always)]
pub const fn lserdy(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "External low-speed oscillator ready"]
#[inline(always)]
pub fn set_lserdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "External low-speed oscillator bypass"]
#[inline(always)]
pub const fn lsebyp(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "External low-speed oscillator bypass"]
#[inline(always)]
pub fn set_lsebyp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "RTC and LCD clock source selection"]
#[inline(always)]
pub const fn rtcsel(&self) -> super::vals::Rtcsel {
let val = (self.0 >> 16usize) & 0x03;
super::vals::Rtcsel::from_bits(val as u8)
}
#[doc = "RTC and LCD clock source selection"]
#[inline(always)]
pub fn set_rtcsel(&mut self, val: super::vals::Rtcsel) {
self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize);
}
#[doc = "RTC clock enable"]
#[inline(always)]
pub const fn rtcen(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "RTC clock enable"]
#[inline(always)]
pub fn set_rtcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "RTC software reset"]
#[inline(always)]
pub const fn rtcrst(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "RTC software reset"]
#[inline(always)]
pub fn set_rtcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "Remove reset flag"]
#[inline(always)]
pub const fn rmvf(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Remove reset flag"]
#[inline(always)]
pub fn set_rmvf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "PIN reset flag"]
#[inline(always)]
pub const fn pinrstf(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "PIN reset flag"]
#[inline(always)]
pub fn set_pinrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "POR/PDR reset flag"]
#[inline(always)]
pub const fn porrstf(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "POR/PDR reset flag"]
#[inline(always)]
pub fn set_porrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Software reset flag"]
#[inline(always)]
pub const fn sftrstf(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Software reset flag"]
#[inline(always)]
pub fn set_sftrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "Independent watchdog reset flag"]
#[inline(always)]
pub const fn iwdgrstf(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "Independent watchdog reset flag"]
#[inline(always)]
pub fn set_iwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Window watchdog reset flag"]
#[inline(always)]
pub const fn wwdgrstf(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Window watchdog reset flag"]
#[inline(always)]
pub fn set_wwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "Low-power reset flag"]
#[inline(always)]
pub const fn lpwrrstf(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Low-power reset flag"]
#[inline(always)]
pub fn set_lpwrrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Csr {
#[inline(always)]
fn default() -> Csr {
Csr(0)
}
}
impl core::fmt::Debug for Csr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Csr")
.field("lsion", &self.lsion())
.field("lsirdy", &self.lsirdy())
.field("lseon", &self.lseon())
.field("lserdy", &self.lserdy())
.field("lsebyp", &self.lsebyp())
.field("rtcsel", &self.rtcsel())
.field("rtcen", &self.rtcen())
.field("rtcrst", &self.rtcrst())
.field("rmvf", &self.rmvf())
.field("pinrstf", &self.pinrstf())
.field("porrstf", &self.porrstf())
.field("sftrstf", &self.sftrstf())
.field("iwdgrstf", &self.iwdgrstf())
.field("wwdgrstf", &self.wwdgrstf())
.field("lpwrrstf", &self.lpwrrstf())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Csr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Csr {{ lsion: {=bool:?}, lsirdy: {=bool:?}, lseon: {=bool:?}, lserdy: {=bool:?}, lsebyp: {=bool:?}, rtcsel: {:?}, rtcen: {=bool:?}, rtcrst: {=bool:?}, rmvf: {=bool:?}, pinrstf: {=bool:?}, porrstf: {=bool:?}, sftrstf: {=bool:?}, iwdgrstf: {=bool:?}, wwdgrstf: {=bool:?}, lpwrrstf: {=bool:?} }}" , self . lsion () , self . lsirdy () , self . lseon () , self . lserdy () , self . lsebyp () , self . rtcsel () , self . rtcen () , self . rtcrst () , self . rmvf () , self . pinrstf () , self . porrstf () , self . sftrstf () , self . iwdgrstf () , self . wwdgrstf () , self . lpwrrstf ())
}
}
#[doc = "Internal clock sources calibration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Icscr(pub u32);
impl Icscr {
#[doc = "nternal high speed clock calibration"]
#[inline(always)]
pub const fn hsical(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[doc = "nternal high speed clock calibration"]
#[inline(always)]
pub fn set_hsical(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
#[doc = "High speed internal clock trimming"]
#[inline(always)]
pub const fn hsitrim(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x1f;
val as u8
}
#[doc = "High speed internal clock trimming"]
#[inline(always)]
pub fn set_hsitrim(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
}
#[doc = "MSI clock ranges"]
#[inline(always)]
pub const fn msirange(&self) -> super::vals::Msirange {
let val = (self.0 >> 13usize) & 0x07;
super::vals::Msirange::from_bits(val as u8)
}
#[doc = "MSI clock ranges"]
#[inline(always)]
pub fn set_msirange(&mut self, val: super::vals::Msirange) {
self.0 = (self.0 & !(0x07 << 13usize)) | (((val.to_bits() as u32) & 0x07) << 13usize);
}
#[doc = "MSI clock calibration"]
#[inline(always)]
pub const fn msical(&self) -> u8 {
let val = (self.0 >> 16usize) & 0xff;
val as u8
}
#[doc = "MSI clock calibration"]
#[inline(always)]
pub fn set_msical(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
}
#[doc = "MSI clock trimming"]
#[inline(always)]
pub const fn msitrim(&self) -> u8 {
let val = (self.0 >> 24usize) & 0xff;
val as u8
}
#[doc = "MSI clock trimming"]
#[inline(always)]
pub fn set_msitrim(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize);
}
}
impl Default for Icscr {
#[inline(always)]
fn default() -> Icscr {
Icscr(0)
}
}
impl core::fmt::Debug for Icscr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Icscr")
.field("hsical", &self.hsical())
.field("hsitrim", &self.hsitrim())
.field("msirange", &self.msirange())
.field("msical", &self.msical())
.field("msitrim", &self.msitrim())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Icscr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Icscr {{ hsical: {=u8:?}, hsitrim: {=u8:?}, msirange: {:?}, msical: {=u8:?}, msitrim: {=u8:?} }}",
self.hsical(),
self.hsitrim(),
self.msirange(),
self.msical(),
self.msitrim()
)
}
}
}
pub mod vals {
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Hpre {
#[doc = "system clock not divided"]
DIV1 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
_RESERVED_3 = 0x03,
_RESERVED_4 = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
#[doc = "system clock divided by 2"]
DIV2 = 0x08,
#[doc = "system clock divided by 4"]
DIV4 = 0x09,
#[doc = "system clock divided by 8"]
DIV8 = 0x0a,
#[doc = "system clock divided by 16"]
DIV16 = 0x0b,
#[doc = "system clock divided by 64"]
DIV64 = 0x0c,
#[doc = "system clock divided by 128"]
DIV128 = 0x0d,
#[doc = "system clock divided by 256"]
DIV256 = 0x0e,
#[doc = "system clock divided by 512"]
DIV512 = 0x0f,
}
impl Hpre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Hpre {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Hpre {
#[inline(always)]
fn from(val: u8) -> Hpre {
Hpre::from_bits(val)
}
}
impl From<Hpre> for u8 {
#[inline(always)]
fn from(val: Hpre) -> u8 {
Hpre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Mcopre {
#[doc = "No division"]
DIV1 = 0x0,
#[doc = "Division by 2"]
DIV2 = 0x01,
#[doc = "Division by 4"]
DIV4 = 0x02,
#[doc = "Division by 8"]
DIV8 = 0x03,
#[doc = "Division by 16"]
DIV16 = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Mcopre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Mcopre {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Mcopre {
#[inline(always)]
fn from(val: u8) -> Mcopre {
Mcopre::from_bits(val)
}
}
impl From<Mcopre> for u8 {
#[inline(always)]
fn from(val: Mcopre) -> u8 {
Mcopre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Mcosel {
#[doc = "No clock"]
DISABLE = 0x0,
#[doc = "SYSCLK clock selected"]
SYS = 0x01,
#[doc = "HSI oscillator clock selected"]
HSI = 0x02,
#[doc = "MSI oscillator clock selected"]
MSI = 0x03,
#[doc = "HSE oscillator clock selected"]
HSE = 0x04,
#[doc = "PLL clock selected"]
PLL = 0x05,
#[doc = "LSI oscillator clock selected"]
LSI = 0x06,
#[doc = "LSE oscillator clock selected"]
LSE = 0x07,
}
impl Mcosel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Mcosel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Mcosel {
#[inline(always)]
fn from(val: u8) -> Mcosel {
Mcosel::from_bits(val)
}
}
impl From<Mcosel> for u8 {
#[inline(always)]
fn from(val: Mcosel) -> u8 {
Mcosel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Msirange {
#[doc = "range 0 around 65.536 kHz"]
RANGE66K = 0x0,
#[doc = "range 1 around 131.072 kHz"]
RANGE131K = 0x01,
#[doc = "range 2 around 262.144 kHz"]
RANGE262K = 0x02,
#[doc = "range 3 around 524.288 kHz"]
RANGE524K = 0x03,
#[doc = "range 4 around 1.048 MHz"]
RANGE1M = 0x04,
#[doc = "range 5 around 2.097 MHz (reset value)"]
RANGE2M = 0x05,
#[doc = "range 6 around 4.194 MHz"]
RANGE4M = 0x06,
_RESERVED_7 = 0x07,
}
impl Msirange {
#[inline(always)]
pub const fn from_bits(val: u8) -> Msirange {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Msirange {
#[inline(always)]
fn from(val: u8) -> Msirange {
Msirange::from_bits(val)
}
}
impl From<Msirange> for u8 {
#[inline(always)]
fn from(val: Msirange) -> u8 {
Msirange::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Plldiv {
_RESERVED_0 = 0x0,
#[doc = "PLLVCO / 2"]
DIV2 = 0x01,
#[doc = "PLLVCO / 3"]
DIV3 = 0x02,
#[doc = "PLLVCO / 4"]
DIV4 = 0x03,
}
impl Plldiv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Plldiv {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Plldiv {
#[inline(always)]
fn from(val: u8) -> Plldiv {
Plldiv::from_bits(val)
}
}
impl From<Plldiv> for u8 {
#[inline(always)]
fn from(val: Plldiv) -> u8 {
Plldiv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllmul {
#[doc = "PLL clock entry x 3"]
MUL3 = 0x0,
#[doc = "PLL clock entry x 4"]
MUL4 = 0x01,
#[doc = "PLL clock entry x 6"]
MUL6 = 0x02,
#[doc = "PLL clock entry x 8"]
MUL8 = 0x03,
#[doc = "PLL clock entry x 12"]
MUL12 = 0x04,
#[doc = "PLL clock entry x 16"]
MUL16 = 0x05,
#[doc = "PLL clock entry x 24"]
MUL24 = 0x06,
#[doc = "PLL clock entry x 32"]
MUL32 = 0x07,
#[doc = "PLL clock entry x 48"]
MUL48 = 0x08,
_RESERVED_9 = 0x09,
_RESERVED_a = 0x0a,
_RESERVED_b = 0x0b,
_RESERVED_c = 0x0c,
_RESERVED_d = 0x0d,
_RESERVED_e = 0x0e,
_RESERVED_f = 0x0f,
}
impl Pllmul {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllmul {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllmul {
#[inline(always)]
fn from(val: u8) -> Pllmul {
Pllmul::from_bits(val)
}
}
impl From<Pllmul> for u8 {
#[inline(always)]
fn from(val: Pllmul) -> u8 {
Pllmul::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllsrc {
#[doc = "HSI selected as PLL input clock"]
HSI = 0x0,
#[doc = "HSE selected as PLL input clock"]
HSE = 0x01,
}
impl Pllsrc {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllsrc {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllsrc {
#[inline(always)]
fn from(val: u8) -> Pllsrc {
Pllsrc::from_bits(val)
}
}
impl From<Pllsrc> for u8 {
#[inline(always)]
fn from(val: Pllsrc) -> u8 {
Pllsrc::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Ppre {
#[doc = "HCLK not divided"]
DIV1 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
_RESERVED_3 = 0x03,
#[doc = "HCLK divided by 2"]
DIV2 = 0x04,
#[doc = "HCLK divided by 4"]
DIV4 = 0x05,
#[doc = "HCLK divided by 8"]
DIV8 = 0x06,
#[doc = "HCLK divided by 16"]
DIV16 = 0x07,
}
impl Ppre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Ppre {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Ppre {
#[inline(always)]
fn from(val: u8) -> Ppre {
Ppre::from_bits(val)
}
}
impl From<Ppre> for u8 {
#[inline(always)]
fn from(val: Ppre) -> u8 {
Ppre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Rtcpre {
#[doc = "HSE divided by 2"]
DIV2 = 0x0,
#[doc = "HSE divided by 4"]
DIV4 = 0x01,
#[doc = "HSE divided by 8"]
DIV8 = 0x02,
#[doc = "HSE divided by 16"]
DIV16 = 0x03,
}
impl Rtcpre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Rtcpre {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Rtcpre {
#[inline(always)]
fn from(val: u8) -> Rtcpre {
Rtcpre::from_bits(val)
}
}
impl From<Rtcpre> for u8 {
#[inline(always)]
fn from(val: Rtcpre) -> u8 {
Rtcpre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Rtcsel {
#[doc = "No clock"]
DISABLE = 0x0,
#[doc = "LSE oscillator clock used as RTC clock"]
LSE = 0x01,
#[doc = "LSI oscillator clock used as RTC clock"]
LSI = 0x02,
#[doc = "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE\\[1:0\\]
bits in the RCC clock control register (RCC_CR)) used as the RTC clock"]
HSE = 0x03,
}
impl Rtcsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Rtcsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Rtcsel {
#[inline(always)]
fn from(val: u8) -> Rtcsel {
Rtcsel::from_bits(val)
}
}
impl From<Rtcsel> for u8 {
#[inline(always)]
fn from(val: Rtcsel) -> u8 {
Rtcsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Sw {
#[doc = "MSI oscillator used as system clock"]
MSI = 0x0,
#[doc = "HSI oscillator used as system clock"]
HSI = 0x01,
#[doc = "HSE oscillator used as system clock"]
HSE = 0x02,
#[doc = "PLL used as system clock"]
PLL1_R = 0x03,
}
impl Sw {
#[inline(always)]
pub const fn from_bits(val: u8) -> Sw {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Sw {
#[inline(always)]
fn from(val: u8) -> Sw {
Sw::from_bits(val)
}
}
impl From<Sw> for u8 {
#[inline(always)]
fn from(val: Sw) -> u8 {
Sw::to_bits(val)
}
}
}