#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
#[doc = "Analog-to-digital converter"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Adc {
ptr: *mut u8,
}
unsafe impl Send for Adc {}
unsafe impl Sync for Adc {}
impl Adc {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "status register"]
#[inline(always)]
pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "control register 1"]
#[inline(always)]
pub const fn cr1(self) -> crate::common::Reg<regs::Cr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "control register 2"]
#[inline(always)]
pub const fn cr2(self) -> crate::common::Reg<regs::Cr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
}
#[doc = "sample time register 1"]
#[inline(always)]
pub const fn smpr1(self) -> crate::common::Reg<regs::Smpr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
#[doc = "sample time register 2"]
#[inline(always)]
pub const fn smpr2(self) -> crate::common::Reg<regs::Smpr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
}
#[doc = "injected channel data offset register x"]
#[inline(always)]
pub const fn jofr(self, n: usize) -> crate::common::Reg<regs::Jofr, crate::common::RW> {
assert!(n < 4usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize + n * 4usize) as _) }
}
#[doc = "watchdog higher threshold register"]
#[inline(always)]
pub const fn htr(self) -> crate::common::Reg<regs::Htr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
}
#[doc = "watchdog lower threshold register"]
#[inline(always)]
pub const fn ltr(self) -> crate::common::Reg<regs::Ltr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
}
#[doc = "regular sequence register 1"]
#[inline(always)]
pub const fn sqr1(self) -> crate::common::Reg<regs::Sqr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
}
#[doc = "regular sequence register 2"]
#[inline(always)]
pub const fn sqr2(self) -> crate::common::Reg<regs::Sqr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
}
#[doc = "regular sequence register 3"]
#[inline(always)]
pub const fn sqr3(self) -> crate::common::Reg<regs::Sqr3, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
}
#[doc = "injected sequence register"]
#[inline(always)]
pub const fn jsqr(self) -> crate::common::Reg<regs::Jsqr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
}
#[doc = "injected data register x"]
#[inline(always)]
pub const fn jdr(self, n: usize) -> crate::common::Reg<regs::Jdr, crate::common::R> {
assert!(n < 4usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize + n * 4usize) as _) }
}
#[doc = "regular data register"]
#[inline(always)]
pub const fn dr(self) -> crate::common::Reg<regs::Dr, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
}
}
pub mod regs {
#[doc = "control register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr1(pub u32);
impl Cr1 {
#[doc = "Analog watchdog channel select bits"]
#[inline(always)]
pub const fn awdch(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x1f;
val as u8
}
#[doc = "Analog watchdog channel select bits"]
#[inline(always)]
pub fn set_awdch(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
}
#[doc = "Interrupt enable for EOC"]
#[inline(always)]
pub const fn eocie(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Interrupt enable for EOC"]
#[inline(always)]
pub fn set_eocie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Analog watchdog interrupt enable"]
#[inline(always)]
pub const fn awdie(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "Analog watchdog interrupt enable"]
#[inline(always)]
pub fn set_awdie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "Interrupt enable for injected channels"]
#[inline(always)]
pub const fn jeocie(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "Interrupt enable for injected channels"]
#[inline(always)]
pub fn set_jeocie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "Scan mode"]
#[inline(always)]
pub const fn scan(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Scan mode"]
#[inline(always)]
pub fn set_scan(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "Enable the watchdog on a single channel in scan mode"]
#[inline(always)]
pub const fn awdsgl(&self) -> super::vals::Awdsgl {
let val = (self.0 >> 9usize) & 0x01;
super::vals::Awdsgl::from_bits(val as u8)
}
#[doc = "Enable the watchdog on a single channel in scan mode"]
#[inline(always)]
pub fn set_awdsgl(&mut self, val: super::vals::Awdsgl) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize);
}
#[doc = "Automatic injected group conversion"]
#[inline(always)]
pub const fn jauto(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "Automatic injected group conversion"]
#[inline(always)]
pub fn set_jauto(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "Discontinuous mode on regular channels"]
#[inline(always)]
pub const fn discen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Discontinuous mode on regular channels"]
#[inline(always)]
pub fn set_discen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "Discontinuous mode on injected channels"]
#[inline(always)]
pub const fn jdiscen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "Discontinuous mode on injected channels"]
#[inline(always)]
pub fn set_jdiscen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "Discontinuous mode channel count"]
#[inline(always)]
pub const fn discnum(&self) -> u8 {
let val = (self.0 >> 13usize) & 0x07;
val as u8
}
#[doc = "Discontinuous mode channel count"]
#[inline(always)]
pub fn set_discnum(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 13usize)) | (((val as u32) & 0x07) << 13usize);
}
#[doc = "Analog watchdog enable on injected channels"]
#[inline(always)]
pub const fn jawden(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "Analog watchdog enable on injected channels"]
#[inline(always)]
pub fn set_jawden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "Analog watchdog enable on regular channels"]
#[inline(always)]
pub const fn awden(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Analog watchdog enable on regular channels"]
#[inline(always)]
pub fn set_awden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "Resolution"]
#[inline(always)]
pub const fn res(&self) -> super::vals::Res {
let val = (self.0 >> 24usize) & 0x03;
super::vals::Res::from_bits(val as u8)
}
#[doc = "Resolution"]
#[inline(always)]
pub fn set_res(&mut self, val: super::vals::Res) {
self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize);
}
#[doc = "Overrun interrupt enable"]
#[inline(always)]
pub const fn ovrie(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "Overrun interrupt enable"]
#[inline(always)]
pub fn set_ovrie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
}
impl Default for Cr1 {
#[inline(always)]
fn default() -> Cr1 {
Cr1(0)
}
}
impl core::fmt::Debug for Cr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cr1")
.field("awdch", &self.awdch())
.field("eocie", &self.eocie())
.field("awdie", &self.awdie())
.field("jeocie", &self.jeocie())
.field("scan", &self.scan())
.field("awdsgl", &self.awdsgl())
.field("jauto", &self.jauto())
.field("discen", &self.discen())
.field("jdiscen", &self.jdiscen())
.field("discnum", &self.discnum())
.field("jawden", &self.jawden())
.field("awden", &self.awden())
.field("res", &self.res())
.field("ovrie", &self.ovrie())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cr1 {{ awdch: {=u8:?}, eocie: {=bool:?}, awdie: {=bool:?}, jeocie: {=bool:?}, scan: {=bool:?}, awdsgl: {:?}, jauto: {=bool:?}, discen: {=bool:?}, jdiscen: {=bool:?}, discnum: {=u8:?}, jawden: {=bool:?}, awden: {=bool:?}, res: {:?}, ovrie: {=bool:?} }}" , self . awdch () , self . eocie () , self . awdie () , self . jeocie () , self . scan () , self . awdsgl () , self . jauto () , self . discen () , self . jdiscen () , self . discnum () , self . jawden () , self . awden () , self . res () , self . ovrie ())
}
}
#[doc = "control register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr2(pub u32);
impl Cr2 {
#[doc = "A/D Converter ON / OFF"]
#[inline(always)]
pub const fn adon(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "A/D Converter ON / OFF"]
#[inline(always)]
pub fn set_adon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Continuous conversion"]
#[inline(always)]
pub const fn cont(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Continuous conversion"]
#[inline(always)]
pub fn set_cont(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Direct memory access mode (for single ADC mode)"]
#[inline(always)]
pub const fn dma(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Direct memory access mode (for single ADC mode)"]
#[inline(always)]
pub fn set_dma(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "DMA disable selection (for single ADC mode)"]
#[inline(always)]
pub const fn dds(&self) -> super::vals::Dds {
let val = (self.0 >> 9usize) & 0x01;
super::vals::Dds::from_bits(val as u8)
}
#[doc = "DMA disable selection (for single ADC mode)"]
#[inline(always)]
pub fn set_dds(&mut self, val: super::vals::Dds) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize);
}
#[doc = "End of conversion selection"]
#[inline(always)]
pub const fn eocs(&self) -> super::vals::Eocs {
let val = (self.0 >> 10usize) & 0x01;
super::vals::Eocs::from_bits(val as u8)
}
#[doc = "End of conversion selection"]
#[inline(always)]
pub fn set_eocs(&mut self, val: super::vals::Eocs) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize);
}
#[doc = "Data alignment"]
#[inline(always)]
pub const fn align(&self) -> super::vals::Align {
let val = (self.0 >> 11usize) & 0x01;
super::vals::Align::from_bits(val as u8)
}
#[doc = "Data alignment"]
#[inline(always)]
pub fn set_align(&mut self, val: super::vals::Align) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize);
}
#[doc = "External event select for injected group"]
#[inline(always)]
pub const fn jextsel(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x0f;
val as u8
}
#[doc = "External event select for injected group"]
#[inline(always)]
pub fn set_jextsel(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
}
#[doc = "External trigger enable for injected channels"]
#[inline(always)]
pub const fn jexten(&self) -> super::vals::Exten {
let val = (self.0 >> 20usize) & 0x03;
super::vals::Exten::from_bits(val as u8)
}
#[doc = "External trigger enable for injected channels"]
#[inline(always)]
pub fn set_jexten(&mut self, val: super::vals::Exten) {
self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize);
}
#[doc = "Start conversion of injected channels"]
#[inline(always)]
pub const fn jswstart(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "Start conversion of injected channels"]
#[inline(always)]
pub fn set_jswstart(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "External event select for regular group"]
#[inline(always)]
pub const fn extsel(&self) -> u8 {
let val = (self.0 >> 24usize) & 0x0f;
val as u8
}
#[doc = "External event select for regular group"]
#[inline(always)]
pub fn set_extsel(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
}
#[doc = "External trigger enable for regular channels"]
#[inline(always)]
pub const fn exten(&self) -> super::vals::Exten {
let val = (self.0 >> 28usize) & 0x03;
super::vals::Exten::from_bits(val as u8)
}
#[doc = "External trigger enable for regular channels"]
#[inline(always)]
pub fn set_exten(&mut self, val: super::vals::Exten) {
self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize);
}
#[doc = "Start conversion of regular channels"]
#[inline(always)]
pub const fn swstart(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Start conversion of regular channels"]
#[inline(always)]
pub fn set_swstart(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
}
impl Default for Cr2 {
#[inline(always)]
fn default() -> Cr2 {
Cr2(0)
}
}
impl core::fmt::Debug for Cr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cr2")
.field("adon", &self.adon())
.field("cont", &self.cont())
.field("dma", &self.dma())
.field("dds", &self.dds())
.field("eocs", &self.eocs())
.field("align", &self.align())
.field("jextsel", &self.jextsel())
.field("jexten", &self.jexten())
.field("jswstart", &self.jswstart())
.field("extsel", &self.extsel())
.field("exten", &self.exten())
.field("swstart", &self.swstart())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cr2 {{ adon: {=bool:?}, cont: {=bool:?}, dma: {=bool:?}, dds: {:?}, eocs: {:?}, align: {:?}, jextsel: {=u8:?}, jexten: {:?}, jswstart: {=bool:?}, extsel: {=u8:?}, exten: {:?}, swstart: {=bool:?} }}" , self . adon () , self . cont () , self . dma () , self . dds () , self . eocs () , self . align () , self . jextsel () , self . jexten () , self . jswstart () , self . extsel () , self . exten () , self . swstart ())
}
}
#[doc = "regular data register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Dr(pub u32);
impl Dr {
#[doc = "Regular data"]
#[inline(always)]
pub const fn data(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[doc = "Regular data"]
#[inline(always)]
pub fn set_data(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
}
impl Default for Dr {
#[inline(always)]
fn default() -> Dr {
Dr(0)
}
}
impl core::fmt::Debug for Dr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Dr").field("data", &self.data()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Dr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Dr {{ data: {=u16:?} }}", self.data())
}
}
#[doc = "watchdog higher threshold register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Htr(pub u32);
impl Htr {
#[doc = "Analog watchdog higher threshold"]
#[inline(always)]
pub const fn ht(&self) -> u16 {
let val = (self.0 >> 0usize) & 0x0fff;
val as u16
}
#[doc = "Analog watchdog higher threshold"]
#[inline(always)]
pub fn set_ht(&mut self, val: u16) {
self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
}
}
impl Default for Htr {
#[inline(always)]
fn default() -> Htr {
Htr(0)
}
}
impl core::fmt::Debug for Htr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Htr").field("ht", &self.ht()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Htr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Htr {{ ht: {=u16:?} }}", self.ht())
}
}
#[doc = "injected data register x"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Jdr(pub u32);
impl Jdr {
#[doc = "Injected data"]
#[inline(always)]
pub const fn jdata(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[doc = "Injected data"]
#[inline(always)]
pub fn set_jdata(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
}
impl Default for Jdr {
#[inline(always)]
fn default() -> Jdr {
Jdr(0)
}
}
impl core::fmt::Debug for Jdr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Jdr").field("jdata", &self.jdata()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Jdr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Jdr {{ jdata: {=u16:?} }}", self.jdata())
}
}
#[doc = "injected channel data offset register x"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Jofr(pub u32);
impl Jofr {
#[doc = "Data offset for injected channel x"]
#[inline(always)]
pub const fn joffset(&self) -> u16 {
let val = (self.0 >> 0usize) & 0x0fff;
val as u16
}
#[doc = "Data offset for injected channel x"]
#[inline(always)]
pub fn set_joffset(&mut self, val: u16) {
self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
}
}
impl Default for Jofr {
#[inline(always)]
fn default() -> Jofr {
Jofr(0)
}
}
impl core::fmt::Debug for Jofr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Jofr").field("joffset", &self.joffset()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Jofr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Jofr {{ joffset: {=u16:?} }}", self.joffset())
}
}
#[doc = "injected sequence register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Jsqr(pub u32);
impl Jsqr {
#[doc = "1st conversion in injected sequence"]
#[inline(always)]
pub const fn jsq(&self, n: usize) -> u8 {
assert!(n < 4usize);
let offs = 0usize + n * 5usize;
let val = (self.0 >> offs) & 0x1f;
val as u8
}
#[doc = "1st conversion in injected sequence"]
#[inline(always)]
pub fn set_jsq(&mut self, n: usize, val: u8) {
assert!(n < 4usize);
let offs = 0usize + n * 5usize;
self.0 = (self.0 & !(0x1f << offs)) | (((val as u32) & 0x1f) << offs);
}
#[doc = "Injected sequence length"]
#[inline(always)]
pub const fn jl(&self) -> u8 {
let val = (self.0 >> 20usize) & 0x03;
val as u8
}
#[doc = "Injected sequence length"]
#[inline(always)]
pub fn set_jl(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
}
}
impl Default for Jsqr {
#[inline(always)]
fn default() -> Jsqr {
Jsqr(0)
}
}
impl core::fmt::Debug for Jsqr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Jsqr")
.field("jsq[0]", &self.jsq(0usize))
.field("jsq[1]", &self.jsq(1usize))
.field("jsq[2]", &self.jsq(2usize))
.field("jsq[3]", &self.jsq(3usize))
.field("jl", &self.jl())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Jsqr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Jsqr {{ jsq[0]: {=u8:?}, jsq[1]: {=u8:?}, jsq[2]: {=u8:?}, jsq[3]: {=u8:?}, jl: {=u8:?} }}",
self.jsq(0usize),
self.jsq(1usize),
self.jsq(2usize),
self.jsq(3usize),
self.jl()
)
}
}
#[doc = "watchdog lower threshold register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ltr(pub u32);
impl Ltr {
#[doc = "Analog watchdog lower threshold"]
#[inline(always)]
pub const fn lt(&self) -> u16 {
let val = (self.0 >> 0usize) & 0x0fff;
val as u16
}
#[doc = "Analog watchdog lower threshold"]
#[inline(always)]
pub fn set_lt(&mut self, val: u16) {
self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
}
}
impl Default for Ltr {
#[inline(always)]
fn default() -> Ltr {
Ltr(0)
}
}
impl core::fmt::Debug for Ltr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ltr").field("lt", &self.lt()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ltr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Ltr {{ lt: {=u16:?} }}", self.lt())
}
}
#[doc = "sample time register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Smpr1(pub u32);
impl Smpr1 {
#[doc = "Channel 10 sampling time selection"]
#[inline(always)]
pub const fn smp(&self, n: usize) -> super::vals::SampleTime {
assert!(n < 9usize);
let offs = 0usize + n * 3usize;
let val = (self.0 >> offs) & 0x07;
super::vals::SampleTime::from_bits(val as u8)
}
#[doc = "Channel 10 sampling time selection"]
#[inline(always)]
pub fn set_smp(&mut self, n: usize, val: super::vals::SampleTime) {
assert!(n < 9usize);
let offs = 0usize + n * 3usize;
self.0 = (self.0 & !(0x07 << offs)) | (((val.to_bits() as u32) & 0x07) << offs);
}
#[doc = "Sample time bits"]
#[inline(always)]
pub const fn smpx_x(&self) -> super::vals::SmprSmpxX {
let val = (self.0 >> 0usize) & 0xffff_ffff;
super::vals::SmprSmpxX::from_bits(val as u32)
}
#[doc = "Sample time bits"]
#[inline(always)]
pub fn set_smpx_x(&mut self, val: super::vals::SmprSmpxX) {
self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize);
}
}
impl Default for Smpr1 {
#[inline(always)]
fn default() -> Smpr1 {
Smpr1(0)
}
}
impl core::fmt::Debug for Smpr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Smpr1")
.field("smp[0]", &self.smp(0usize))
.field("smp[1]", &self.smp(1usize))
.field("smp[2]", &self.smp(2usize))
.field("smp[3]", &self.smp(3usize))
.field("smp[4]", &self.smp(4usize))
.field("smp[5]", &self.smp(5usize))
.field("smp[6]", &self.smp(6usize))
.field("smp[7]", &self.smp(7usize))
.field("smp[8]", &self.smp(8usize))
.field("smpx_x", &self.smpx_x())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Smpr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Smpr1 {{ smp[0]: {:?}, smp[1]: {:?}, smp[2]: {:?}, smp[3]: {:?}, smp[4]: {:?}, smp[5]: {:?}, smp[6]: {:?}, smp[7]: {:?}, smp[8]: {:?}, smpx_x: {:?} }}" , self . smp (0usize) , self . smp (1usize) , self . smp (2usize) , self . smp (3usize) , self . smp (4usize) , self . smp (5usize) , self . smp (6usize) , self . smp (7usize) , self . smp (8usize) , self . smpx_x ())
}
}
#[doc = "sample time register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Smpr2(pub u32);
impl Smpr2 {
#[doc = "Channel 0 sampling time selection"]
#[inline(always)]
pub const fn smp(&self, n: usize) -> super::vals::SampleTime {
assert!(n < 10usize);
let offs = 0usize + n * 3usize;
let val = (self.0 >> offs) & 0x07;
super::vals::SampleTime::from_bits(val as u8)
}
#[doc = "Channel 0 sampling time selection"]
#[inline(always)]
pub fn set_smp(&mut self, n: usize, val: super::vals::SampleTime) {
assert!(n < 10usize);
let offs = 0usize + n * 3usize;
self.0 = (self.0 & !(0x07 << offs)) | (((val.to_bits() as u32) & 0x07) << offs);
}
#[doc = "Sample time bits"]
#[inline(always)]
pub const fn smpx_x(&self) -> super::vals::SmprSmpxX {
let val = (self.0 >> 0usize) & 0xffff_ffff;
super::vals::SmprSmpxX::from_bits(val as u32)
}
#[doc = "Sample time bits"]
#[inline(always)]
pub fn set_smpx_x(&mut self, val: super::vals::SmprSmpxX) {
self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val.to_bits() as u32) & 0xffff_ffff) << 0usize);
}
}
impl Default for Smpr2 {
#[inline(always)]
fn default() -> Smpr2 {
Smpr2(0)
}
}
impl core::fmt::Debug for Smpr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Smpr2")
.field("smp[0]", &self.smp(0usize))
.field("smp[1]", &self.smp(1usize))
.field("smp[2]", &self.smp(2usize))
.field("smp[3]", &self.smp(3usize))
.field("smp[4]", &self.smp(4usize))
.field("smp[5]", &self.smp(5usize))
.field("smp[6]", &self.smp(6usize))
.field("smp[7]", &self.smp(7usize))
.field("smp[8]", &self.smp(8usize))
.field("smp[9]", &self.smp(9usize))
.field("smpx_x", &self.smpx_x())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Smpr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Smpr2 {{ smp[0]: {:?}, smp[1]: {:?}, smp[2]: {:?}, smp[3]: {:?}, smp[4]: {:?}, smp[5]: {:?}, smp[6]: {:?}, smp[7]: {:?}, smp[8]: {:?}, smp[9]: {:?}, smpx_x: {:?} }}" , self . smp (0usize) , self . smp (1usize) , self . smp (2usize) , self . smp (3usize) , self . smp (4usize) , self . smp (5usize) , self . smp (6usize) , self . smp (7usize) , self . smp (8usize) , self . smp (9usize) , self . smpx_x ())
}
}
#[doc = "regular sequence register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Sqr1(pub u32);
impl Sqr1 {
#[doc = "13th conversion in regular sequence"]
#[inline(always)]
pub const fn sq(&self, n: usize) -> u8 {
assert!(n < 4usize);
let offs = 0usize + n * 5usize;
let val = (self.0 >> offs) & 0x1f;
val as u8
}
#[doc = "13th conversion in regular sequence"]
#[inline(always)]
pub fn set_sq(&mut self, n: usize, val: u8) {
assert!(n < 4usize);
let offs = 0usize + n * 5usize;
self.0 = (self.0 & !(0x1f << offs)) | (((val as u32) & 0x1f) << offs);
}
#[doc = "Regular channel sequence length"]
#[inline(always)]
pub const fn l(&self) -> u8 {
let val = (self.0 >> 20usize) & 0x0f;
val as u8
}
#[doc = "Regular channel sequence length"]
#[inline(always)]
pub fn set_l(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 20usize)) | (((val as u32) & 0x0f) << 20usize);
}
}
impl Default for Sqr1 {
#[inline(always)]
fn default() -> Sqr1 {
Sqr1(0)
}
}
impl core::fmt::Debug for Sqr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sqr1")
.field("sq[0]", &self.sq(0usize))
.field("sq[1]", &self.sq(1usize))
.field("sq[2]", &self.sq(2usize))
.field("sq[3]", &self.sq(3usize))
.field("l", &self.l())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Sqr1 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Sqr1 {{ sq[0]: {=u8:?}, sq[1]: {=u8:?}, sq[2]: {=u8:?}, sq[3]: {=u8:?}, l: {=u8:?} }}",
self.sq(0usize),
self.sq(1usize),
self.sq(2usize),
self.sq(3usize),
self.l()
)
}
}
#[doc = "regular sequence register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Sqr2(pub u32);
impl Sqr2 {
#[doc = "7th conversion in regular sequence"]
#[inline(always)]
pub const fn sq(&self, n: usize) -> u8 {
assert!(n < 6usize);
let offs = 0usize + n * 5usize;
let val = (self.0 >> offs) & 0x1f;
val as u8
}
#[doc = "7th conversion in regular sequence"]
#[inline(always)]
pub fn set_sq(&mut self, n: usize, val: u8) {
assert!(n < 6usize);
let offs = 0usize + n * 5usize;
self.0 = (self.0 & !(0x1f << offs)) | (((val as u32) & 0x1f) << offs);
}
}
impl Default for Sqr2 {
#[inline(always)]
fn default() -> Sqr2 {
Sqr2(0)
}
}
impl core::fmt::Debug for Sqr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sqr2")
.field("sq[0]", &self.sq(0usize))
.field("sq[1]", &self.sq(1usize))
.field("sq[2]", &self.sq(2usize))
.field("sq[3]", &self.sq(3usize))
.field("sq[4]", &self.sq(4usize))
.field("sq[5]", &self.sq(5usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Sqr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Sqr2 {{ sq[0]: {=u8:?}, sq[1]: {=u8:?}, sq[2]: {=u8:?}, sq[3]: {=u8:?}, sq[4]: {=u8:?}, sq[5]: {=u8:?} }}" , self . sq (0usize) , self . sq (1usize) , self . sq (2usize) , self . sq (3usize) , self . sq (4usize) , self . sq (5usize))
}
}
#[doc = "regular sequence register 3"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Sqr3(pub u32);
impl Sqr3 {
#[doc = "1st conversion in regular sequence"]
#[inline(always)]
pub const fn sq(&self, n: usize) -> u8 {
assert!(n < 6usize);
let offs = 0usize + n * 5usize;
let val = (self.0 >> offs) & 0x1f;
val as u8
}
#[doc = "1st conversion in regular sequence"]
#[inline(always)]
pub fn set_sq(&mut self, n: usize, val: u8) {
assert!(n < 6usize);
let offs = 0usize + n * 5usize;
self.0 = (self.0 & !(0x1f << offs)) | (((val as u32) & 0x1f) << offs);
}
}
impl Default for Sqr3 {
#[inline(always)]
fn default() -> Sqr3 {
Sqr3(0)
}
}
impl core::fmt::Debug for Sqr3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sqr3")
.field("sq[0]", &self.sq(0usize))
.field("sq[1]", &self.sq(1usize))
.field("sq[2]", &self.sq(2usize))
.field("sq[3]", &self.sq(3usize))
.field("sq[4]", &self.sq(4usize))
.field("sq[5]", &self.sq(5usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Sqr3 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Sqr3 {{ sq[0]: {=u8:?}, sq[1]: {=u8:?}, sq[2]: {=u8:?}, sq[3]: {=u8:?}, sq[4]: {=u8:?}, sq[5]: {=u8:?} }}" , self . sq (0usize) , self . sq (1usize) , self . sq (2usize) , self . sq (3usize) , self . sq (4usize) , self . sq (5usize))
}
}
#[doc = "status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Sr(pub u32);
impl Sr {
#[doc = "Analog watchdog event occurred"]
#[inline(always)]
pub const fn awd(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Analog watchdog event occurred"]
#[inline(always)]
pub fn set_awd(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Regular channel end of conversion"]
#[inline(always)]
pub const fn eoc(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Regular channel end of conversion"]
#[inline(always)]
pub fn set_eoc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Injected channel end of conversion"]
#[inline(always)]
pub const fn jeoc(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Injected channel end of conversion"]
#[inline(always)]
pub fn set_jeoc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Injected channel conversion has started"]
#[inline(always)]
pub const fn jstrt(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Injected channel conversion has started"]
#[inline(always)]
pub fn set_jstrt(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "Regular channel conversion has started"]
#[inline(always)]
pub const fn strt(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "Regular channel conversion has started"]
#[inline(always)]
pub fn set_strt(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "Overrun occurred"]
#[inline(always)]
pub const fn ovr(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Overrun occurred"]
#[inline(always)]
pub fn set_ovr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
}
impl Default for Sr {
#[inline(always)]
fn default() -> Sr {
Sr(0)
}
}
impl core::fmt::Debug for Sr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sr")
.field("awd", &self.awd())
.field("eoc", &self.eoc())
.field("jeoc", &self.jeoc())
.field("jstrt", &self.jstrt())
.field("strt", &self.strt())
.field("ovr", &self.ovr())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Sr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Sr {{ awd: {=bool:?}, eoc: {=bool:?}, jeoc: {=bool:?}, jstrt: {=bool:?}, strt: {=bool:?}, ovr: {=bool:?} }}" , self . awd () , self . eoc () , self . jeoc () , self . jstrt () , self . strt () , self . ovr ())
}
}
}
pub mod vals {
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Align {
#[doc = "Right alignment"]
RIGHT = 0x0,
#[doc = "Left alignment"]
LEFT = 0x01,
}
impl Align {
#[inline(always)]
pub const fn from_bits(val: u8) -> Align {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Align {
#[inline(always)]
fn from(val: u8) -> Align {
Align::from_bits(val)
}
}
impl From<Align> for u8 {
#[inline(always)]
fn from(val: Align) -> u8 {
Align::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Awdsgl {
#[doc = "Analog watchdog enabled on all channels"]
ALL_CHANNELS = 0x0,
#[doc = "Analog watchdog enabled on a single channel"]
SINGLE_CHANNEL = 0x01,
}
impl Awdsgl {
#[inline(always)]
pub const fn from_bits(val: u8) -> Awdsgl {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Awdsgl {
#[inline(always)]
fn from(val: u8) -> Awdsgl {
Awdsgl::from_bits(val)
}
}
impl From<Awdsgl> for u8 {
#[inline(always)]
fn from(val: Awdsgl) -> u8 {
Awdsgl::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Dds {
#[doc = "No new DMA request is issued after the last transfer"]
SINGLE = 0x0,
#[doc = "DMA requests are issued as long as data are converted and DMA=1"]
CONTINUOUS = 0x01,
}
impl Dds {
#[inline(always)]
pub const fn from_bits(val: u8) -> Dds {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Dds {
#[inline(always)]
fn from(val: u8) -> Dds {
Dds::from_bits(val)
}
}
impl From<Dds> for u8 {
#[inline(always)]
fn from(val: Dds) -> u8 {
Dds::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Eocs {
#[doc = "The EOC bit is set at the end of each sequence of regular conversions"]
EACH_SEQUENCE = 0x0,
#[doc = "The EOC bit is set at the end of each regular conversion"]
EACH_CONVERSION = 0x01,
}
impl Eocs {
#[inline(always)]
pub const fn from_bits(val: u8) -> Eocs {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Eocs {
#[inline(always)]
fn from(val: u8) -> Eocs {
Eocs::from_bits(val)
}
}
impl From<Eocs> for u8 {
#[inline(always)]
fn from(val: Eocs) -> u8 {
Eocs::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Exten {
#[doc = "Trigger detection disabled"]
DISABLED = 0x0,
#[doc = "Trigger detection on the rising edge"]
RISING_EDGE = 0x01,
#[doc = "Trigger detection on the falling edge"]
FALLING_EDGE = 0x02,
#[doc = "Trigger detection on both the rising and falling edges"]
BOTH_EDGES = 0x03,
}
impl Exten {
#[inline(always)]
pub const fn from_bits(val: u8) -> Exten {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Exten {
#[inline(always)]
fn from(val: u8) -> Exten {
Exten::from_bits(val)
}
}
impl From<Exten> for u8 {
#[inline(always)]
fn from(val: Exten) -> u8 {
Exten::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Res {
#[doc = "12-bit (15 ADCCLK cycles)"]
BITS12 = 0x0,
#[doc = "10-bit (13 ADCCLK cycles)"]
BITS10 = 0x01,
#[doc = "8-bit (11 ADCCLK cycles)"]
BITS8 = 0x02,
#[doc = "6-bit (9 ADCCLK cycles)"]
BITS6 = 0x03,
}
impl Res {
#[inline(always)]
pub const fn from_bits(val: u8) -> Res {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Res {
#[inline(always)]
fn from(val: u8) -> Res {
Res::from_bits(val)
}
}
impl From<Res> for u8 {
#[inline(always)]
fn from(val: Res) -> u8 {
Res::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum SampleTime {
#[doc = "3 cycles"]
CYCLES3 = 0x0,
#[doc = "15 cycles"]
CYCLES15 = 0x01,
#[doc = "28 cycles"]
CYCLES28 = 0x02,
#[doc = "56 cycles"]
CYCLES56 = 0x03,
#[doc = "84 cycles"]
CYCLES84 = 0x04,
#[doc = "112 cycles"]
CYCLES112 = 0x05,
#[doc = "144 cycles"]
CYCLES144 = 0x06,
#[doc = "480 cycles"]
CYCLES480 = 0x07,
}
impl SampleTime {
#[inline(always)]
pub const fn from_bits(val: u8) -> SampleTime {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for SampleTime {
#[inline(always)]
fn from(val: u8) -> SampleTime {
SampleTime::from_bits(val)
}
}
impl From<SampleTime> for u8 {
#[inline(always)]
fn from(val: SampleTime) -> u8 {
SampleTime::to_bits(val)
}
}
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
pub struct SmprSmpxX(u32);
impl SmprSmpxX {
#[doc = "3 cycles"]
pub const CYCLES3: Self = Self(0x0);
#[doc = "15 cycles"]
pub const CYCLES15: Self = Self(0x01);
#[doc = "28 cycles"]
pub const CYCLES28: Self = Self(0x02);
#[doc = "56 cycles"]
pub const CYCLES56: Self = Self(0x03);
#[doc = "84 cycles"]
pub const CYCLES84: Self = Self(0x04);
#[doc = "112 cycles"]
pub const CYCLES112: Self = Self(0x05);
#[doc = "144 cycles"]
pub const CYCLES144: Self = Self(0x06);
#[doc = "480 cycles"]
pub const CYCLES480: Self = Self(0x07);
}
impl SmprSmpxX {
pub const fn from_bits(val: u32) -> SmprSmpxX {
Self(val & 0xffff_ffff)
}
pub const fn to_bits(self) -> u32 {
self.0
}
}
impl core::fmt::Debug for SmprSmpxX {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
match self.0 {
0x0 => f.write_str("CYCLES3"),
0x01 => f.write_str("CYCLES15"),
0x02 => f.write_str("CYCLES28"),
0x03 => f.write_str("CYCLES56"),
0x04 => f.write_str("CYCLES84"),
0x05 => f.write_str("CYCLES112"),
0x06 => f.write_str("CYCLES144"),
0x07 => f.write_str("CYCLES480"),
other => core::write!(f, "0x{:02X}", other),
}
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for SmprSmpxX {
fn format(&self, f: defmt::Formatter) {
match self.0 {
0x0 => defmt::write!(f, "CYCLES3"),
0x01 => defmt::write!(f, "CYCLES15"),
0x02 => defmt::write!(f, "CYCLES28"),
0x03 => defmt::write!(f, "CYCLES56"),
0x04 => defmt::write!(f, "CYCLES84"),
0x05 => defmt::write!(f, "CYCLES112"),
0x06 => defmt::write!(f, "CYCLES144"),
0x07 => defmt::write!(f, "CYCLES480"),
other => defmt::write!(f, "0x{:02X}", other),
}
}
}
impl From<u32> for SmprSmpxX {
#[inline(always)]
fn from(val: u32) -> SmprSmpxX {
SmprSmpxX::from_bits(val)
}
}
impl From<SmprSmpxX> for u32 {
#[inline(always)]
fn from(val: SmprSmpxX) -> u32 {
SmprSmpxX::to_bits(val)
}
}
}