#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
#[doc = "Analog to Digital Converter"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Adc {
ptr: *mut u8,
}
unsafe impl Send for Adc {}
unsafe impl Sync for Adc {}
impl Adc {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "ADC interrupt and status register"]
#[inline(always)]
pub const fn isr(self) -> crate::common::Reg<regs::Isr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "ADC interrupt enable register"]
#[inline(always)]
pub const fn ier(self) -> crate::common::Reg<regs::Ier, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "ADC control register"]
#[inline(always)]
pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
}
#[doc = "ADC configuration register 1"]
#[inline(always)]
pub const fn cfgr1(self) -> crate::common::Reg<regs::Cfgr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
#[doc = "ADC configuration register 2"]
#[inline(always)]
pub const fn cfgr2(self) -> crate::common::Reg<regs::Cfgr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
}
#[doc = "ADC sampling time register"]
#[inline(always)]
pub const fn smpr(self) -> crate::common::Reg<regs::Smpr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
}
#[doc = "watchdog threshold register"]
#[inline(always)]
pub const fn awd1tr(self) -> crate::common::Reg<regs::Awd1tr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
}
#[doc = "watchdog threshold register"]
#[inline(always)]
pub const fn awd2tr(self) -> crate::common::Reg<regs::Awd2tr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
}
#[doc = "channel selection register"]
#[inline(always)]
pub const fn chselr(self) -> crate::common::Reg<regs::Chselr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
}
#[doc = "channel selection register CHSELRMOD = 1 in ADC_CFGR1"]
#[inline(always)]
pub const fn chselr_1(self) -> crate::common::Reg<regs::Chselr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
}
#[doc = "watchdog threshold register"]
#[inline(always)]
pub const fn awd3tr(self) -> crate::common::Reg<regs::Awd3tr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
}
#[doc = "ADC group regular conversion data register"]
#[inline(always)]
pub const fn dr(self) -> crate::common::Reg<regs::Dr, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
}
#[doc = "ADC analog watchdog 2 configuration register"]
#[inline(always)]
pub const fn awd2cr(self) -> crate::common::Reg<regs::Awd2cr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) }
}
#[doc = "ADC analog watchdog 3 configuration register"]
#[inline(always)]
pub const fn awd3cr(self) -> crate::common::Reg<regs::Awd3cr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) }
}
#[doc = "ADC calibration factors register"]
#[inline(always)]
pub const fn calfact(self) -> crate::common::Reg<regs::Calfact, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb4usize) as _) }
}
#[doc = "ADC common control register"]
#[inline(always)]
pub const fn ccr(self) -> crate::common::Reg<regs::Ccr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) }
}
}
pub mod regs {
#[doc = "watchdog threshold register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Awd1tr(pub u32);
impl Awd1tr {
#[doc = "ADC analog watchdog 1 threshold low"]
#[inline(always)]
pub const fn lt1(&self) -> u16 {
let val = (self.0 >> 0usize) & 0x0fff;
val as u16
}
#[doc = "ADC analog watchdog 1 threshold low"]
#[inline(always)]
pub fn set_lt1(&mut self, val: u16) {
self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
}
#[doc = "ADC analog watchdog 1 threshold high"]
#[inline(always)]
pub const fn ht1(&self) -> u16 {
let val = (self.0 >> 16usize) & 0x0fff;
val as u16
}
#[doc = "ADC analog watchdog 1 threshold high"]
#[inline(always)]
pub fn set_ht1(&mut self, val: u16) {
self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
}
}
impl Default for Awd1tr {
#[inline(always)]
fn default() -> Awd1tr {
Awd1tr(0)
}
}
impl core::fmt::Debug for Awd1tr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Awd1tr")
.field("lt1", &self.lt1())
.field("ht1", &self.ht1())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Awd1tr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Awd1tr {{ lt1: {=u16:?}, ht1: {=u16:?} }}", self.lt1(), self.ht1())
}
}
#[doc = "ADC analog watchdog 2 configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Awd2cr(pub u32);
impl Awd2cr {
#[doc = "ADC analog watchdog 2 monitored channel selection"]
#[inline(always)]
pub const fn awd2ch(&self) -> u32 {
let val = (self.0 >> 0usize) & 0x0007_ffff;
val as u32
}
#[doc = "ADC analog watchdog 2 monitored channel selection"]
#[inline(always)]
pub fn set_awd2ch(&mut self, val: u32) {
self.0 = (self.0 & !(0x0007_ffff << 0usize)) | (((val as u32) & 0x0007_ffff) << 0usize);
}
}
impl Default for Awd2cr {
#[inline(always)]
fn default() -> Awd2cr {
Awd2cr(0)
}
}
impl core::fmt::Debug for Awd2cr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Awd2cr").field("awd2ch", &self.awd2ch()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Awd2cr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Awd2cr {{ awd2ch: {=u32:?} }}", self.awd2ch())
}
}
#[doc = "watchdog threshold register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Awd2tr(pub u32);
impl Awd2tr {
#[doc = "ADC analog watchdog 2 threshold low"]
#[inline(always)]
pub const fn lt2(&self) -> u16 {
let val = (self.0 >> 0usize) & 0x0fff;
val as u16
}
#[doc = "ADC analog watchdog 2 threshold low"]
#[inline(always)]
pub fn set_lt2(&mut self, val: u16) {
self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
}
#[doc = "ADC analog watchdog 2 threshold high"]
#[inline(always)]
pub const fn ht2(&self) -> u16 {
let val = (self.0 >> 16usize) & 0x0fff;
val as u16
}
#[doc = "ADC analog watchdog 2 threshold high"]
#[inline(always)]
pub fn set_ht2(&mut self, val: u16) {
self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
}
}
impl Default for Awd2tr {
#[inline(always)]
fn default() -> Awd2tr {
Awd2tr(0)
}
}
impl core::fmt::Debug for Awd2tr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Awd2tr")
.field("lt2", &self.lt2())
.field("ht2", &self.ht2())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Awd2tr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Awd2tr {{ lt2: {=u16:?}, ht2: {=u16:?} }}", self.lt2(), self.ht2())
}
}
#[doc = "ADC analog watchdog 3 configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Awd3cr(pub u32);
impl Awd3cr {
#[doc = "ADC analog watchdog 3 monitored channel selection"]
#[inline(always)]
pub const fn awd3ch(&self) -> u32 {
let val = (self.0 >> 0usize) & 0x0007_ffff;
val as u32
}
#[doc = "ADC analog watchdog 3 monitored channel selection"]
#[inline(always)]
pub fn set_awd3ch(&mut self, val: u32) {
self.0 = (self.0 & !(0x0007_ffff << 0usize)) | (((val as u32) & 0x0007_ffff) << 0usize);
}
}
impl Default for Awd3cr {
#[inline(always)]
fn default() -> Awd3cr {
Awd3cr(0)
}
}
impl core::fmt::Debug for Awd3cr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Awd3cr").field("awd3ch", &self.awd3ch()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Awd3cr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Awd3cr {{ awd3ch: {=u32:?} }}", self.awd3ch())
}
}
#[doc = "watchdog threshold register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Awd3tr(pub u32);
impl Awd3tr {
#[doc = "ADC analog watchdog 3 threshold high"]
#[inline(always)]
pub const fn lt3(&self) -> u16 {
let val = (self.0 >> 0usize) & 0x0fff;
val as u16
}
#[doc = "ADC analog watchdog 3 threshold high"]
#[inline(always)]
pub fn set_lt3(&mut self, val: u16) {
self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
}
#[doc = "ADC analog watchdog 3 threshold high"]
#[inline(always)]
pub const fn ht3(&self) -> u16 {
let val = (self.0 >> 16usize) & 0x0fff;
val as u16
}
#[doc = "ADC analog watchdog 3 threshold high"]
#[inline(always)]
pub fn set_ht3(&mut self, val: u16) {
self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
}
}
impl Default for Awd3tr {
#[inline(always)]
fn default() -> Awd3tr {
Awd3tr(0)
}
}
impl core::fmt::Debug for Awd3tr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Awd3tr")
.field("lt3", &self.lt3())
.field("ht3", &self.ht3())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Awd3tr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Awd3tr {{ lt3: {=u16:?}, ht3: {=u16:?} }}", self.lt3(), self.ht3())
}
}
#[doc = "ADC calibration factors register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Calfact(pub u32);
impl Calfact {
#[doc = "ADC calibration factor in single-ended mode"]
#[inline(always)]
pub const fn calfact(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x7f;
val as u8
}
#[doc = "ADC calibration factor in single-ended mode"]
#[inline(always)]
pub fn set_calfact(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
}
}
impl Default for Calfact {
#[inline(always)]
fn default() -> Calfact {
Calfact(0)
}
}
impl core::fmt::Debug for Calfact {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Calfact").field("calfact", &self.calfact()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Calfact {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Calfact {{ calfact: {=u8:?} }}", self.calfact())
}
}
#[doc = "ADC common control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ccr(pub u32);
impl Ccr {
#[doc = "ADC prescaler"]
#[inline(always)]
pub const fn presc(&self) -> u8 {
let val = (self.0 >> 18usize) & 0x0f;
val as u8
}
#[doc = "ADC prescaler"]
#[inline(always)]
pub fn set_presc(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 18usize)) | (((val as u32) & 0x0f) << 18usize);
}
#[doc = "VREFINT enable"]
#[inline(always)]
pub const fn vrefen(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "VREFINT enable"]
#[inline(always)]
pub fn set_vrefen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "Temperature sensor enable"]
#[inline(always)]
pub const fn tsen(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Temperature sensor enable"]
#[inline(always)]
pub fn set_tsen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "VBAT enable"]
#[inline(always)]
pub const fn vbaten(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "VBAT enable"]
#[inline(always)]
pub fn set_vbaten(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
}
impl Default for Ccr {
#[inline(always)]
fn default() -> Ccr {
Ccr(0)
}
}
impl core::fmt::Debug for Ccr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ccr")
.field("presc", &self.presc())
.field("vrefen", &self.vrefen())
.field("tsen", &self.tsen())
.field("vbaten", &self.vbaten())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ccr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ccr {{ presc: {=u8:?}, vrefen: {=bool:?}, tsen: {=bool:?}, vbaten: {=bool:?} }}",
self.presc(),
self.vrefen(),
self.tsen(),
self.vbaten()
)
}
}
#[doc = "ADC configuration register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfgr1(pub u32);
impl Cfgr1 {
#[doc = "ADC DMA transfer enable"]
#[inline(always)]
pub const fn dmaen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "ADC DMA transfer enable"]
#[inline(always)]
pub fn set_dmaen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Direct memory access configuration"]
#[inline(always)]
pub const fn dmacfg(&self) -> super::vals::Dmacfg {
let val = (self.0 >> 1usize) & 0x01;
super::vals::Dmacfg::from_bits(val as u8)
}
#[doc = "Direct memory access configuration"]
#[inline(always)]
pub fn set_dmacfg(&mut self, val: super::vals::Dmacfg) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize);
}
#[doc = "Scan sequence direction"]
#[inline(always)]
pub const fn scandir(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Scan sequence direction"]
#[inline(always)]
pub fn set_scandir(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "ADC data resolution"]
#[inline(always)]
pub const fn res(&self) -> super::vals::Res {
let val = (self.0 >> 3usize) & 0x03;
super::vals::Res::from_bits(val as u8)
}
#[doc = "ADC data resolution"]
#[inline(always)]
pub fn set_res(&mut self, val: super::vals::Res) {
self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
}
#[doc = "ADC data alignement"]
#[inline(always)]
pub const fn align(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "ADC data alignement"]
#[inline(always)]
pub fn set_align(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "ADC group regular external trigger source"]
#[inline(always)]
pub const fn extsel(&self) -> u8 {
let val = (self.0 >> 6usize) & 0x07;
val as u8
}
#[doc = "ADC group regular external trigger source"]
#[inline(always)]
pub fn set_extsel(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 6usize)) | (((val as u32) & 0x07) << 6usize);
}
#[doc = "ADC group regular external trigger polarity"]
#[inline(always)]
pub const fn exten(&self) -> u8 {
let val = (self.0 >> 10usize) & 0x03;
val as u8
}
#[doc = "ADC group regular external trigger polarity"]
#[inline(always)]
pub fn set_exten(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
}
#[doc = "ADC group regular overrun configuration"]
#[inline(always)]
pub const fn ovrmod(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "ADC group regular overrun configuration"]
#[inline(always)]
pub fn set_ovrmod(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "Continuous conversion"]
#[inline(always)]
pub const fn cont(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "Continuous conversion"]
#[inline(always)]
pub fn set_cont(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "Wait conversion mode"]
#[inline(always)]
pub const fn wait(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "Wait conversion mode"]
#[inline(always)]
pub fn set_wait(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "Auto-off mode"]
#[inline(always)]
pub const fn autoff(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "Auto-off mode"]
#[inline(always)]
pub fn set_autoff(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "ADC group regular sequencer discontinuous mode"]
#[inline(always)]
pub const fn discen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "ADC group regular sequencer discontinuous mode"]
#[inline(always)]
pub fn set_discen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Mode selection of the ADC_CHSELR register"]
#[inline(always)]
pub const fn chselrmod(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "Mode selection of the ADC_CHSELR register"]
#[inline(always)]
pub fn set_chselrmod(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "ADC analog watchdog 1 monitoring a single channel or all channels"]
#[inline(always)]
pub const fn awd1sgl(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "ADC analog watchdog 1 monitoring a single channel or all channels"]
#[inline(always)]
pub fn set_awd1sgl(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "ADC analog watchdog 1 enable on scope ADC group regular"]
#[inline(always)]
pub const fn awd1en(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "ADC analog watchdog 1 enable on scope ADC group regular"]
#[inline(always)]
pub fn set_awd1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "ADC analog watchdog 1 monitored channel selection"]
#[inline(always)]
pub const fn awdch1ch(&self) -> u8 {
let val = (self.0 >> 26usize) & 0x1f;
val as u8
}
#[doc = "ADC analog watchdog 1 monitored channel selection"]
#[inline(always)]
pub fn set_awdch1ch(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 26usize)) | (((val as u32) & 0x1f) << 26usize);
}
}
impl Default for Cfgr1 {
#[inline(always)]
fn default() -> Cfgr1 {
Cfgr1(0)
}
}
impl core::fmt::Debug for Cfgr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cfgr1")
.field("dmaen", &self.dmaen())
.field("dmacfg", &self.dmacfg())
.field("scandir", &self.scandir())
.field("res", &self.res())
.field("align", &self.align())
.field("extsel", &self.extsel())
.field("exten", &self.exten())
.field("ovrmod", &self.ovrmod())
.field("cont", &self.cont())
.field("wait", &self.wait())
.field("autoff", &self.autoff())
.field("discen", &self.discen())
.field("chselrmod", &self.chselrmod())
.field("awd1sgl", &self.awd1sgl())
.field("awd1en", &self.awd1en())
.field("awdch1ch", &self.awdch1ch())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cfgr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cfgr1 {{ dmaen: {=bool:?}, dmacfg: {:?}, scandir: {=bool:?}, res: {:?}, align: {=bool:?}, extsel: {=u8:?}, exten: {=u8:?}, ovrmod: {=bool:?}, cont: {=bool:?}, wait: {=bool:?}, autoff: {=bool:?}, discen: {=bool:?}, chselrmod: {=bool:?}, awd1sgl: {=bool:?}, awd1en: {=bool:?}, awdch1ch: {=u8:?} }}" , self . dmaen () , self . dmacfg () , self . scandir () , self . res () , self . align () , self . extsel () , self . exten () , self . ovrmod () , self . cont () , self . wait () , self . autoff () , self . discen () , self . chselrmod () , self . awd1sgl () , self . awd1en () , self . awdch1ch ())
}
}
#[doc = "ADC configuration register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfgr2(pub u32);
impl Cfgr2 {
#[doc = "ADC oversampler enable on scope ADC group regular"]
#[inline(always)]
pub const fn ovse(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "ADC oversampler enable on scope ADC group regular"]
#[inline(always)]
pub fn set_ovse(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "ADC oversampling ratio"]
#[inline(always)]
pub const fn ovsr(&self) -> u8 {
let val = (self.0 >> 2usize) & 0x07;
val as u8
}
#[doc = "ADC oversampling ratio"]
#[inline(always)]
pub fn set_ovsr(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 2usize)) | (((val as u32) & 0x07) << 2usize);
}
#[doc = "ADC oversampling shift"]
#[inline(always)]
pub const fn ovss(&self) -> u8 {
let val = (self.0 >> 5usize) & 0x0f;
val as u8
}
#[doc = "ADC oversampling shift"]
#[inline(always)]
pub fn set_ovss(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 5usize)) | (((val as u32) & 0x0f) << 5usize);
}
#[doc = "ADC oversampling discontinuous mode (triggered mode) for ADC group regular"]
#[inline(always)]
pub const fn tovs(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "ADC oversampling discontinuous mode (triggered mode) for ADC group regular"]
#[inline(always)]
pub fn set_tovs(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "Low frequency trigger mode enable"]
#[inline(always)]
pub const fn lftrig(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "Low frequency trigger mode enable"]
#[inline(always)]
pub fn set_lftrig(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "ADC clock mode"]
#[inline(always)]
pub const fn ckmode(&self) -> u8 {
let val = (self.0 >> 30usize) & 0x03;
val as u8
}
#[doc = "ADC clock mode"]
#[inline(always)]
pub fn set_ckmode(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 30usize)) | (((val as u32) & 0x03) << 30usize);
}
}
impl Default for Cfgr2 {
#[inline(always)]
fn default() -> Cfgr2 {
Cfgr2(0)
}
}
impl core::fmt::Debug for Cfgr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cfgr2")
.field("ovse", &self.ovse())
.field("ovsr", &self.ovsr())
.field("ovss", &self.ovss())
.field("tovs", &self.tovs())
.field("lftrig", &self.lftrig())
.field("ckmode", &self.ckmode())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cfgr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cfgr2 {{ ovse: {=bool:?}, ovsr: {=u8:?}, ovss: {=u8:?}, tovs: {=bool:?}, lftrig: {=bool:?}, ckmode: {=u8:?} }}" , self . ovse () , self . ovsr () , self . ovss () , self . tovs () , self . lftrig () , self . ckmode ())
}
}
#[doc = "channel selection register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Chselr(pub u32);
impl Chselr {
#[doc = "Channel-x selection"]
#[inline(always)]
pub const fn chsel(&self) -> u32 {
let val = (self.0 >> 0usize) & 0x0007_ffff;
val as u32
}
#[doc = "Channel-x selection"]
#[inline(always)]
pub fn set_chsel(&mut self, val: u32) {
self.0 = (self.0 & !(0x0007_ffff << 0usize)) | (((val as u32) & 0x0007_ffff) << 0usize);
}
}
impl Default for Chselr {
#[inline(always)]
fn default() -> Chselr {
Chselr(0)
}
}
impl core::fmt::Debug for Chselr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Chselr").field("chsel", &self.chsel()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Chselr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Chselr {{ chsel: {=u32:?} }}", self.chsel())
}
}
#[doc = "channel selection register CHSELRMOD = 1 in ADC_CFGR1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Chselr1(pub u32);
impl Chselr1 {
#[doc = "conversion of the sequence"]
#[inline(always)]
pub const fn sq1(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x0f;
val as u8
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub fn set_sq1(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub const fn sq2(&self) -> u8 {
let val = (self.0 >> 4usize) & 0x0f;
val as u8
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub fn set_sq2(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub const fn sq3(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x0f;
val as u8
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub fn set_sq3(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub const fn sq4(&self) -> u8 {
let val = (self.0 >> 12usize) & 0x0f;
val as u8
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub fn set_sq4(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 12usize)) | (((val as u32) & 0x0f) << 12usize);
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub const fn sq5(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x0f;
val as u8
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub fn set_sq5(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub const fn sq6(&self) -> u8 {
let val = (self.0 >> 20usize) & 0x0f;
val as u8
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub fn set_sq6(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 20usize)) | (((val as u32) & 0x0f) << 20usize);
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub const fn sq7(&self) -> u8 {
let val = (self.0 >> 24usize) & 0x0f;
val as u8
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub fn set_sq7(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub const fn sq8(&self) -> u8 {
let val = (self.0 >> 28usize) & 0x0f;
val as u8
}
#[doc = "conversion of the sequence"]
#[inline(always)]
pub fn set_sq8(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize);
}
}
impl Default for Chselr1 {
#[inline(always)]
fn default() -> Chselr1 {
Chselr1(0)
}
}
impl core::fmt::Debug for Chselr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Chselr1")
.field("sq1", &self.sq1())
.field("sq2", &self.sq2())
.field("sq3", &self.sq3())
.field("sq4", &self.sq4())
.field("sq5", &self.sq5())
.field("sq6", &self.sq6())
.field("sq7", &self.sq7())
.field("sq8", &self.sq8())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Chselr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Chselr1 {{ sq1: {=u8:?}, sq2: {=u8:?}, sq3: {=u8:?}, sq4: {=u8:?}, sq5: {=u8:?}, sq6: {=u8:?}, sq7: {=u8:?}, sq8: {=u8:?} }}" , self . sq1 () , self . sq2 () , self . sq3 () , self . sq4 () , self . sq5 () , self . sq6 () , self . sq7 () , self . sq8 ())
}
}
#[doc = "ADC control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr(pub u32);
impl Cr {
#[doc = "ADC enable"]
#[inline(always)]
pub const fn aden(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "ADC enable"]
#[inline(always)]
pub fn set_aden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "ADC disable"]
#[inline(always)]
pub const fn addis(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "ADC disable"]
#[inline(always)]
pub fn set_addis(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "ADC group regular conversion start"]
#[inline(always)]
pub const fn adstart(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "ADC group regular conversion start"]
#[inline(always)]
pub fn set_adstart(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "ADC group regular conversion stop"]
#[inline(always)]
pub const fn adstp(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "ADC group regular conversion stop"]
#[inline(always)]
pub fn set_adstp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "ADC voltage regulator enable"]
#[inline(always)]
pub const fn advregen(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "ADC voltage regulator enable"]
#[inline(always)]
pub fn set_advregen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "ADC calibration"]
#[inline(always)]
pub const fn adcal(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "ADC calibration"]
#[inline(always)]
pub fn set_adcal(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Cr {
#[inline(always)]
fn default() -> Cr {
Cr(0)
}
}
impl core::fmt::Debug for Cr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cr")
.field("aden", &self.aden())
.field("addis", &self.addis())
.field("adstart", &self.adstart())
.field("adstp", &self.adstp())
.field("advregen", &self.advregen())
.field("adcal", &self.adcal())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cr {{ aden: {=bool:?}, addis: {=bool:?}, adstart: {=bool:?}, adstp: {=bool:?}, advregen: {=bool:?}, adcal: {=bool:?} }}" , self . aden () , self . addis () , self . adstart () , self . adstp () , self . advregen () , self . adcal ())
}
}
#[doc = "ADC group regular conversion data register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Dr(pub u32);
impl Dr {
#[doc = "ADC group regular conversion data"]
#[inline(always)]
pub const fn regular_data(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[doc = "ADC group regular conversion data"]
#[inline(always)]
pub fn set_regular_data(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
}
impl Default for Dr {
#[inline(always)]
fn default() -> Dr {
Dr(0)
}
}
impl core::fmt::Debug for Dr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Dr")
.field("regular_data", &self.regular_data())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Dr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Dr {{ regular_data: {=u16:?} }}", self.regular_data())
}
}
#[doc = "ADC interrupt enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ier(pub u32);
impl Ier {
#[doc = "ADC ready interrupt"]
#[inline(always)]
pub const fn adrdyie(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "ADC ready interrupt"]
#[inline(always)]
pub fn set_adrdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "ADC group regular end of sampling interrupt"]
#[inline(always)]
pub const fn eosmpie(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "ADC group regular end of sampling interrupt"]
#[inline(always)]
pub fn set_eosmpie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "ADC group regular end of unitary conversion interrupt"]
#[inline(always)]
pub const fn eocie(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "ADC group regular end of unitary conversion interrupt"]
#[inline(always)]
pub fn set_eocie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "ADC group regular end of sequence conversions interrupt"]
#[inline(always)]
pub const fn eosie(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "ADC group regular end of sequence conversions interrupt"]
#[inline(always)]
pub fn set_eosie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "ADC group regular overrun interrupt"]
#[inline(always)]
pub const fn ovrie(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "ADC group regular overrun interrupt"]
#[inline(always)]
pub fn set_ovrie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "ADC analog watchdog 1 interrupt"]
#[inline(always)]
pub const fn awd1ie(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "ADC analog watchdog 1 interrupt"]
#[inline(always)]
pub fn set_awd1ie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "ADC analog watchdog 2 interrupt"]
#[inline(always)]
pub const fn awd2ie(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "ADC analog watchdog 2 interrupt"]
#[inline(always)]
pub fn set_awd2ie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "ADC analog watchdog 3 interrupt"]
#[inline(always)]
pub const fn awd3ie(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "ADC analog watchdog 3 interrupt"]
#[inline(always)]
pub fn set_awd3ie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "End of calibration interrupt enable"]
#[inline(always)]
pub const fn eocalie(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "End of calibration interrupt enable"]
#[inline(always)]
pub fn set_eocalie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "Channel Configuration Ready Interrupt enable"]
#[inline(always)]
pub const fn ccrdyie(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "Channel Configuration Ready Interrupt enable"]
#[inline(always)]
pub fn set_ccrdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
}
impl Default for Ier {
#[inline(always)]
fn default() -> Ier {
Ier(0)
}
}
impl core::fmt::Debug for Ier {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ier")
.field("adrdyie", &self.adrdyie())
.field("eosmpie", &self.eosmpie())
.field("eocie", &self.eocie())
.field("eosie", &self.eosie())
.field("ovrie", &self.ovrie())
.field("awd1ie", &self.awd1ie())
.field("awd2ie", &self.awd2ie())
.field("awd3ie", &self.awd3ie())
.field("eocalie", &self.eocalie())
.field("ccrdyie", &self.ccrdyie())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ier {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ier {{ adrdyie: {=bool:?}, eosmpie: {=bool:?}, eocie: {=bool:?}, eosie: {=bool:?}, ovrie: {=bool:?}, awd1ie: {=bool:?}, awd2ie: {=bool:?}, awd3ie: {=bool:?}, eocalie: {=bool:?}, ccrdyie: {=bool:?} }}" , self . adrdyie () , self . eosmpie () , self . eocie () , self . eosie () , self . ovrie () , self . awd1ie () , self . awd2ie () , self . awd3ie () , self . eocalie () , self . ccrdyie ())
}
}
#[doc = "ADC interrupt and status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Isr(pub u32);
impl Isr {
#[doc = "ADC ready flag"]
#[inline(always)]
pub const fn adrdy(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "ADC ready flag"]
#[inline(always)]
pub fn set_adrdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "ADC group regular end of sampling flag"]
#[inline(always)]
pub const fn eosmp(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "ADC group regular end of sampling flag"]
#[inline(always)]
pub fn set_eosmp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "ADC group regular end of unitary conversion flag"]
#[inline(always)]
pub const fn eoc(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "ADC group regular end of unitary conversion flag"]
#[inline(always)]
pub fn set_eoc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "ADC group regular end of sequence conversions flag"]
#[inline(always)]
pub const fn eos(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "ADC group regular end of sequence conversions flag"]
#[inline(always)]
pub fn set_eos(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "ADC group regular overrun flag"]
#[inline(always)]
pub const fn ovr(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "ADC group regular overrun flag"]
#[inline(always)]
pub fn set_ovr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "ADC analog watchdog 1 flag"]
#[inline(always)]
pub const fn awd1(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "ADC analog watchdog 1 flag"]
#[inline(always)]
pub fn set_awd1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "ADC analog watchdog 2 flag"]
#[inline(always)]
pub const fn awd2(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "ADC analog watchdog 2 flag"]
#[inline(always)]
pub fn set_awd2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "ADC analog watchdog 3 flag"]
#[inline(always)]
pub const fn awd3(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "ADC analog watchdog 3 flag"]
#[inline(always)]
pub fn set_awd3(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "End Of Calibration flag"]
#[inline(always)]
pub const fn eocal(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "End Of Calibration flag"]
#[inline(always)]
pub fn set_eocal(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "Channel Configuration Ready flag"]
#[inline(always)]
pub const fn ccrdy(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "Channel Configuration Ready flag"]
#[inline(always)]
pub fn set_ccrdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
}
impl Default for Isr {
#[inline(always)]
fn default() -> Isr {
Isr(0)
}
}
impl core::fmt::Debug for Isr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Isr")
.field("adrdy", &self.adrdy())
.field("eosmp", &self.eosmp())
.field("eoc", &self.eoc())
.field("eos", &self.eos())
.field("ovr", &self.ovr())
.field("awd1", &self.awd1())
.field("awd2", &self.awd2())
.field("awd3", &self.awd3())
.field("eocal", &self.eocal())
.field("ccrdy", &self.ccrdy())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Isr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Isr {{ adrdy: {=bool:?}, eosmp: {=bool:?}, eoc: {=bool:?}, eos: {=bool:?}, ovr: {=bool:?}, awd1: {=bool:?}, awd2: {=bool:?}, awd3: {=bool:?}, eocal: {=bool:?}, ccrdy: {=bool:?} }}" , self . adrdy () , self . eosmp () , self . eoc () , self . eos () , self . ovr () , self . awd1 () , self . awd2 () , self . awd3 () , self . eocal () , self . ccrdy ())
}
}
#[doc = "ADC sampling time register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Smpr(pub u32);
impl Smpr {
#[doc = "Sampling time selection"]
#[inline(always)]
pub const fn smp1(&self) -> super::vals::SampleTime {
let val = (self.0 >> 0usize) & 0x07;
super::vals::SampleTime::from_bits(val as u8)
}
#[doc = "Sampling time selection"]
#[inline(always)]
pub fn set_smp1(&mut self, val: super::vals::SampleTime) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
}
#[doc = "Sampling time selection"]
#[inline(always)]
pub const fn smp2(&self) -> super::vals::SampleTime {
let val = (self.0 >> 4usize) & 0x07;
super::vals::SampleTime::from_bits(val as u8)
}
#[doc = "Sampling time selection"]
#[inline(always)]
pub fn set_smp2(&mut self, val: super::vals::SampleTime) {
self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
}
#[doc = "Channel sampling time selection"]
#[inline(always)]
pub const fn smpsel(&self, n: usize) -> bool {
assert!(n < 19usize);
let offs = 8usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Channel sampling time selection"]
#[inline(always)]
pub fn set_smpsel(&mut self, n: usize, val: bool) {
assert!(n < 19usize);
let offs = 8usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Smpr {
#[inline(always)]
fn default() -> Smpr {
Smpr(0)
}
}
impl core::fmt::Debug for Smpr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Smpr")
.field("smp1", &self.smp1())
.field("smp2", &self.smp2())
.field("smpsel[0]", &self.smpsel(0usize))
.field("smpsel[1]", &self.smpsel(1usize))
.field("smpsel[2]", &self.smpsel(2usize))
.field("smpsel[3]", &self.smpsel(3usize))
.field("smpsel[4]", &self.smpsel(4usize))
.field("smpsel[5]", &self.smpsel(5usize))
.field("smpsel[6]", &self.smpsel(6usize))
.field("smpsel[7]", &self.smpsel(7usize))
.field("smpsel[8]", &self.smpsel(8usize))
.field("smpsel[9]", &self.smpsel(9usize))
.field("smpsel[10]", &self.smpsel(10usize))
.field("smpsel[11]", &self.smpsel(11usize))
.field("smpsel[12]", &self.smpsel(12usize))
.field("smpsel[13]", &self.smpsel(13usize))
.field("smpsel[14]", &self.smpsel(14usize))
.field("smpsel[15]", &self.smpsel(15usize))
.field("smpsel[16]", &self.smpsel(16usize))
.field("smpsel[17]", &self.smpsel(17usize))
.field("smpsel[18]", &self.smpsel(18usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Smpr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Smpr {{ smp1: {:?}, smp2: {:?}, smpsel[0]: {=bool:?}, smpsel[1]: {=bool:?}, smpsel[2]: {=bool:?}, smpsel[3]: {=bool:?}, smpsel[4]: {=bool:?}, smpsel[5]: {=bool:?}, smpsel[6]: {=bool:?}, smpsel[7]: {=bool:?}, smpsel[8]: {=bool:?}, smpsel[9]: {=bool:?}, smpsel[10]: {=bool:?}, smpsel[11]: {=bool:?}, smpsel[12]: {=bool:?}, smpsel[13]: {=bool:?}, smpsel[14]: {=bool:?}, smpsel[15]: {=bool:?}, smpsel[16]: {=bool:?}, smpsel[17]: {=bool:?}, smpsel[18]: {=bool:?} }}" , self . smp1 () , self . smp2 () , self . smpsel (0usize) , self . smpsel (1usize) , self . smpsel (2usize) , self . smpsel (3usize) , self . smpsel (4usize) , self . smpsel (5usize) , self . smpsel (6usize) , self . smpsel (7usize) , self . smpsel (8usize) , self . smpsel (9usize) , self . smpsel (10usize) , self . smpsel (11usize) , self . smpsel (12usize) , self . smpsel (13usize) , self . smpsel (14usize) , self . smpsel (15usize) , self . smpsel (16usize) , self . smpsel (17usize) , self . smpsel (18usize))
}
}
}
pub mod vals {
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Dmacfg {
#[doc = "DMA One Shot mode selected"]
ONE_SHOT = 0x0,
#[doc = "DMA Circular mode selected"]
CIRCULAR = 0x01,
}
impl Dmacfg {
#[inline(always)]
pub const fn from_bits(val: u8) -> Dmacfg {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Dmacfg {
#[inline(always)]
fn from(val: u8) -> Dmacfg {
Dmacfg::from_bits(val)
}
}
impl From<Dmacfg> for u8 {
#[inline(always)]
fn from(val: Dmacfg) -> u8 {
Dmacfg::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Res {
#[doc = "12-bit resolution"]
BITS12 = 0x0,
#[doc = "10-bit resolution"]
BITS10 = 0x01,
#[doc = "8-bit resolution"]
BITS8 = 0x02,
#[doc = "6-bit resolution"]
BITS6 = 0x03,
}
impl Res {
#[inline(always)]
pub const fn from_bits(val: u8) -> Res {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Res {
#[inline(always)]
fn from(val: u8) -> Res {
Res::from_bits(val)
}
}
impl From<Res> for u8 {
#[inline(always)]
fn from(val: Res) -> u8 {
Res::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum SampleTime {
#[doc = "1.5 ADC cycles"]
CYCLES1_5 = 0x0,
#[doc = "3.5 ADC cycles"]
CYCLES3_5 = 0x01,
#[doc = "7.5 ADC cycles"]
CYCLES7_5 = 0x02,
#[doc = "12.5 ADC cycles"]
CYCLES12_5 = 0x03,
#[doc = "19.5 ADC cycles"]
CYCLES19_5 = 0x04,
#[doc = "39.5 ADC cycles"]
CYCLES39_5 = 0x05,
#[doc = "79.5 ADC cycles"]
CYCLES79_5 = 0x06,
#[doc = "160.5 ADC cycles"]
CYCLES160_5 = 0x07,
}
impl SampleTime {
#[inline(always)]
pub const fn from_bits(val: u8) -> SampleTime {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for SampleTime {
#[inline(always)]
fn from(val: u8) -> SampleTime {
SampleTime::from_bits(val)
}
}
impl From<SampleTime> for u8 {
#[inline(always)]
fn from(val: SampleTime) -> u8 {
SampleTime::to_bits(val)
}
}
}