#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
#[doc = "Reset and clock controller"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Rcc {
ptr: *mut u8,
}
unsafe impl Send for Rcc {}
unsafe impl Sync for Rcc {}
impl Rcc {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "RCC clock control register"]
#[inline(always)]
pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "RCC HSI calibration register"]
#[inline(always)]
pub const fn hsicfgr(self) -> crate::common::Reg<regs::Hsicfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
}
#[doc = "RCC clock recovery RC register"]
#[inline(always)]
pub const fn crrcr(self) -> crate::common::Reg<regs::Crrcr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
}
#[doc = "RCC CSI calibration register"]
#[inline(always)]
pub const fn csicfgr(self) -> crate::common::Reg<regs::Csicfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
}
#[doc = "RCC clock configuration register"]
#[inline(always)]
pub const fn cfgr(self) -> crate::common::Reg<regs::Cfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
}
#[doc = "RCC CPU domain clock configuration register 2"]
#[inline(always)]
pub const fn cfgr2(self) -> crate::common::Reg<regs::Cfgr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
}
#[doc = "RCC PLL clock source selection register"]
#[inline(always)]
pub const fn pllcfgr(self, n: usize) -> crate::common::Reg<regs::Pllcfgr, crate::common::RW> {
assert!(n < 3usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize + n * 4usize) as _) }
}
#[doc = "RCC PLL1 dividers register"]
#[inline(always)]
pub const fn plldivr(self, n: usize) -> crate::common::Reg<regs::Plldivr, crate::common::RW> {
assert!(n < 3usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 8usize) as _) }
}
#[doc = "RCC PLL1 fractional divider register"]
#[inline(always)]
pub const fn pllfracr(self, n: usize) -> crate::common::Reg<regs::Pllfracr, crate::common::RW> {
assert!(n < 3usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize + n * 8usize) as _) }
}
#[doc = "RCC clock source interrupt enable register"]
#[inline(always)]
pub const fn cier(self) -> crate::common::Reg<regs::Cier, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
}
#[doc = "RCC clock source interrupt flag register"]
#[inline(always)]
pub const fn cifr(self) -> crate::common::Reg<regs::Cifr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
}
#[doc = "RCC clock source interrupt clear register"]
#[inline(always)]
pub const fn cicr(self) -> crate::common::Reg<regs::Cicr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
}
#[doc = "RCC AHB1 reset register"]
#[inline(always)]
pub const fn ahb1rstr(self) -> crate::common::Reg<regs::Ahb1rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
}
#[doc = "RCC AHB2 peripheral reset register"]
#[inline(always)]
pub const fn ahb2rstr(self) -> crate::common::Reg<regs::Ahb2rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) }
}
#[doc = "RCC AHB4 peripheral reset register"]
#[inline(always)]
pub const fn ahb4rstr(self) -> crate::common::Reg<regs::Ahb4rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) }
}
#[doc = "RCC APB1 peripheral low reset register"]
#[inline(always)]
pub const fn apb1lrstr(self) -> crate::common::Reg<regs::Apb1lrstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) }
}
#[doc = "RCC APB1 peripheral high reset register"]
#[inline(always)]
pub const fn apb1hrstr(self) -> crate::common::Reg<regs::Apb1hrstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) }
}
#[doc = "RCC APB2 peripheral reset register"]
#[inline(always)]
pub const fn apb2rstr(self) -> crate::common::Reg<regs::Apb2rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) }
}
#[doc = "RCC APB3 peripheral reset register"]
#[inline(always)]
pub const fn apb3rstr(self) -> crate::common::Reg<regs::Apb3rstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
}
#[doc = "RCC AHB1 peripherals clock register"]
#[inline(always)]
pub const fn ahb1enr(self) -> crate::common::Reg<regs::Ahb1enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) }
}
#[doc = "RCC AHB2 peripheral clock register"]
#[inline(always)]
pub const fn ahb2enr(self) -> crate::common::Reg<regs::Ahb2enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) }
}
#[doc = "RCC AHB4 peripheral clock register"]
#[inline(always)]
pub const fn ahb4enr(self) -> crate::common::Reg<regs::Ahb4enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) }
}
#[doc = "RCC APB1 peripheral clock register"]
#[inline(always)]
pub const fn apb1lenr(self) -> crate::common::Reg<regs::Apb1lenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x9cusize) as _) }
}
#[doc = "RCC APB1 peripheral clock register"]
#[inline(always)]
pub const fn apb1henr(self) -> crate::common::Reg<regs::Apb1henr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) }
}
#[doc = "RCC APB2 peripheral clock register"]
#[inline(always)]
pub const fn apb2enr(self) -> crate::common::Reg<regs::Apb2enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) }
}
#[doc = "RCC APB3 peripheral clock register"]
#[inline(always)]
pub const fn apb3enr(self) -> crate::common::Reg<regs::Apb3enr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) }
}
#[doc = "RCC AHB1 sleep clock register"]
#[inline(always)]
pub const fn ahb1lpenr(self) -> crate::common::Reg<regs::Ahb1lpenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) }
}
#[doc = "RCC AHB2 sleep clock register"]
#[inline(always)]
pub const fn ahb2lpenr(self) -> crate::common::Reg<regs::Ahb2lpenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb4usize) as _) }
}
#[doc = "RCC AHB4 sleep clock register"]
#[inline(always)]
pub const fn ahb4lpenr(self) -> crate::common::Reg<regs::Ahb4lpenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xbcusize) as _) }
}
#[doc = "RCC APB1 sleep clock register"]
#[inline(always)]
pub const fn apb1llpenr(self) -> crate::common::Reg<regs::Apb1llpenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) }
}
#[doc = "RCC APB1 sleep clock register"]
#[inline(always)]
pub const fn apb1hlpenr(self) -> crate::common::Reg<regs::Apb1hlpenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc8usize) as _) }
}
#[doc = "RCC APB2 sleep clock register"]
#[inline(always)]
pub const fn apb2lpenr(self) -> crate::common::Reg<regs::Apb2lpenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xccusize) as _) }
}
#[doc = "RCC APB3 sleep clock register"]
#[inline(always)]
pub const fn apb3lpenr(self) -> crate::common::Reg<regs::Apb3lpenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd0usize) as _) }
}
#[doc = "RCC kernel clock configuration register"]
#[inline(always)]
pub const fn ccipr1(self) -> crate::common::Reg<regs::Ccipr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd8usize) as _) }
}
#[doc = "RCC kernel clock configuration register"]
#[inline(always)]
pub const fn ccipr2(self) -> crate::common::Reg<regs::Ccipr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xdcusize) as _) }
}
#[doc = "RCC kernel clock configuration register"]
#[inline(always)]
pub const fn ccipr3(self) -> crate::common::Reg<regs::Ccipr3, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe0usize) as _) }
}
#[doc = "RCC kernel clock configuration register"]
#[inline(always)]
pub const fn ccipr4(self) -> crate::common::Reg<regs::Ccipr4, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe4usize) as _) }
}
#[doc = "RCC kernel clock configuration register"]
#[inline(always)]
pub const fn ccipr5(self) -> crate::common::Reg<regs::Ccipr5, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe8usize) as _) }
}
#[doc = "RCC Backup domain control register"]
#[inline(always)]
pub const fn bdcr(self) -> crate::common::Reg<regs::Bdcr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf0usize) as _) }
}
#[doc = "RCC reset status register"]
#[inline(always)]
pub const fn rsr(self) -> crate::common::Reg<regs::Rsr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf4usize) as _) }
}
#[doc = "RCC secure configuration register"]
#[inline(always)]
pub const fn seccfgr(self) -> crate::common::Reg<regs::Seccfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) }
}
#[doc = "RCC privilege configuration register"]
#[inline(always)]
pub const fn privcfgr(self) -> crate::common::Reg<regs::Privcfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0114usize) as _) }
}
}
pub mod regs {
#[doc = "RCC AHB1 peripherals clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb1enr(pub u32);
impl Ahb1enr {
#[doc = "GPDMA1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn gpdma1en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "GPDMA1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_gpdma1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "GPDMA2 clock enable Set and reset by software."]
#[inline(always)]
pub const fn gpdma2en(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "GPDMA2 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_gpdma2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Flash interface clock enable Set and reset by software."]
#[inline(always)]
pub const fn flitfen(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Flash interface clock enable Set and reset by software."]
#[inline(always)]
pub fn set_flitfen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "CRC clock enable Set and reset by software."]
#[inline(always)]
pub const fn crcen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC clock enable Set and reset by software."]
#[inline(always)]
pub fn set_crcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "CORDIC clock enable Set and reset by software."]
#[inline(always)]
pub const fn cordicen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "CORDIC clock enable Set and reset by software."]
#[inline(always)]
pub fn set_cordicen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "FMAC clock enable Set and reset by software."]
#[inline(always)]
pub const fn fmacen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "FMAC clock enable Set and reset by software."]
#[inline(always)]
pub fn set_fmacen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "RAMCFG clock enable Set and reset by software."]
#[inline(always)]
pub const fn ramcfgen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "RAMCFG clock enable Set and reset by software."]
#[inline(always)]
pub fn set_ramcfgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "ETH clock enable Set and reset by software"]
#[inline(always)]
pub const fn ethen(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "ETH clock enable Set and reset by software"]
#[inline(always)]
pub fn set_ethen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "ETHTX clock enable Set and reset by software"]
#[inline(always)]
pub const fn ethtxen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "ETHTX clock enable Set and reset by software"]
#[inline(always)]
pub fn set_ethtxen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "ETHRX clock enable Set and reset by software"]
#[inline(always)]
pub const fn ethrxen(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "ETHRX clock enable Set and reset by software"]
#[inline(always)]
pub fn set_ethrxen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "TZSC1 clock enable Set and reset by software"]
#[inline(always)]
pub const fn tzsc1en(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "TZSC1 clock enable Set and reset by software"]
#[inline(always)]
pub fn set_tzsc1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "BKPRAM clock enable Set and reset by software"]
#[inline(always)]
pub const fn bkpramen(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "BKPRAM clock enable Set and reset by software"]
#[inline(always)]
pub fn set_bkpramen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "DCACHE clock enable Set and reset by software"]
#[inline(always)]
pub const fn dcacheen(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "DCACHE clock enable Set and reset by software"]
#[inline(always)]
pub fn set_dcacheen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "SRAM1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn sram1en(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "SRAM1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_sram1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Ahb1enr {
#[inline(always)]
fn default() -> Ahb1enr {
Ahb1enr(0)
}
}
impl core::fmt::Debug for Ahb1enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb1enr")
.field("gpdma1en", &self.gpdma1en())
.field("gpdma2en", &self.gpdma2en())
.field("flitfen", &self.flitfen())
.field("crcen", &self.crcen())
.field("cordicen", &self.cordicen())
.field("fmacen", &self.fmacen())
.field("ramcfgen", &self.ramcfgen())
.field("ethen", &self.ethen())
.field("ethtxen", &self.ethtxen())
.field("ethrxen", &self.ethrxen())
.field("tzsc1en", &self.tzsc1en())
.field("bkpramen", &self.bkpramen())
.field("dcacheen", &self.dcacheen())
.field("sram1en", &self.sram1en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb1enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb1enr {{ gpdma1en: {=bool:?}, gpdma2en: {=bool:?}, flitfen: {=bool:?}, crcen: {=bool:?}, cordicen: {=bool:?}, fmacen: {=bool:?}, ramcfgen: {=bool:?}, ethen: {=bool:?}, ethtxen: {=bool:?}, ethrxen: {=bool:?}, tzsc1en: {=bool:?}, bkpramen: {=bool:?}, dcacheen: {=bool:?}, sram1en: {=bool:?} }}" , self . gpdma1en () , self . gpdma2en () , self . flitfen () , self . crcen () , self . cordicen () , self . fmacen () , self . ramcfgen () , self . ethen () , self . ethtxen () , self . ethrxen () , self . tzsc1en () , self . bkpramen () , self . dcacheen () , self . sram1en ())
}
}
#[doc = "RCC AHB1 sleep clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb1lpenr(pub u32);
impl Ahb1lpenr {
#[doc = "GPDMA1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn gpdma1lpen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "GPDMA1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_gpdma1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "GPDMA2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn gpdma2lpen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "GPDMA2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_gpdma2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Flash interface (FLITF) clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn flitflpen(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Flash interface (FLITF) clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_flitflpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "CRC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn crclpen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_crclpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "CORDIC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn cordiclpen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "CORDIC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_cordiclpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "FMAC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn fmaclpen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "FMAC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_fmaclpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "RAMCFG clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn ramcfglpen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "RAMCFG clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_ramcfglpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "ETH clock enable during Sleep mode Set and reset by software"]
#[inline(always)]
pub const fn ethlpen(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "ETH clock enable during Sleep mode Set and reset by software"]
#[inline(always)]
pub fn set_ethlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "ETHTX clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub const fn ethtxlpen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "ETHTX clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub fn set_ethtxlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "ETHRX clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub const fn ethrxlpen(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "ETHRX clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub fn set_ethrxlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "TZSC1 clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub const fn tzsc1lpen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "TZSC1 clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub fn set_tzsc1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "BKPRAM clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub const fn bkpramlpen(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "BKPRAM clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub fn set_bkpramlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "ICACHE clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub const fn icachelpen(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "ICACHE clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub fn set_icachelpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "DCACHE clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub const fn dcachelpen(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "DCACHE clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub fn set_dcachelpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "SRAM1 clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub const fn sram1lpen(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "SRAM1 clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub fn set_sram1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Ahb1lpenr {
#[inline(always)]
fn default() -> Ahb1lpenr {
Ahb1lpenr(0)
}
}
impl core::fmt::Debug for Ahb1lpenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb1lpenr")
.field("gpdma1lpen", &self.gpdma1lpen())
.field("gpdma2lpen", &self.gpdma2lpen())
.field("flitflpen", &self.flitflpen())
.field("crclpen", &self.crclpen())
.field("cordiclpen", &self.cordiclpen())
.field("fmaclpen", &self.fmaclpen())
.field("ramcfglpen", &self.ramcfglpen())
.field("ethlpen", &self.ethlpen())
.field("ethtxlpen", &self.ethtxlpen())
.field("ethrxlpen", &self.ethrxlpen())
.field("tzsc1lpen", &self.tzsc1lpen())
.field("bkpramlpen", &self.bkpramlpen())
.field("icachelpen", &self.icachelpen())
.field("dcachelpen", &self.dcachelpen())
.field("sram1lpen", &self.sram1lpen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb1lpenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb1lpenr {{ gpdma1lpen: {=bool:?}, gpdma2lpen: {=bool:?}, flitflpen: {=bool:?}, crclpen: {=bool:?}, cordiclpen: {=bool:?}, fmaclpen: {=bool:?}, ramcfglpen: {=bool:?}, ethlpen: {=bool:?}, ethtxlpen: {=bool:?}, ethrxlpen: {=bool:?}, tzsc1lpen: {=bool:?}, bkpramlpen: {=bool:?}, icachelpen: {=bool:?}, dcachelpen: {=bool:?}, sram1lpen: {=bool:?} }}" , self . gpdma1lpen () , self . gpdma2lpen () , self . flitflpen () , self . crclpen () , self . cordiclpen () , self . fmaclpen () , self . ramcfglpen () , self . ethlpen () , self . ethtxlpen () , self . ethrxlpen () , self . tzsc1lpen () , self . bkpramlpen () , self . icachelpen () , self . dcachelpen () , self . sram1lpen ())
}
}
#[doc = "RCC AHB1 reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb1rstr(pub u32);
impl Ahb1rstr {
#[doc = "GPDMA1 block reset Set and reset by software."]
#[inline(always)]
pub const fn gpdma1rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "GPDMA1 block reset Set and reset by software."]
#[inline(always)]
pub fn set_gpdma1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "GPDMA2 block reset Set and reset by software."]
#[inline(always)]
pub const fn gpdma2rst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "GPDMA2 block reset Set and reset by software."]
#[inline(always)]
pub fn set_gpdma2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "CRC block reset Set and reset by software."]
#[inline(always)]
pub const fn crcrst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC block reset Set and reset by software."]
#[inline(always)]
pub fn set_crcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "CORDIC block reset Set and reset by software."]
#[inline(always)]
pub const fn cordicrst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "CORDIC block reset Set and reset by software."]
#[inline(always)]
pub fn set_cordicrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "FMAC block reset Set and reset by software."]
#[inline(always)]
pub const fn fmacrst(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "FMAC block reset Set and reset by software."]
#[inline(always)]
pub fn set_fmacrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "RAMCFG block reset Set and reset by software."]
#[inline(always)]
pub const fn ramcfgrst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "RAMCFG block reset Set and reset by software."]
#[inline(always)]
pub fn set_ramcfgrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "ETH1 block reset Set and reset by software"]
#[inline(always)]
pub const fn ethrst(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "ETH1 block reset Set and reset by software"]
#[inline(always)]
pub fn set_ethrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "TZSC1 reset Set and reset by software"]
#[inline(always)]
pub const fn tzsc1rst(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "TZSC1 reset Set and reset by software"]
#[inline(always)]
pub fn set_tzsc1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
}
impl Default for Ahb1rstr {
#[inline(always)]
fn default() -> Ahb1rstr {
Ahb1rstr(0)
}
}
impl core::fmt::Debug for Ahb1rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb1rstr")
.field("gpdma1rst", &self.gpdma1rst())
.field("gpdma2rst", &self.gpdma2rst())
.field("crcrst", &self.crcrst())
.field("cordicrst", &self.cordicrst())
.field("fmacrst", &self.fmacrst())
.field("ramcfgrst", &self.ramcfgrst())
.field("ethrst", &self.ethrst())
.field("tzsc1rst", &self.tzsc1rst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb1rstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb1rstr {{ gpdma1rst: {=bool:?}, gpdma2rst: {=bool:?}, crcrst: {=bool:?}, cordicrst: {=bool:?}, fmacrst: {=bool:?}, ramcfgrst: {=bool:?}, ethrst: {=bool:?}, tzsc1rst: {=bool:?} }}" , self . gpdma1rst () , self . gpdma2rst () , self . crcrst () , self . cordicrst () , self . fmacrst () , self . ramcfgrst () , self . ethrst () , self . tzsc1rst ())
}
}
#[doc = "RCC AHB2 peripheral clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb2enr(pub u32);
impl Ahb2enr {
#[doc = "GPIOA clock enable Set and reset by software."]
#[inline(always)]
pub const fn gpioaen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "GPIOA clock enable Set and reset by software."]
#[inline(always)]
pub fn set_gpioaen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "GPIOB clock enable Set and reset by software."]
#[inline(always)]
pub const fn gpioben(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "GPIOB clock enable Set and reset by software."]
#[inline(always)]
pub fn set_gpioben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "GPIOC clock enable Set and reset by software."]
#[inline(always)]
pub const fn gpiocen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "GPIOC clock enable Set and reset by software."]
#[inline(always)]
pub fn set_gpiocen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "GPIOD clock enable Set and reset by software."]
#[inline(always)]
pub const fn gpioden(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "GPIOD clock enable Set and reset by software."]
#[inline(always)]
pub fn set_gpioden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "GPIOE clock enable Set and reset by software."]
#[inline(always)]
pub const fn gpioeen(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "GPIOE clock enable Set and reset by software."]
#[inline(always)]
pub fn set_gpioeen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "GPIOF clock enable Set and reset by software."]
#[inline(always)]
pub const fn gpiofen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "GPIOF clock enable Set and reset by software."]
#[inline(always)]
pub fn set_gpiofen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "GPIOG clock enable Set and reset by software."]
#[inline(always)]
pub const fn gpiogen(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "GPIOG clock enable Set and reset by software."]
#[inline(always)]
pub fn set_gpiogen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "GPIOH clock enable Set and reset by software."]
#[inline(always)]
pub const fn gpiohen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "GPIOH clock enable Set and reset by software."]
#[inline(always)]
pub fn set_gpiohen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "GPIOI clock enable Set and reset by software."]
#[inline(always)]
pub const fn gpioien(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "GPIOI clock enable Set and reset by software."]
#[inline(always)]
pub fn set_gpioien(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "ADC1 and 2 peripherals clock enabled Set and reset by software."]
#[inline(always)]
pub const fn adc12en(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "ADC1 and 2 peripherals clock enabled Set and reset by software."]
#[inline(always)]
pub fn set_adc12en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "DAC clock enable Set and reset by software."]
#[inline(always)]
pub const fn dac1en(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "DAC clock enable Set and reset by software."]
#[inline(always)]
pub fn set_dac1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "digital camera interface clock enable (DCMI or PSSI depending which interface is active) Set and reset by software."]
#[inline(always)]
pub const fn dcmi_pssien(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "digital camera interface clock enable (DCMI or PSSI depending which interface is active) Set and reset by software."]
#[inline(always)]
pub fn set_dcmi_pssien(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "AES clock enable Set and reset by software."]
#[inline(always)]
pub const fn aesen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "AES clock enable Set and reset by software."]
#[inline(always)]
pub fn set_aesen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "HASH clock enable Set and reset by software."]
#[inline(always)]
pub const fn hashen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "HASH clock enable Set and reset by software."]
#[inline(always)]
pub fn set_hashen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "RNG clock enable Set and reset by software."]
#[inline(always)]
pub const fn rngen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "RNG clock enable Set and reset by software."]
#[inline(always)]
pub fn set_rngen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "PKA clock enable Set and reset by software."]
#[inline(always)]
pub const fn pkaen(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "PKA clock enable Set and reset by software."]
#[inline(always)]
pub fn set_pkaen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "SAES clock enable Set and reset by software."]
#[inline(always)]
pub const fn saesen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "SAES clock enable Set and reset by software."]
#[inline(always)]
pub fn set_saesen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "SRAM3 clock enable Set and reset by software."]
#[inline(always)]
pub const fn sram3en(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "SRAM3 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_sram3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "SRAM2 clock enable Set and reset by software."]
#[inline(always)]
pub const fn sram2en(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "SRAM2 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_sram2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Ahb2enr {
#[inline(always)]
fn default() -> Ahb2enr {
Ahb2enr(0)
}
}
impl core::fmt::Debug for Ahb2enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb2enr")
.field("gpioaen", &self.gpioaen())
.field("gpioben", &self.gpioben())
.field("gpiocen", &self.gpiocen())
.field("gpioden", &self.gpioden())
.field("gpioeen", &self.gpioeen())
.field("gpiofen", &self.gpiofen())
.field("gpiogen", &self.gpiogen())
.field("gpiohen", &self.gpiohen())
.field("gpioien", &self.gpioien())
.field("adc12en", &self.adc12en())
.field("dac1en", &self.dac1en())
.field("dcmi_pssien", &self.dcmi_pssien())
.field("aesen", &self.aesen())
.field("hashen", &self.hashen())
.field("rngen", &self.rngen())
.field("pkaen", &self.pkaen())
.field("saesen", &self.saesen())
.field("sram3en", &self.sram3en())
.field("sram2en", &self.sram2en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb2enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb2enr {{ gpioaen: {=bool:?}, gpioben: {=bool:?}, gpiocen: {=bool:?}, gpioden: {=bool:?}, gpioeen: {=bool:?}, gpiofen: {=bool:?}, gpiogen: {=bool:?}, gpiohen: {=bool:?}, gpioien: {=bool:?}, adc12en: {=bool:?}, dac1en: {=bool:?}, dcmi_pssien: {=bool:?}, aesen: {=bool:?}, hashen: {=bool:?}, rngen: {=bool:?}, pkaen: {=bool:?}, saesen: {=bool:?}, sram3en: {=bool:?}, sram2en: {=bool:?} }}" , self . gpioaen () , self . gpioben () , self . gpiocen () , self . gpioden () , self . gpioeen () , self . gpiofen () , self . gpiogen () , self . gpiohen () , self . gpioien () , self . adc12en () , self . dac1en () , self . dcmi_pssien () , self . aesen () , self . hashen () , self . rngen () , self . pkaen () , self . saesen () , self . sram3en () , self . sram2en ())
}
}
#[doc = "RCC AHB2 sleep clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb2lpenr(pub u32);
impl Ahb2lpenr {
#[doc = "GPIOA clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn gpioalpen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "GPIOA clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_gpioalpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "GPIOB clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn gpioblpen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "GPIOB clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_gpioblpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "GPIOC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn gpioclpen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "GPIOC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_gpioclpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "GPIOD clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn gpiodlpen(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "GPIOD clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_gpiodlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "GPIOE clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn gpioelpen(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "GPIOE clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_gpioelpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "GPIOF clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn gpioflpen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "GPIOF clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_gpioflpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "GPIOG clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn gpioglpen(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "GPIOG clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_gpioglpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "GPIOH clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn gpiohlpen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "GPIOH clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_gpiohlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "GPIOI clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn gpioilpen(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "GPIOI clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_gpioilpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "ADC1 and 2 peripherals clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn adc12lpen(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "ADC1 and 2 peripherals clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_adc12lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "DAC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn dac1lpen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "DAC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_dac1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "digital camera interface clock enable during sleep mode (DCMI or PSSI depending which interface is active) Set and reset by software."]
#[inline(always)]
pub const fn dcmi_pssilpen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "digital camera interface clock enable during sleep mode (DCMI or PSSI depending which interface is active) Set and reset by software."]
#[inline(always)]
pub fn set_dcmi_pssilpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "AES clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn aeslpen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "AES clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_aeslpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "HASH clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn hashlpen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "HASH clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_hashlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "RNG clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn rnglpen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "RNG clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_rnglpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "PKA clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn pkalpen(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "PKA clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_pkalpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "SAES clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn saeslpen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "SAES clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_saeslpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "SRAM2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn sram2lpen(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "SRAM2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_sram2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "SRAM3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn sram3lpen(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "SRAM3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_sram3lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Ahb2lpenr {
#[inline(always)]
fn default() -> Ahb2lpenr {
Ahb2lpenr(0)
}
}
impl core::fmt::Debug for Ahb2lpenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb2lpenr")
.field("gpioalpen", &self.gpioalpen())
.field("gpioblpen", &self.gpioblpen())
.field("gpioclpen", &self.gpioclpen())
.field("gpiodlpen", &self.gpiodlpen())
.field("gpioelpen", &self.gpioelpen())
.field("gpioflpen", &self.gpioflpen())
.field("gpioglpen", &self.gpioglpen())
.field("gpiohlpen", &self.gpiohlpen())
.field("gpioilpen", &self.gpioilpen())
.field("adc12lpen", &self.adc12lpen())
.field("dac1lpen", &self.dac1lpen())
.field("dcmi_pssilpen", &self.dcmi_pssilpen())
.field("aeslpen", &self.aeslpen())
.field("hashlpen", &self.hashlpen())
.field("rnglpen", &self.rnglpen())
.field("pkalpen", &self.pkalpen())
.field("saeslpen", &self.saeslpen())
.field("sram2lpen", &self.sram2lpen())
.field("sram3lpen", &self.sram3lpen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb2lpenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb2lpenr {{ gpioalpen: {=bool:?}, gpioblpen: {=bool:?}, gpioclpen: {=bool:?}, gpiodlpen: {=bool:?}, gpioelpen: {=bool:?}, gpioflpen: {=bool:?}, gpioglpen: {=bool:?}, gpiohlpen: {=bool:?}, gpioilpen: {=bool:?}, adc12lpen: {=bool:?}, dac1lpen: {=bool:?}, dcmi_pssilpen: {=bool:?}, aeslpen: {=bool:?}, hashlpen: {=bool:?}, rnglpen: {=bool:?}, pkalpen: {=bool:?}, saeslpen: {=bool:?}, sram2lpen: {=bool:?}, sram3lpen: {=bool:?} }}" , self . gpioalpen () , self . gpioblpen () , self . gpioclpen () , self . gpiodlpen () , self . gpioelpen () , self . gpioflpen () , self . gpioglpen () , self . gpiohlpen () , self . gpioilpen () , self . adc12lpen () , self . dac1lpen () , self . dcmi_pssilpen () , self . aeslpen () , self . hashlpen () , self . rnglpen () , self . pkalpen () , self . saeslpen () , self . sram2lpen () , self . sram3lpen ())
}
}
#[doc = "RCC AHB2 peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb2rstr(pub u32);
impl Ahb2rstr {
#[doc = "GPIOA block reset Set and reset by software."]
#[inline(always)]
pub const fn gpioarst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "GPIOA block reset Set and reset by software."]
#[inline(always)]
pub fn set_gpioarst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "GPIOB block reset Set and reset by software."]
#[inline(always)]
pub const fn gpiobrst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "GPIOB block reset Set and reset by software."]
#[inline(always)]
pub fn set_gpiobrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "GPIOC block reset Set and reset by software."]
#[inline(always)]
pub const fn gpiocrst(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "GPIOC block reset Set and reset by software."]
#[inline(always)]
pub fn set_gpiocrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "GPIOD block reset Set and reset by software."]
#[inline(always)]
pub const fn gpiodrst(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "GPIOD block reset Set and reset by software."]
#[inline(always)]
pub fn set_gpiodrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "GPIOE block reset Set and reset by software."]
#[inline(always)]
pub const fn gpioerst(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "GPIOE block reset Set and reset by software."]
#[inline(always)]
pub fn set_gpioerst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "GPIOF block reset Set and reset by software."]
#[inline(always)]
pub const fn gpiofrst(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "GPIOF block reset Set and reset by software."]
#[inline(always)]
pub fn set_gpiofrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "GPIOG block reset Set and reset by software."]
#[inline(always)]
pub const fn gpiogrst(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "GPIOG block reset Set and reset by software."]
#[inline(always)]
pub fn set_gpiogrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "GPIOH block reset Set and reset by software."]
#[inline(always)]
pub const fn gpiohrst(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "GPIOH block reset Set and reset by software."]
#[inline(always)]
pub fn set_gpiohrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "GPIOI block reset Set and reset by software."]
#[inline(always)]
pub const fn gpioirst(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "GPIOI block reset Set and reset by software."]
#[inline(always)]
pub fn set_gpioirst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "ADC1 and 2 blocks reset Set and reset by software."]
#[inline(always)]
pub const fn adc12rst(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "ADC1 and 2 blocks reset Set and reset by software."]
#[inline(always)]
pub fn set_adc12rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "DAC block reset Set and reset by software."]
#[inline(always)]
pub const fn dac1rst(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "DAC block reset Set and reset by software."]
#[inline(always)]
pub fn set_dac1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "digital camera interface block reset (DCMI or PSSI depending which interface is active) Set and reset by software."]
#[inline(always)]
pub const fn dcmi_pssirst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "digital camera interface block reset (DCMI or PSSI depending which interface is active) Set and reset by software."]
#[inline(always)]
pub fn set_dcmi_pssirst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "AES block reset Set and reset by software."]
#[inline(always)]
pub const fn aesrst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "AES block reset Set and reset by software."]
#[inline(always)]
pub fn set_aesrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "HASH block reset Set and reset by software."]
#[inline(always)]
pub const fn hashrst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "HASH block reset Set and reset by software."]
#[inline(always)]
pub fn set_hashrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "RNG block reset Set and reset by software."]
#[inline(always)]
pub const fn rngrst(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "RNG block reset Set and reset by software."]
#[inline(always)]
pub fn set_rngrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "PKA block reset Set and reset by software."]
#[inline(always)]
pub const fn pkarst(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "PKA block reset Set and reset by software."]
#[inline(always)]
pub fn set_pkarst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "SAES block reset Set and reset by software."]
#[inline(always)]
pub const fn saesrst(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "SAES block reset Set and reset by software."]
#[inline(always)]
pub fn set_saesrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Ahb2rstr {
#[inline(always)]
fn default() -> Ahb2rstr {
Ahb2rstr(0)
}
}
impl core::fmt::Debug for Ahb2rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb2rstr")
.field("gpioarst", &self.gpioarst())
.field("gpiobrst", &self.gpiobrst())
.field("gpiocrst", &self.gpiocrst())
.field("gpiodrst", &self.gpiodrst())
.field("gpioerst", &self.gpioerst())
.field("gpiofrst", &self.gpiofrst())
.field("gpiogrst", &self.gpiogrst())
.field("gpiohrst", &self.gpiohrst())
.field("gpioirst", &self.gpioirst())
.field("adc12rst", &self.adc12rst())
.field("dac1rst", &self.dac1rst())
.field("dcmi_pssirst", &self.dcmi_pssirst())
.field("aesrst", &self.aesrst())
.field("hashrst", &self.hashrst())
.field("rngrst", &self.rngrst())
.field("pkarst", &self.pkarst())
.field("saesrst", &self.saesrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb2rstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb2rstr {{ gpioarst: {=bool:?}, gpiobrst: {=bool:?}, gpiocrst: {=bool:?}, gpiodrst: {=bool:?}, gpioerst: {=bool:?}, gpiofrst: {=bool:?}, gpiogrst: {=bool:?}, gpiohrst: {=bool:?}, gpioirst: {=bool:?}, adc12rst: {=bool:?}, dac1rst: {=bool:?}, dcmi_pssirst: {=bool:?}, aesrst: {=bool:?}, hashrst: {=bool:?}, rngrst: {=bool:?}, pkarst: {=bool:?}, saesrst: {=bool:?} }}" , self . gpioarst () , self . gpiobrst () , self . gpiocrst () , self . gpiodrst () , self . gpioerst () , self . gpiofrst () , self . gpiogrst () , self . gpiohrst () , self . gpioirst () , self . adc12rst () , self . dac1rst () , self . dcmi_pssirst () , self . aesrst () , self . hashrst () , self . rngrst () , self . pkarst () , self . saesrst ())
}
}
#[doc = "RCC AHB4 peripheral clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb4enr(pub u32);
impl Ahb4enr {
#[doc = "OTFDEC1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn otfdec1en(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "OTFDEC1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_otfdec1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "SDMMC1 and SDMMC1 delay peripheral clock enable reset"]
#[inline(always)]
pub const fn sdmmc1en(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "SDMMC1 and SDMMC1 delay peripheral clock enable reset"]
#[inline(always)]
pub fn set_sdmmc1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SDMMC2 and SDMMC2 delay peripheral clock enabled Set and reset by software."]
#[inline(always)]
pub const fn sdmmc2en(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SDMMC2 and SDMMC2 delay peripheral clock enabled Set and reset by software."]
#[inline(always)]
pub fn set_sdmmc2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "FMC clock enable Set and reset by software."]
#[inline(always)]
pub const fn fmcen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "FMC clock enable Set and reset by software."]
#[inline(always)]
pub fn set_fmcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "OCTOSPI1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn octospi1en(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "OCTOSPI1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_octospi1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Ahb4enr {
#[inline(always)]
fn default() -> Ahb4enr {
Ahb4enr(0)
}
}
impl core::fmt::Debug for Ahb4enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb4enr")
.field("otfdec1en", &self.otfdec1en())
.field("sdmmc1en", &self.sdmmc1en())
.field("sdmmc2en", &self.sdmmc2en())
.field("fmcen", &self.fmcen())
.field("octospi1en", &self.octospi1en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb4enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb4enr {{ otfdec1en: {=bool:?}, sdmmc1en: {=bool:?}, sdmmc2en: {=bool:?}, fmcen: {=bool:?}, octospi1en: {=bool:?} }}" , self . otfdec1en () , self . sdmmc1en () , self . sdmmc2en () , self . fmcen () , self . octospi1en ())
}
}
#[doc = "RCC AHB4 sleep clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb4lpenr(pub u32);
impl Ahb4lpenr {
#[doc = "OTFDEC1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn otfdec1lpen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "OTFDEC1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_otfdec1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "SDMMC1 and SDMMC1 delay peripheral clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub const fn sdmmc1lpen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "SDMMC1 and SDMMC1 delay peripheral clock enable during sleep mode Set and reset by software"]
#[inline(always)]
pub fn set_sdmmc1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SDMMC2 and SDMMC2 delay peripheral clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn sdmmc2lpen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SDMMC2 and SDMMC2 delay peripheral clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_sdmmc2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "FMC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn fmclpen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "FMC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_fmclpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "OCTOSPI1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn octospi1lpen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "OCTOSPI1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_octospi1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Ahb4lpenr {
#[inline(always)]
fn default() -> Ahb4lpenr {
Ahb4lpenr(0)
}
}
impl core::fmt::Debug for Ahb4lpenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb4lpenr")
.field("otfdec1lpen", &self.otfdec1lpen())
.field("sdmmc1lpen", &self.sdmmc1lpen())
.field("sdmmc2lpen", &self.sdmmc2lpen())
.field("fmclpen", &self.fmclpen())
.field("octospi1lpen", &self.octospi1lpen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb4lpenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb4lpenr {{ otfdec1lpen: {=bool:?}, sdmmc1lpen: {=bool:?}, sdmmc2lpen: {=bool:?}, fmclpen: {=bool:?}, octospi1lpen: {=bool:?} }}" , self . otfdec1lpen () , self . sdmmc1lpen () , self . sdmmc2lpen () , self . fmclpen () , self . octospi1lpen ())
}
}
#[doc = "RCC AHB4 peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahb4rstr(pub u32);
impl Ahb4rstr {
#[doc = "OTFDEC1 block reset Set and reset by software."]
#[inline(always)]
pub const fn otfdec1rst(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "OTFDEC1 block reset Set and reset by software."]
#[inline(always)]
pub fn set_otfdec1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "SDMMC1 and SDMMC1 delay blocks reset Set and reset by software."]
#[inline(always)]
pub const fn sdmmc1rst(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "SDMMC1 and SDMMC1 delay blocks reset Set and reset by software."]
#[inline(always)]
pub fn set_sdmmc1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SDMMC2 and SDMMC2 delay blocks reset Set and reset by software."]
#[inline(always)]
pub const fn sdmmc2rst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SDMMC2 and SDMMC2 delay blocks reset Set and reset by software."]
#[inline(always)]
pub fn set_sdmmc2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "FMC block reset Set and reset by software."]
#[inline(always)]
pub const fn fmcrst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "FMC block reset Set and reset by software."]
#[inline(always)]
pub fn set_fmcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "OCTOSPI1 block reset Set and reset by software."]
#[inline(always)]
pub const fn octospi1rst(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "OCTOSPI1 block reset Set and reset by software."]
#[inline(always)]
pub fn set_octospi1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Ahb4rstr {
#[inline(always)]
fn default() -> Ahb4rstr {
Ahb4rstr(0)
}
}
impl core::fmt::Debug for Ahb4rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahb4rstr")
.field("otfdec1rst", &self.otfdec1rst())
.field("sdmmc1rst", &self.sdmmc1rst())
.field("sdmmc2rst", &self.sdmmc2rst())
.field("fmcrst", &self.fmcrst())
.field("octospi1rst", &self.octospi1rst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahb4rstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahb4rstr {{ otfdec1rst: {=bool:?}, sdmmc1rst: {=bool:?}, sdmmc2rst: {=bool:?}, fmcrst: {=bool:?}, octospi1rst: {=bool:?} }}" , self . otfdec1rst () , self . sdmmc1rst () , self . sdmmc2rst () , self . fmcrst () , self . octospi1rst ())
}
}
#[doc = "RCC APB1 peripheral clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1henr(pub u32);
impl Apb1henr {
#[doc = "UART9 clock enable Set and reset by software."]
#[inline(always)]
pub const fn uart9en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "UART9 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_uart9en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "UART12 clock enable Set and reset by software."]
#[inline(always)]
pub const fn uart12en(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "UART12 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_uart12en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "DTS clock enable Set and reset by software."]
#[inline(always)]
pub const fn dtsen(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "DTS clock enable Set and reset by software."]
#[inline(always)]
pub fn set_dtsen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "LPTIM2 clock enable Set and reset by software."]
#[inline(always)]
pub const fn lptim2en(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "LPTIM2 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_lptim2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "FDCAN1 and FDCAN2 peripheral clock enable Set and reset by software."]
#[inline(always)]
pub const fn fdcan12en(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "FDCAN1 and FDCAN2 peripheral clock enable Set and reset by software."]
#[inline(always)]
pub fn set_fdcan12en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "UCPD clock enable Set and reset by software."]
#[inline(always)]
pub const fn ucpden(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "UCPD clock enable Set and reset by software."]
#[inline(always)]
pub fn set_ucpden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
}
impl Default for Apb1henr {
#[inline(always)]
fn default() -> Apb1henr {
Apb1henr(0)
}
}
impl core::fmt::Debug for Apb1henr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1henr")
.field("uart9en", &self.uart9en())
.field("uart12en", &self.uart12en())
.field("dtsen", &self.dtsen())
.field("lptim2en", &self.lptim2en())
.field("fdcan12en", &self.fdcan12en())
.field("ucpden", &self.ucpden())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1henr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1henr {{ uart9en: {=bool:?}, uart12en: {=bool:?}, dtsen: {=bool:?}, lptim2en: {=bool:?}, fdcan12en: {=bool:?}, ucpden: {=bool:?} }}" , self . uart9en () , self . uart12en () , self . dtsen () , self . lptim2en () , self . fdcan12en () , self . ucpden ())
}
}
#[doc = "RCC APB1 sleep clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1hlpenr(pub u32);
impl Apb1hlpenr {
#[doc = "UART9 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn uart9lpen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "UART9 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_uart9lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "UART12 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn uart12lpen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "UART12 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_uart12lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "DTS clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn dtslpen(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "DTS clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_dtslpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "LPTIM2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn lptim2lpen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "LPTIM2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_lptim2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "FDCAN1 and FDCAN2 peripheral clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn fdcan12lpen(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "FDCAN1 and FDCAN2 peripheral clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_fdcan12lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "UCPD clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn ucpdlpen(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "UCPD clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_ucpdlpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
}
impl Default for Apb1hlpenr {
#[inline(always)]
fn default() -> Apb1hlpenr {
Apb1hlpenr(0)
}
}
impl core::fmt::Debug for Apb1hlpenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1hlpenr")
.field("uart9lpen", &self.uart9lpen())
.field("uart12lpen", &self.uart12lpen())
.field("dtslpen", &self.dtslpen())
.field("lptim2lpen", &self.lptim2lpen())
.field("fdcan12lpen", &self.fdcan12lpen())
.field("ucpdlpen", &self.ucpdlpen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1hlpenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1hlpenr {{ uart9lpen: {=bool:?}, uart12lpen: {=bool:?}, dtslpen: {=bool:?}, lptim2lpen: {=bool:?}, fdcan12lpen: {=bool:?}, ucpdlpen: {=bool:?} }}" , self . uart9lpen () , self . uart12lpen () , self . dtslpen () , self . lptim2lpen () , self . fdcan12lpen () , self . ucpdlpen ())
}
}
#[doc = "RCC APB1 peripheral high reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1hrstr(pub u32);
impl Apb1hrstr {
#[doc = "UART9 block reset Set and reset by software."]
#[inline(always)]
pub const fn uart9rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "UART9 block reset Set and reset by software."]
#[inline(always)]
pub fn set_uart9rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "UART12 block reset Set and reset by software."]
#[inline(always)]
pub const fn uart12rst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "UART12 block reset Set and reset by software."]
#[inline(always)]
pub fn set_uart12rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "DTS block reset Set and reset by software."]
#[inline(always)]
pub const fn dtsrst(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "DTS block reset Set and reset by software."]
#[inline(always)]
pub fn set_dtsrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "LPTIM2 block reset Set and reset by software."]
#[inline(always)]
pub const fn lptim2rst(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "LPTIM2 block reset Set and reset by software."]
#[inline(always)]
pub fn set_lptim2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "FDCAN1 and FDCAN2 blocks reset Set and reset by software."]
#[inline(always)]
pub const fn fdcan12rst(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "FDCAN1 and FDCAN2 blocks reset Set and reset by software."]
#[inline(always)]
pub fn set_fdcan12rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "UCPD block reset Set and reset by software."]
#[inline(always)]
pub const fn ucpdrst(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "UCPD block reset Set and reset by software."]
#[inline(always)]
pub fn set_ucpdrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
}
impl Default for Apb1hrstr {
#[inline(always)]
fn default() -> Apb1hrstr {
Apb1hrstr(0)
}
}
impl core::fmt::Debug for Apb1hrstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1hrstr")
.field("uart9rst", &self.uart9rst())
.field("uart12rst", &self.uart12rst())
.field("dtsrst", &self.dtsrst())
.field("lptim2rst", &self.lptim2rst())
.field("fdcan12rst", &self.fdcan12rst())
.field("ucpdrst", &self.ucpdrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1hrstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1hrstr {{ uart9rst: {=bool:?}, uart12rst: {=bool:?}, dtsrst: {=bool:?}, lptim2rst: {=bool:?}, fdcan12rst: {=bool:?}, ucpdrst: {=bool:?} }}" , self . uart9rst () , self . uart12rst () , self . dtsrst () , self . lptim2rst () , self . fdcan12rst () , self . ucpdrst ())
}
}
#[doc = "RCC APB1 peripheral clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1lenr(pub u32);
impl Apb1lenr {
#[doc = "TIM2 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim2en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM3 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim3en(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "TIM3 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "TIM4 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim4en(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "TIM4 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim4en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "TIM5 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim5en(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "TIM5 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim5en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "TIM6 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim6en(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "TIM6 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim6en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "TIM7 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim7en(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "TIM7 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim7en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "TIM12 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim12en(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "TIM12 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim12en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "TIM13 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim13en(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "TIM13 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim13en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "TIM14 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim14en(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "TIM14 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim14en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "WWDG clock enable Set and reset by software."]
#[inline(always)]
pub const fn wwdgen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "WWDG clock enable Set and reset by software."]
#[inline(always)]
pub fn set_wwdgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI2 clock enable Set and reset by software."]
#[inline(always)]
pub const fn spi2en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_spi2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "SPI3 clock enable Set and reset by software."]
#[inline(always)]
pub const fn spi3en(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "SPI3 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_spi3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "USART2 clock enable Set and reset by software."]
#[inline(always)]
pub const fn usart2en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_usart2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART3 clock enable Set and reset by software."]
#[inline(always)]
pub const fn usart3en(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART3 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_usart3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "UART4 clock enable Set and reset by software."]
#[inline(always)]
pub const fn uart4en(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "UART4 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_uart4en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "UART5 clock enable Set and reset by software."]
#[inline(always)]
pub const fn uart5en(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "UART5 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_uart5en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "I2C1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn i2c1en(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_i2c1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 clock enable Set and reset by software."]
#[inline(always)]
pub const fn i2c2en(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_i2c2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "I3C1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn i3c1en(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "I3C1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_i3c1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "CRS clock enable Set and reset by software."]
#[inline(always)]
pub const fn crsen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "CRS clock enable Set and reset by software."]
#[inline(always)]
pub fn set_crsen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "USART6 clock enable Set and reset by software."]
#[inline(always)]
pub const fn usart6en(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "USART6 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_usart6en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "USART10 clock enable Set and reset by software."]
#[inline(always)]
pub const fn usart10en(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "USART10 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_usart10en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "USART11 clock enable"]
#[inline(always)]
pub const fn usart11en(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "USART11 clock enable"]
#[inline(always)]
pub fn set_usart11en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "HDMI-CEC clock enable Set and reset by software."]
#[inline(always)]
pub const fn cecen(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "HDMI-CEC clock enable Set and reset by software."]
#[inline(always)]
pub fn set_cecen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "UART7 clock enable Set and reset by software."]
#[inline(always)]
pub const fn uart7en(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "UART7 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_uart7en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "UART8 clock enable Set and reset by software."]
#[inline(always)]
pub const fn uart8en(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "UART8 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_uart8en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apb1lenr {
#[inline(always)]
fn default() -> Apb1lenr {
Apb1lenr(0)
}
}
impl core::fmt::Debug for Apb1lenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1lenr")
.field("tim2en", &self.tim2en())
.field("tim3en", &self.tim3en())
.field("tim4en", &self.tim4en())
.field("tim5en", &self.tim5en())
.field("tim6en", &self.tim6en())
.field("tim7en", &self.tim7en())
.field("tim12en", &self.tim12en())
.field("tim13en", &self.tim13en())
.field("tim14en", &self.tim14en())
.field("wwdgen", &self.wwdgen())
.field("spi2en", &self.spi2en())
.field("spi3en", &self.spi3en())
.field("usart2en", &self.usart2en())
.field("usart3en", &self.usart3en())
.field("uart4en", &self.uart4en())
.field("uart5en", &self.uart5en())
.field("i2c1en", &self.i2c1en())
.field("i2c2en", &self.i2c2en())
.field("i3c1en", &self.i3c1en())
.field("crsen", &self.crsen())
.field("usart6en", &self.usart6en())
.field("usart10en", &self.usart10en())
.field("usart11en", &self.usart11en())
.field("cecen", &self.cecen())
.field("uart7en", &self.uart7en())
.field("uart8en", &self.uart8en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1lenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1lenr {{ tim2en: {=bool:?}, tim3en: {=bool:?}, tim4en: {=bool:?}, tim5en: {=bool:?}, tim6en: {=bool:?}, tim7en: {=bool:?}, tim12en: {=bool:?}, tim13en: {=bool:?}, tim14en: {=bool:?}, wwdgen: {=bool:?}, spi2en: {=bool:?}, spi3en: {=bool:?}, usart2en: {=bool:?}, usart3en: {=bool:?}, uart4en: {=bool:?}, uart5en: {=bool:?}, i2c1en: {=bool:?}, i2c2en: {=bool:?}, i3c1en: {=bool:?}, crsen: {=bool:?}, usart6en: {=bool:?}, usart10en: {=bool:?}, usart11en: {=bool:?}, cecen: {=bool:?}, uart7en: {=bool:?}, uart8en: {=bool:?} }}" , self . tim2en () , self . tim3en () , self . tim4en () , self . tim5en () , self . tim6en () , self . tim7en () , self . tim12en () , self . tim13en () , self . tim14en () , self . wwdgen () , self . spi2en () , self . spi3en () , self . usart2en () , self . usart3en () , self . uart4en () , self . uart5en () , self . i2c1en () , self . i2c2en () , self . i3c1en () , self . crsen () , self . usart6en () , self . usart10en () , self . usart11en () , self . cecen () , self . uart7en () , self . uart8en ())
}
}
#[doc = "RCC APB1 sleep clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1llpenr(pub u32);
impl Apb1llpenr {
#[doc = "TIM2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim2lpen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim3lpen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "TIM3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim3lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "TIM4 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim4lpen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "TIM4 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim4lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "TIM5 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim5lpen(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "TIM5 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim5lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "TIM6 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim6lpen(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "TIM6 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim6lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "TIM7 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim7lpen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "TIM7 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim7lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "TIM12 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim12lpen(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "TIM12 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim12lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "TIM13 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim13lpen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "TIM13 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim13lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "TIM14 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim14lpen(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "TIM14 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim14lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "WWDG clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn wwdglpen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "WWDG clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_wwdglpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn spi2lpen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_spi2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "SPI3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn spi3lpen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "SPI3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_spi3lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "USART2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn usart2lpen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_usart2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn usart3lpen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_usart3lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "UART4 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn uart4lpen(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "UART4 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_uart4lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "UART5 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn uart5lpen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "UART5 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_uart5lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "I2C1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn i2c1lpen(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_i2c1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn i2c2lpen(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_i2c2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "I3C1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn i3c1lpen(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "I3C1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_i3c1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "CRS clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn crslpen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "CRS clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_crslpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "USART6 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn usart6lpen(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "USART6 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_usart6lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "USART10 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn usart10lpen(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "USART10 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_usart10lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "USART11 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn usart11lpen(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "USART11 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_usart11lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "HDMI-CEC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn ceclpen(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "HDMI-CEC clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_ceclpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "UART7 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn uart7lpen(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "UART7 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_uart7lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "UART8 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn uart8lpen(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "UART8 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_uart8lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apb1llpenr {
#[inline(always)]
fn default() -> Apb1llpenr {
Apb1llpenr(0)
}
}
impl core::fmt::Debug for Apb1llpenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1llpenr")
.field("tim2lpen", &self.tim2lpen())
.field("tim3lpen", &self.tim3lpen())
.field("tim4lpen", &self.tim4lpen())
.field("tim5lpen", &self.tim5lpen())
.field("tim6lpen", &self.tim6lpen())
.field("tim7lpen", &self.tim7lpen())
.field("tim12lpen", &self.tim12lpen())
.field("tim13lpen", &self.tim13lpen())
.field("tim14lpen", &self.tim14lpen())
.field("wwdglpen", &self.wwdglpen())
.field("spi2lpen", &self.spi2lpen())
.field("spi3lpen", &self.spi3lpen())
.field("usart2lpen", &self.usart2lpen())
.field("usart3lpen", &self.usart3lpen())
.field("uart4lpen", &self.uart4lpen())
.field("uart5lpen", &self.uart5lpen())
.field("i2c1lpen", &self.i2c1lpen())
.field("i2c2lpen", &self.i2c2lpen())
.field("i3c1lpen", &self.i3c1lpen())
.field("crslpen", &self.crslpen())
.field("usart6lpen", &self.usart6lpen())
.field("usart10lpen", &self.usart10lpen())
.field("usart11lpen", &self.usart11lpen())
.field("ceclpen", &self.ceclpen())
.field("uart7lpen", &self.uart7lpen())
.field("uart8lpen", &self.uart8lpen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1llpenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1llpenr {{ tim2lpen: {=bool:?}, tim3lpen: {=bool:?}, tim4lpen: {=bool:?}, tim5lpen: {=bool:?}, tim6lpen: {=bool:?}, tim7lpen: {=bool:?}, tim12lpen: {=bool:?}, tim13lpen: {=bool:?}, tim14lpen: {=bool:?}, wwdglpen: {=bool:?}, spi2lpen: {=bool:?}, spi3lpen: {=bool:?}, usart2lpen: {=bool:?}, usart3lpen: {=bool:?}, uart4lpen: {=bool:?}, uart5lpen: {=bool:?}, i2c1lpen: {=bool:?}, i2c2lpen: {=bool:?}, i3c1lpen: {=bool:?}, crslpen: {=bool:?}, usart6lpen: {=bool:?}, usart10lpen: {=bool:?}, usart11lpen: {=bool:?}, ceclpen: {=bool:?}, uart7lpen: {=bool:?}, uart8lpen: {=bool:?} }}" , self . tim2lpen () , self . tim3lpen () , self . tim4lpen () , self . tim5lpen () , self . tim6lpen () , self . tim7lpen () , self . tim12lpen () , self . tim13lpen () , self . tim14lpen () , self . wwdglpen () , self . spi2lpen () , self . spi3lpen () , self . usart2lpen () , self . usart3lpen () , self . uart4lpen () , self . uart5lpen () , self . i2c1lpen () , self . i2c2lpen () , self . i3c1lpen () , self . crslpen () , self . usart6lpen () , self . usart10lpen () , self . usart11lpen () , self . ceclpen () , self . uart7lpen () , self . uart8lpen ())
}
}
#[doc = "RCC APB1 peripheral low reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1lrstr(pub u32);
impl Apb1lrstr {
#[doc = "TIM2 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim2rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM3 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim3rst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "TIM3 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "TIM4 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim4rst(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "TIM4 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim4rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "TIM5 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim5rst(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "TIM5 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim5rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "TIM6 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim6rst(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "TIM6 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim6rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "TIM7 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim7rst(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "TIM7 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim7rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "TIM12 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim12rst(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "TIM12 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim12rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "TIM13 block reset t Set and reset by software."]
#[inline(always)]
pub const fn tim13rst(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "TIM13 block reset t Set and reset by software."]
#[inline(always)]
pub fn set_tim13rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "TIM14 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim14rst(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "TIM14 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim14rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "SPI2 block reset Set and reset by software."]
#[inline(always)]
pub const fn spi2rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 block reset Set and reset by software."]
#[inline(always)]
pub fn set_spi2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "SPI3 block reset Set and reset by software."]
#[inline(always)]
pub const fn spi3rst(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "SPI3 block reset Set and reset by software."]
#[inline(always)]
pub fn set_spi3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "USART2 block reset Set and reset by software."]
#[inline(always)]
pub const fn usart2rst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 block reset Set and reset by software."]
#[inline(always)]
pub fn set_usart2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART3 block reset Set and reset by software."]
#[inline(always)]
pub const fn usart3rst(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART3 block reset Set and reset by software."]
#[inline(always)]
pub fn set_usart3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "UART4 block reset Set and reset by software."]
#[inline(always)]
pub const fn uart4rst(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "UART4 block reset Set and reset by software."]
#[inline(always)]
pub fn set_uart4rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "UART5 block reset Set and reset by software."]
#[inline(always)]
pub const fn uart5rst(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "UART5 block reset Set and reset by software."]
#[inline(always)]
pub fn set_uart5rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "I2C1 block reset Set and reset by software."]
#[inline(always)]
pub const fn i2c1rst(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 block reset Set and reset by software."]
#[inline(always)]
pub fn set_i2c1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 block reset Set and reset by software."]
#[inline(always)]
pub const fn i2c2rst(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 block reset Set and reset by software."]
#[inline(always)]
pub fn set_i2c2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "I3C1 block reset Set and reset by software."]
#[inline(always)]
pub const fn i3c1rst(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "I3C1 block reset Set and reset by software."]
#[inline(always)]
pub fn set_i3c1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "CRS block reset Set and reset by software."]
#[inline(always)]
pub const fn crsrst(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "CRS block reset Set and reset by software."]
#[inline(always)]
pub fn set_crsrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "USART6 block reset Set and reset by software."]
#[inline(always)]
pub const fn usart6rst(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "USART6 block reset Set and reset by software."]
#[inline(always)]
pub fn set_usart6rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "USART10 block reset Set and reset by software."]
#[inline(always)]
pub const fn usart10rst(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "USART10 block reset Set and reset by software."]
#[inline(always)]
pub fn set_usart10rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "USART11 block reset Set and reset by software."]
#[inline(always)]
pub const fn usart11rst(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "USART11 block reset Set and reset by software."]
#[inline(always)]
pub fn set_usart11rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "HDMI-CEC block reset Set and reset by software."]
#[inline(always)]
pub const fn cecrst(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "HDMI-CEC block reset Set and reset by software."]
#[inline(always)]
pub fn set_cecrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "UART7 block reset Set and reset by software."]
#[inline(always)]
pub const fn uart7rst(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "UART7 block reset Set and reset by software."]
#[inline(always)]
pub fn set_uart7rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "UART8 block reset Set and reset by software."]
#[inline(always)]
pub const fn uart8rst(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "UART8 block reset Set and reset by software."]
#[inline(always)]
pub fn set_uart8rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apb1lrstr {
#[inline(always)]
fn default() -> Apb1lrstr {
Apb1lrstr(0)
}
}
impl core::fmt::Debug for Apb1lrstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1lrstr")
.field("tim2rst", &self.tim2rst())
.field("tim3rst", &self.tim3rst())
.field("tim4rst", &self.tim4rst())
.field("tim5rst", &self.tim5rst())
.field("tim6rst", &self.tim6rst())
.field("tim7rst", &self.tim7rst())
.field("tim12rst", &self.tim12rst())
.field("tim13rst", &self.tim13rst())
.field("tim14rst", &self.tim14rst())
.field("spi2rst", &self.spi2rst())
.field("spi3rst", &self.spi3rst())
.field("usart2rst", &self.usart2rst())
.field("usart3rst", &self.usart3rst())
.field("uart4rst", &self.uart4rst())
.field("uart5rst", &self.uart5rst())
.field("i2c1rst", &self.i2c1rst())
.field("i2c2rst", &self.i2c2rst())
.field("i3c1rst", &self.i3c1rst())
.field("crsrst", &self.crsrst())
.field("usart6rst", &self.usart6rst())
.field("usart10rst", &self.usart10rst())
.field("usart11rst", &self.usart11rst())
.field("cecrst", &self.cecrst())
.field("uart7rst", &self.uart7rst())
.field("uart8rst", &self.uart8rst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1lrstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1lrstr {{ tim2rst: {=bool:?}, tim3rst: {=bool:?}, tim4rst: {=bool:?}, tim5rst: {=bool:?}, tim6rst: {=bool:?}, tim7rst: {=bool:?}, tim12rst: {=bool:?}, tim13rst: {=bool:?}, tim14rst: {=bool:?}, spi2rst: {=bool:?}, spi3rst: {=bool:?}, usart2rst: {=bool:?}, usart3rst: {=bool:?}, uart4rst: {=bool:?}, uart5rst: {=bool:?}, i2c1rst: {=bool:?}, i2c2rst: {=bool:?}, i3c1rst: {=bool:?}, crsrst: {=bool:?}, usart6rst: {=bool:?}, usart10rst: {=bool:?}, usart11rst: {=bool:?}, cecrst: {=bool:?}, uart7rst: {=bool:?}, uart8rst: {=bool:?} }}" , self . tim2rst () , self . tim3rst () , self . tim4rst () , self . tim5rst () , self . tim6rst () , self . tim7rst () , self . tim12rst () , self . tim13rst () , self . tim14rst () , self . spi2rst () , self . spi3rst () , self . usart2rst () , self . usart3rst () , self . uart4rst () , self . uart5rst () , self . i2c1rst () , self . i2c2rst () , self . i3c1rst () , self . crsrst () , self . usart6rst () , self . usart10rst () , self . usart11rst () , self . cecrst () , self . uart7rst () , self . uart8rst ())
}
}
#[doc = "RCC APB2 peripheral clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb2enr(pub u32);
impl Apb2enr {
#[doc = "TIM1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim1en(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn spi1en(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_spi1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "TIM8 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim8en(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "TIM8 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim8en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "USART1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn usart1en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_usart1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM15 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim15en(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "TIM15 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim15en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "TIM16 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim16en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim16en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM17 clock enable Set and reset by software."]
#[inline(always)]
pub const fn tim17en(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM17 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_tim17en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "SPI4 clock enable Set and reset by software."]
#[inline(always)]
pub const fn spi4en(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "SPI4 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_spi4en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "SPI6 clock enable Set and reset by software."]
#[inline(always)]
pub const fn spi6en(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "SPI6 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_spi6en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "SAI1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn sai1en(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "SAI1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_sai1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "SAI2 clock enable Set and cleared by software."]
#[inline(always)]
pub const fn sai2en(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "SAI2 clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_sai2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "USB clock enable Set and reset by software."]
#[inline(always)]
pub const fn usben(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "USB clock enable Set and reset by software."]
#[inline(always)]
pub fn set_usben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
}
impl Default for Apb2enr {
#[inline(always)]
fn default() -> Apb2enr {
Apb2enr(0)
}
}
impl core::fmt::Debug for Apb2enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb2enr")
.field("tim1en", &self.tim1en())
.field("spi1en", &self.spi1en())
.field("tim8en", &self.tim8en())
.field("usart1en", &self.usart1en())
.field("tim15en", &self.tim15en())
.field("tim16en", &self.tim16en())
.field("tim17en", &self.tim17en())
.field("spi4en", &self.spi4en())
.field("spi6en", &self.spi6en())
.field("sai1en", &self.sai1en())
.field("sai2en", &self.sai2en())
.field("usben", &self.usben())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb2enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb2enr {{ tim1en: {=bool:?}, spi1en: {=bool:?}, tim8en: {=bool:?}, usart1en: {=bool:?}, tim15en: {=bool:?}, tim16en: {=bool:?}, tim17en: {=bool:?}, spi4en: {=bool:?}, spi6en: {=bool:?}, sai1en: {=bool:?}, sai2en: {=bool:?}, usben: {=bool:?} }}" , self . tim1en () , self . spi1en () , self . tim8en () , self . usart1en () , self . tim15en () , self . tim16en () , self . tim17en () , self . spi4en () , self . spi6en () , self . sai1en () , self . sai2en () , self . usben ())
}
}
#[doc = "RCC APB2 sleep clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb2lpenr(pub u32);
impl Apb2lpenr {
#[doc = "TIM1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim1lpen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn spi1lpen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_spi1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "TIM8 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim8lpen(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "TIM8 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim8lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "USART1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn usart1lpen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_usart1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM15 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim15lpen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "TIM15 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim15lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "TIM16 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim16lpen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim16lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM17 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn tim17lpen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM17 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_tim17lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "SPI4 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn spi4lpen(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "SPI4 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_spi4lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "SPI6 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn spi6lpen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "SPI6 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_spi6lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "SAI1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn sai1lpen(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "SAI1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_sai1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "SAI2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn sai2lpen(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "SAI2 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_sai2lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "USB clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn usblpen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "USB clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_usblpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
}
impl Default for Apb2lpenr {
#[inline(always)]
fn default() -> Apb2lpenr {
Apb2lpenr(0)
}
}
impl core::fmt::Debug for Apb2lpenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb2lpenr")
.field("tim1lpen", &self.tim1lpen())
.field("spi1lpen", &self.spi1lpen())
.field("tim8lpen", &self.tim8lpen())
.field("usart1lpen", &self.usart1lpen())
.field("tim15lpen", &self.tim15lpen())
.field("tim16lpen", &self.tim16lpen())
.field("tim17lpen", &self.tim17lpen())
.field("spi4lpen", &self.spi4lpen())
.field("spi6lpen", &self.spi6lpen())
.field("sai1lpen", &self.sai1lpen())
.field("sai2lpen", &self.sai2lpen())
.field("usblpen", &self.usblpen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb2lpenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb2lpenr {{ tim1lpen: {=bool:?}, spi1lpen: {=bool:?}, tim8lpen: {=bool:?}, usart1lpen: {=bool:?}, tim15lpen: {=bool:?}, tim16lpen: {=bool:?}, tim17lpen: {=bool:?}, spi4lpen: {=bool:?}, spi6lpen: {=bool:?}, sai1lpen: {=bool:?}, sai2lpen: {=bool:?}, usblpen: {=bool:?} }}" , self . tim1lpen () , self . spi1lpen () , self . tim8lpen () , self . usart1lpen () , self . tim15lpen () , self . tim16lpen () , self . tim17lpen () , self . spi4lpen () , self . spi6lpen () , self . sai1lpen () , self . sai2lpen () , self . usblpen ())
}
}
#[doc = "RCC APB2 peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb2rstr(pub u32);
impl Apb2rstr {
#[doc = "TIM1 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim1rst(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 block reset Set and reset by software."]
#[inline(always)]
pub const fn spi1rst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 block reset Set and reset by software."]
#[inline(always)]
pub fn set_spi1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "TIM8 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim8rst(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "TIM8 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim8rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "USART1 block reset Set and reset by software."]
#[inline(always)]
pub const fn usart1rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 block reset Set and reset by software."]
#[inline(always)]
pub fn set_usart1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM15 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim15rst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "TIM15 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim15rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "TIM16 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim16rst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim16rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM17 block reset Set and reset by software."]
#[inline(always)]
pub const fn tim17rst(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM17 block reset Set and reset by software."]
#[inline(always)]
pub fn set_tim17rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "SPI4 block reset Set and reset by software."]
#[inline(always)]
pub const fn spi4rst(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "SPI4 block reset Set and reset by software."]
#[inline(always)]
pub fn set_spi4rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "SPI6 block reset Set and reset by software."]
#[inline(always)]
pub const fn spi6rst(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "SPI6 block reset Set and reset by software."]
#[inline(always)]
pub fn set_spi6rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "SAI1 block reset Set and reset by software."]
#[inline(always)]
pub const fn sai1rst(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "SAI1 block reset Set and reset by software."]
#[inline(always)]
pub fn set_sai1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "SAI2 block reset Set and reset by software."]
#[inline(always)]
pub const fn sai2rst(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "SAI2 block reset Set and reset by software."]
#[inline(always)]
pub fn set_sai2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "USB block reset Set and reset by software."]
#[inline(always)]
pub const fn usbrst(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "USB block reset Set and reset by software."]
#[inline(always)]
pub fn set_usbrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
}
impl Default for Apb2rstr {
#[inline(always)]
fn default() -> Apb2rstr {
Apb2rstr(0)
}
}
impl core::fmt::Debug for Apb2rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb2rstr")
.field("tim1rst", &self.tim1rst())
.field("spi1rst", &self.spi1rst())
.field("tim8rst", &self.tim8rst())
.field("usart1rst", &self.usart1rst())
.field("tim15rst", &self.tim15rst())
.field("tim16rst", &self.tim16rst())
.field("tim17rst", &self.tim17rst())
.field("spi4rst", &self.spi4rst())
.field("spi6rst", &self.spi6rst())
.field("sai1rst", &self.sai1rst())
.field("sai2rst", &self.sai2rst())
.field("usbrst", &self.usbrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb2rstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb2rstr {{ tim1rst: {=bool:?}, spi1rst: {=bool:?}, tim8rst: {=bool:?}, usart1rst: {=bool:?}, tim15rst: {=bool:?}, tim16rst: {=bool:?}, tim17rst: {=bool:?}, spi4rst: {=bool:?}, spi6rst: {=bool:?}, sai1rst: {=bool:?}, sai2rst: {=bool:?}, usbrst: {=bool:?} }}" , self . tim1rst () , self . spi1rst () , self . tim8rst () , self . usart1rst () , self . tim15rst () , self . tim16rst () , self . tim17rst () , self . spi4rst () , self . spi6rst () , self . sai1rst () , self . sai2rst () , self . usbrst ())
}
}
#[doc = "RCC APB3 peripheral clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb3enr(pub u32);
impl Apb3enr {
#[doc = "SBS clock enable Set and reset by software."]
#[inline(always)]
pub const fn syscfgen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "SBS clock enable Set and reset by software."]
#[inline(always)]
pub fn set_syscfgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "SPI5 clock enable Set and reset by software."]
#[inline(always)]
pub const fn spi5en(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "SPI5 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_spi5en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "LPUART1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn lpuart1en(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "LPUART1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_lpuart1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "I2C3 clock enable Set and reset by software."]
#[inline(always)]
pub const fn i2c3en(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "I2C3 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_i2c3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "I2C4 clock enable Set and reset by software."]
#[inline(always)]
pub const fn i2c4en(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "I2C4 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_i2c4en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "LPTIM1 clock enable Set and reset by software."]
#[inline(always)]
pub const fn lptim1en(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "LPTIM1 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_lptim1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "LPTIM3 clock enable Set and reset by software."]
#[inline(always)]
pub const fn lptim3en(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "LPTIM3 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_lptim3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "LPTIM4 clock enable Set and reset by software."]
#[inline(always)]
pub const fn lptim4en(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "LPTIM4 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_lptim4en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "LPTIM5 clock enable Set and reset by software."]
#[inline(always)]
pub const fn lptim5en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "LPTIM5 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_lptim5en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "LPTIM6 clock enable Set and reset by software."]
#[inline(always)]
pub const fn lptim6en(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "LPTIM6 clock enable Set and reset by software."]
#[inline(always)]
pub fn set_lptim6en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "VREF clock enable Set and reset by software."]
#[inline(always)]
pub const fn vrefen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "VREF clock enable Set and reset by software."]
#[inline(always)]
pub fn set_vrefen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "RTC APB interface clock enable Set and reset by software."]
#[inline(always)]
pub const fn rtcapben(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "RTC APB interface clock enable Set and reset by software."]
#[inline(always)]
pub fn set_rtcapben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
}
impl Default for Apb3enr {
#[inline(always)]
fn default() -> Apb3enr {
Apb3enr(0)
}
}
impl core::fmt::Debug for Apb3enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb3enr")
.field("syscfgen", &self.syscfgen())
.field("spi5en", &self.spi5en())
.field("lpuart1en", &self.lpuart1en())
.field("i2c3en", &self.i2c3en())
.field("i2c4en", &self.i2c4en())
.field("lptim1en", &self.lptim1en())
.field("lptim3en", &self.lptim3en())
.field("lptim4en", &self.lptim4en())
.field("lptim5en", &self.lptim5en())
.field("lptim6en", &self.lptim6en())
.field("vrefen", &self.vrefen())
.field("rtcapben", &self.rtcapben())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb3enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb3enr {{ syscfgen: {=bool:?}, spi5en: {=bool:?}, lpuart1en: {=bool:?}, i2c3en: {=bool:?}, i2c4en: {=bool:?}, lptim1en: {=bool:?}, lptim3en: {=bool:?}, lptim4en: {=bool:?}, lptim5en: {=bool:?}, lptim6en: {=bool:?}, vrefen: {=bool:?}, rtcapben: {=bool:?} }}" , self . syscfgen () , self . spi5en () , self . lpuart1en () , self . i2c3en () , self . i2c4en () , self . lptim1en () , self . lptim3en () , self . lptim4en () , self . lptim5en () , self . lptim6en () , self . vrefen () , self . rtcapben ())
}
}
#[doc = "RCC APB3 sleep clock register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb3lpenr(pub u32);
impl Apb3lpenr {
#[doc = "SBS clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn syscfglpen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "SBS clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_syscfglpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "SPI5 clock enable during Slsleepeep mode Set and reset by software."]
#[inline(always)]
pub const fn spi5lpen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "SPI5 clock enable during Slsleepeep mode Set and reset by software."]
#[inline(always)]
pub fn set_spi5lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "LPUART1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn lpuart1lpen(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "LPUART1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_lpuart1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "I2C3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn i2c3lpen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "I2C3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_i2c3lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "I2C4 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn i2c4lpen(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "I2C4 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_i2c4lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "LPTIM1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn lptim1lpen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "LPTIM1 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_lptim1lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "LPTIM3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn lptim3lpen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "LPTIM3 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_lptim3lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "LPTIM4 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn lptim4lpen(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "LPTIM4 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_lptim4lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "LPTIM5 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn lptim5lpen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "LPTIM5 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_lptim5lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "LPTIM6 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn lptim6lpen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "LPTIM6 clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_lptim6lpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "VREF clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn vreflpen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "VREF clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_vreflpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "RTC APB interface clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub const fn rtcapblpen(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "RTC APB interface clock enable during sleep mode Set and reset by software."]
#[inline(always)]
pub fn set_rtcapblpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
}
impl Default for Apb3lpenr {
#[inline(always)]
fn default() -> Apb3lpenr {
Apb3lpenr(0)
}
}
impl core::fmt::Debug for Apb3lpenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb3lpenr")
.field("syscfglpen", &self.syscfglpen())
.field("spi5lpen", &self.spi5lpen())
.field("lpuart1lpen", &self.lpuart1lpen())
.field("i2c3lpen", &self.i2c3lpen())
.field("i2c4lpen", &self.i2c4lpen())
.field("lptim1lpen", &self.lptim1lpen())
.field("lptim3lpen", &self.lptim3lpen())
.field("lptim4lpen", &self.lptim4lpen())
.field("lptim5lpen", &self.lptim5lpen())
.field("lptim6lpen", &self.lptim6lpen())
.field("vreflpen", &self.vreflpen())
.field("rtcapblpen", &self.rtcapblpen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb3lpenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb3lpenr {{ syscfglpen: {=bool:?}, spi5lpen: {=bool:?}, lpuart1lpen: {=bool:?}, i2c3lpen: {=bool:?}, i2c4lpen: {=bool:?}, lptim1lpen: {=bool:?}, lptim3lpen: {=bool:?}, lptim4lpen: {=bool:?}, lptim5lpen: {=bool:?}, lptim6lpen: {=bool:?}, vreflpen: {=bool:?}, rtcapblpen: {=bool:?} }}" , self . syscfglpen () , self . spi5lpen () , self . lpuart1lpen () , self . i2c3lpen () , self . i2c4lpen () , self . lptim1lpen () , self . lptim3lpen () , self . lptim4lpen () , self . lptim5lpen () , self . lptim6lpen () , self . vreflpen () , self . rtcapblpen ())
}
}
#[doc = "RCC APB3 peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb3rstr(pub u32);
impl Apb3rstr {
#[doc = "SBS block reset Set and reset by software."]
#[inline(always)]
pub const fn syscfgrst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "SBS block reset Set and reset by software."]
#[inline(always)]
pub fn set_syscfgrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "SPI5 block reset Set and reset by software."]
#[inline(always)]
pub const fn spi5rst(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "SPI5 block reset Set and reset by software."]
#[inline(always)]
pub fn set_spi5rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "LPUART1 block reset Set and reset by software."]
#[inline(always)]
pub const fn lpuart1rst(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "LPUART1 block reset Set and reset by software."]
#[inline(always)]
pub fn set_lpuart1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "I2C3 block reset Set and reset by software."]
#[inline(always)]
pub const fn i2c3rst(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "I2C3 block reset Set and reset by software."]
#[inline(always)]
pub fn set_i2c3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "I2C4 block reset Set and reset by software."]
#[inline(always)]
pub const fn i2c4rst(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "I2C4 block reset Set and reset by software."]
#[inline(always)]
pub fn set_i2c4rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "LPTIM1 block reset Set and reset by software."]
#[inline(always)]
pub const fn lptim1rst(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "LPTIM1 block reset Set and reset by software."]
#[inline(always)]
pub fn set_lptim1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "LPTIM3 block reset Set and reset by software."]
#[inline(always)]
pub const fn lptim3rst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "LPTIM3 block reset Set and reset by software."]
#[inline(always)]
pub fn set_lptim3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "LPTIM4 block reset Set and reset by software."]
#[inline(always)]
pub const fn lptim4rst(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "LPTIM4 block reset Set and reset by software."]
#[inline(always)]
pub fn set_lptim4rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "LPTIM5 block reset Set and reset by software."]
#[inline(always)]
pub const fn lptim5rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "LPTIM5 block reset Set and reset by software."]
#[inline(always)]
pub fn set_lptim5rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "LPTIM6 block reset Set and reset by software."]
#[inline(always)]
pub const fn lptim6rst(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "LPTIM6 block reset Set and reset by software."]
#[inline(always)]
pub fn set_lptim6rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "VREF block reset Set and reset by software."]
#[inline(always)]
pub const fn vrefrst(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "VREF block reset Set and reset by software."]
#[inline(always)]
pub fn set_vrefrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Apb3rstr {
#[inline(always)]
fn default() -> Apb3rstr {
Apb3rstr(0)
}
}
impl core::fmt::Debug for Apb3rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb3rstr")
.field("syscfgrst", &self.syscfgrst())
.field("spi5rst", &self.spi5rst())
.field("lpuart1rst", &self.lpuart1rst())
.field("i2c3rst", &self.i2c3rst())
.field("i2c4rst", &self.i2c4rst())
.field("lptim1rst", &self.lptim1rst())
.field("lptim3rst", &self.lptim3rst())
.field("lptim4rst", &self.lptim4rst())
.field("lptim5rst", &self.lptim5rst())
.field("lptim6rst", &self.lptim6rst())
.field("vrefrst", &self.vrefrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb3rstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb3rstr {{ syscfgrst: {=bool:?}, spi5rst: {=bool:?}, lpuart1rst: {=bool:?}, i2c3rst: {=bool:?}, i2c4rst: {=bool:?}, lptim1rst: {=bool:?}, lptim3rst: {=bool:?}, lptim4rst: {=bool:?}, lptim5rst: {=bool:?}, lptim6rst: {=bool:?}, vrefrst: {=bool:?} }}" , self . syscfgrst () , self . spi5rst () , self . lpuart1rst () , self . i2c3rst () , self . i2c4rst () , self . lptim1rst () , self . lptim3rst () , self . lptim4rst () , self . lptim5rst () , self . lptim6rst () , self . vrefrst ())
}
}
#[doc = "RCC Backup domain control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Bdcr(pub u32);
impl Bdcr {
#[doc = "LSE oscillator enabled Set and reset by software."]
#[inline(always)]
pub const fn lseon(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator enabled Set and reset by software."]
#[inline(always)]
pub fn set_lseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0."]
#[inline(always)]
pub const fn lserdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0."]
#[inline(always)]
pub fn set_lserdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)"]
#[inline(always)]
pub const fn lsebyp(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)"]
#[inline(always)]
pub fn set_lsebyp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)."]
#[inline(always)]
pub const fn lsedrv(&self) -> super::vals::Lsedrv {
let val = (self.0 >> 3usize) & 0x03;
super::vals::Lsedrv::from_bits(val as u8)
}
#[doc = "LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)."]
#[inline(always)]
pub fn set_lsedrv(&mut self, val: super::vals::Lsedrv) {
self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
}
#[doc = "LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON."]
#[inline(always)]
pub const fn lsecsson(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON."]
#[inline(always)]
pub fn set_lsecsson(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator."]
#[inline(always)]
pub const fn lsecssd(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator."]
#[inline(always)]
pub fn set_lsecssd(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "low-speed external clock type in bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled."]
#[inline(always)]
pub const fn lseext(&self) -> super::vals::Lseext {
let val = (self.0 >> 7usize) & 0x01;
super::vals::Lseext::from_bits(val as u8)
}
#[doc = "low-speed external clock type in bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled."]
#[inline(always)]
pub fn set_lseext(&mut self, val: super::vals::Lseext) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
}
#[doc = "RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)."]
#[inline(always)]
pub const fn rtcsel(&self) -> super::vals::Rtcsel {
let val = (self.0 >> 8usize) & 0x03;
super::vals::Rtcsel::from_bits(val as u8)
}
#[doc = "RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)."]
#[inline(always)]
pub fn set_rtcsel(&mut self, val: super::vals::Rtcsel) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
}
#[doc = "RTC clock enable Set and reset by software."]
#[inline(always)]
pub const fn rtcen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "RTC clock enable Set and reset by software."]
#[inline(always)]
pub fn set_rtcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "VSwitch domain software reset Set and reset by software."]
#[inline(always)]
pub const fn vswrst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "VSwitch domain software reset Set and reset by software."]
#[inline(always)]
pub fn set_vswrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Low-speed clock output (LSCO) enable Set and cleared by software."]
#[inline(always)]
pub const fn lscoen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Low-speed clock output (LSCO) enable Set and cleared by software."]
#[inline(always)]
pub fn set_lscoen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Low-speed clock output selection Set and cleared by software."]
#[inline(always)]
pub const fn lscosel(&self) -> super::vals::Lscosel {
let val = (self.0 >> 25usize) & 0x01;
super::vals::Lscosel::from_bits(val as u8)
}
#[doc = "Low-speed clock output selection Set and cleared by software."]
#[inline(always)]
pub fn set_lscosel(&mut self, val: super::vals::Lscosel) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32) & 0x01) << 25usize);
}
#[doc = "LSI oscillator enable Set and cleared by software."]
#[inline(always)]
pub const fn lsion(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "LSI oscillator enable Set and cleared by software."]
#[inline(always)]
pub fn set_lsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0."]
#[inline(always)]
pub const fn lsirdy(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0."]
#[inline(always)]
pub fn set_lsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
}
impl Default for Bdcr {
#[inline(always)]
fn default() -> Bdcr {
Bdcr(0)
}
}
impl core::fmt::Debug for Bdcr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Bdcr")
.field("lseon", &self.lseon())
.field("lserdy", &self.lserdy())
.field("lsebyp", &self.lsebyp())
.field("lsedrv", &self.lsedrv())
.field("lsecsson", &self.lsecsson())
.field("lsecssd", &self.lsecssd())
.field("lseext", &self.lseext())
.field("rtcsel", &self.rtcsel())
.field("rtcen", &self.rtcen())
.field("vswrst", &self.vswrst())
.field("lscoen", &self.lscoen())
.field("lscosel", &self.lscosel())
.field("lsion", &self.lsion())
.field("lsirdy", &self.lsirdy())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Bdcr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Bdcr {{ lseon: {=bool:?}, lserdy: {=bool:?}, lsebyp: {=bool:?}, lsedrv: {:?}, lsecsson: {=bool:?}, lsecssd: {=bool:?}, lseext: {:?}, rtcsel: {:?}, rtcen: {=bool:?}, vswrst: {=bool:?}, lscoen: {=bool:?}, lscosel: {:?}, lsion: {=bool:?}, lsirdy: {=bool:?} }}" , self . lseon () , self . lserdy () , self . lsebyp () , self . lsedrv () , self . lsecsson () , self . lsecssd () , self . lseext () , self . rtcsel () , self . rtcen () , self . vswrst () , self . lscoen () , self . lscosel () , self . lsion () , self . lsirdy ())
}
}
#[doc = "RCC kernel clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ccipr1(pub u32);
impl Ccipr1 {
#[doc = "USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn usart1sel(&self) -> super::vals::Usart1sel {
let val = (self.0 >> 0usize) & 0x07;
super::vals::Usart1sel::from_bits(val as u8)
}
#[doc = "USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_usart1sel(&mut self, val: super::vals::Usart1sel) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
}
#[doc = "USART2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn usart2sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 3usize) & 0x07;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "USART2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_usart2sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x07 << 3usize)) | (((val.to_bits() as u32) & 0x07) << 3usize);
}
#[doc = "USART3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn usart3sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 6usize) & 0x07;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "USART3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_usart3sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x07 << 6usize)) | (((val.to_bits() as u32) & 0x07) << 6usize);
}
#[doc = "UART4 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn uart4sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 9usize) & 0x07;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "UART4 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_uart4sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x07 << 9usize)) | (((val.to_bits() as u32) & 0x07) << 9usize);
}
#[doc = "UART5 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn uart5sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 12usize) & 0x07;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "UART5 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_uart5sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize);
}
#[doc = "USART6 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn usart6sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 15usize) & 0x07;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "USART6 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_usart6sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x07 << 15usize)) | (((val.to_bits() as u32) & 0x07) << 15usize);
}
#[doc = "UART7 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn uart7sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 18usize) & 0x07;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "UART7 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_uart7sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x07 << 18usize)) | (((val.to_bits() as u32) & 0x07) << 18usize);
}
#[doc = "UART8 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn uart8sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 21usize) & 0x07;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "UART8 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_uart8sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x07 << 21usize)) | (((val.to_bits() as u32) & 0x07) << 21usize);
}
#[doc = "UART9 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn uart9sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 24usize) & 0x07;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "UART9 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_uart9sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize);
}
#[doc = "USART10 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn usart10sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 27usize) & 0x07;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "USART10 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_usart10sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x07 << 27usize)) | (((val.to_bits() as u32) & 0x07) << 27usize);
}
#[doc = "TIM12, TIM15 and LPTIM2 input capture source selection Set and reset by software."]
#[inline(always)]
pub const fn timicsel(&self) -> super::vals::Timicsel {
let val = (self.0 >> 31usize) & 0x01;
super::vals::Timicsel::from_bits(val as u8)
}
#[doc = "TIM12, TIM15 and LPTIM2 input capture source selection Set and reset by software."]
#[inline(always)]
pub fn set_timicsel(&mut self, val: super::vals::Timicsel) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize);
}
}
impl Default for Ccipr1 {
#[inline(always)]
fn default() -> Ccipr1 {
Ccipr1(0)
}
}
impl core::fmt::Debug for Ccipr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ccipr1")
.field("usart1sel", &self.usart1sel())
.field("usart2sel", &self.usart2sel())
.field("usart3sel", &self.usart3sel())
.field("uart4sel", &self.uart4sel())
.field("uart5sel", &self.uart5sel())
.field("usart6sel", &self.usart6sel())
.field("uart7sel", &self.uart7sel())
.field("uart8sel", &self.uart8sel())
.field("uart9sel", &self.uart9sel())
.field("usart10sel", &self.usart10sel())
.field("timicsel", &self.timicsel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ccipr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ccipr1 {{ usart1sel: {:?}, usart2sel: {:?}, usart3sel: {:?}, uart4sel: {:?}, uart5sel: {:?}, usart6sel: {:?}, uart7sel: {:?}, uart8sel: {:?}, uart9sel: {:?}, usart10sel: {:?}, timicsel: {:?} }}" , self . usart1sel () , self . usart2sel () , self . usart3sel () , self . uart4sel () , self . uart5sel () , self . usart6sel () , self . uart7sel () , self . uart8sel () , self . uart9sel () , self . usart10sel () , self . timicsel ())
}
}
#[doc = "RCC kernel clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ccipr2(pub u32);
impl Ccipr2 {
#[doc = "USART11 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn usart11sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 0usize) & 0x07;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "USART11 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_usart11sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
}
#[doc = "USART12 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn usart12sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 4usize) & 0x07;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "USART12 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_usart12sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
}
#[doc = "LPTIM1 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn lptim1sel(&self) -> super::vals::Lptimsel {
let val = (self.0 >> 8usize) & 0x07;
super::vals::Lptimsel::from_bits(val as u8)
}
#[doc = "LPTIM1 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_lptim1sel(&mut self, val: super::vals::Lptimsel) {
self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
}
#[doc = "LPTIM2 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn lptim2sel(&self) -> super::vals::Lptim2sel {
let val = (self.0 >> 12usize) & 0x07;
super::vals::Lptim2sel::from_bits(val as u8)
}
#[doc = "LPTIM2 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_lptim2sel(&mut self, val: super::vals::Lptim2sel) {
self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize);
}
#[doc = "LPTIM3 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn lptim3sel(&self) -> super::vals::Lptimsel {
let val = (self.0 >> 16usize) & 0x07;
super::vals::Lptimsel::from_bits(val as u8)
}
#[doc = "LPTIM3 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_lptim3sel(&mut self, val: super::vals::Lptimsel) {
self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize);
}
#[doc = "LPTIM4 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn lptim4sel(&self) -> super::vals::Lptimsel {
let val = (self.0 >> 20usize) & 0x07;
super::vals::Lptimsel::from_bits(val as u8)
}
#[doc = "LPTIM4 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_lptim4sel(&mut self, val: super::vals::Lptimsel) {
self.0 = (self.0 & !(0x07 << 20usize)) | (((val.to_bits() as u32) & 0x07) << 20usize);
}
#[doc = "LPTIM5 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn lptim5sel(&self) -> super::vals::Lptimsel {
let val = (self.0 >> 24usize) & 0x07;
super::vals::Lptimsel::from_bits(val as u8)
}
#[doc = "LPTIM5 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_lptim5sel(&mut self, val: super::vals::Lptimsel) {
self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize);
}
#[doc = "LPTIM6 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn lptim6sel(&self) -> super::vals::Lptimsel {
let val = (self.0 >> 28usize) & 0x07;
super::vals::Lptimsel::from_bits(val as u8)
}
#[doc = "LPTIM6 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_lptim6sel(&mut self, val: super::vals::Lptimsel) {
self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize);
}
}
impl Default for Ccipr2 {
#[inline(always)]
fn default() -> Ccipr2 {
Ccipr2(0)
}
}
impl core::fmt::Debug for Ccipr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ccipr2")
.field("usart11sel", &self.usart11sel())
.field("usart12sel", &self.usart12sel())
.field("lptim1sel", &self.lptim1sel())
.field("lptim2sel", &self.lptim2sel())
.field("lptim3sel", &self.lptim3sel())
.field("lptim4sel", &self.lptim4sel())
.field("lptim5sel", &self.lptim5sel())
.field("lptim6sel", &self.lptim6sel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ccipr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ccipr2 {{ usart11sel: {:?}, usart12sel: {:?}, lptim1sel: {:?}, lptim2sel: {:?}, lptim3sel: {:?}, lptim4sel: {:?}, lptim5sel: {:?}, lptim6sel: {:?} }}" , self . usart11sel () , self . usart12sel () , self . lptim1sel () , self . lptim2sel () , self . lptim3sel () , self . lptim4sel () , self . lptim5sel () , self . lptim6sel ())
}
}
#[doc = "RCC kernel clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ccipr3(pub u32);
impl Ccipr3 {
#[doc = "SPI1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn spi1sel(&self) -> super::vals::Spi1sel {
let val = (self.0 >> 0usize) & 0x07;
super::vals::Spi1sel::from_bits(val as u8)
}
#[doc = "SPI1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_spi1sel(&mut self, val: super::vals::Spi1sel) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
}
#[doc = "SPI2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn spi2sel(&self) -> super::vals::Spi2sel {
let val = (self.0 >> 3usize) & 0x07;
super::vals::Spi2sel::from_bits(val as u8)
}
#[doc = "SPI2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_spi2sel(&mut self, val: super::vals::Spi2sel) {
self.0 = (self.0 & !(0x07 << 3usize)) | (((val.to_bits() as u32) & 0x07) << 3usize);
}
#[doc = "SPI3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn spi3sel(&self) -> super::vals::Spi3sel {
let val = (self.0 >> 6usize) & 0x07;
super::vals::Spi3sel::from_bits(val as u8)
}
#[doc = "SPI3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_spi3sel(&mut self, val: super::vals::Spi3sel) {
self.0 = (self.0 & !(0x07 << 6usize)) | (((val.to_bits() as u32) & 0x07) << 6usize);
}
#[doc = "SPI4 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn spi4sel(&self) -> super::vals::Spi4sel {
let val = (self.0 >> 9usize) & 0x07;
super::vals::Spi4sel::from_bits(val as u8)
}
#[doc = "SPI4 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_spi4sel(&mut self, val: super::vals::Spi4sel) {
self.0 = (self.0 & !(0x07 << 9usize)) | (((val.to_bits() as u32) & 0x07) << 9usize);
}
#[doc = "SPI5 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn spi5sel(&self) -> super::vals::Spi5sel {
let val = (self.0 >> 12usize) & 0x07;
super::vals::Spi5sel::from_bits(val as u8)
}
#[doc = "SPI5 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_spi5sel(&mut self, val: super::vals::Spi5sel) {
self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize);
}
#[doc = "SPI6 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn spi6sel(&self) -> super::vals::Spi6sel {
let val = (self.0 >> 15usize) & 0x07;
super::vals::Spi6sel::from_bits(val as u8)
}
#[doc = "SPI6 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_spi6sel(&mut self, val: super::vals::Spi6sel) {
self.0 = (self.0 & !(0x07 << 15usize)) | (((val.to_bits() as u32) & 0x07) << 15usize);
}
#[doc = "LPUART1 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn lpuart1sel(&self) -> super::vals::Lpusartsel {
let val = (self.0 >> 24usize) & 0x07;
super::vals::Lpusartsel::from_bits(val as u8)
}
#[doc = "LPUART1 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_lpuart1sel(&mut self, val: super::vals::Lpusartsel) {
self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize);
}
}
impl Default for Ccipr3 {
#[inline(always)]
fn default() -> Ccipr3 {
Ccipr3(0)
}
}
impl core::fmt::Debug for Ccipr3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ccipr3")
.field("spi1sel", &self.spi1sel())
.field("spi2sel", &self.spi2sel())
.field("spi3sel", &self.spi3sel())
.field("spi4sel", &self.spi4sel())
.field("spi5sel", &self.spi5sel())
.field("spi6sel", &self.spi6sel())
.field("lpuart1sel", &self.lpuart1sel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ccipr3 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ccipr3 {{ spi1sel: {:?}, spi2sel: {:?}, spi3sel: {:?}, spi4sel: {:?}, spi5sel: {:?}, spi6sel: {:?}, lpuart1sel: {:?} }}" , self . spi1sel () , self . spi2sel () , self . spi3sel () , self . spi4sel () , self . spi5sel () , self . spi6sel () , self . lpuart1sel ())
}
}
#[doc = "RCC kernel clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ccipr4(pub u32);
impl Ccipr4 {
#[doc = "OCTOSPI1 kernel clock source selection Set and reset by software."]
#[inline(always)]
pub const fn octospi1sel(&self) -> super::vals::Octospisel {
let val = (self.0 >> 0usize) & 0x03;
super::vals::Octospisel::from_bits(val as u8)
}
#[doc = "OCTOSPI1 kernel clock source selection Set and reset by software."]
#[inline(always)]
pub fn set_octospi1sel(&mut self, val: super::vals::Octospisel) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "SYSTICK clock source selection Note: rcc_hclk frequency must be four times higher than lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK)."]
#[inline(always)]
pub const fn systicksel(&self) -> super::vals::Systicksel {
let val = (self.0 >> 2usize) & 0x03;
super::vals::Systicksel::from_bits(val as u8)
}
#[doc = "SYSTICK clock source selection Note: rcc_hclk frequency must be four times higher than lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK)."]
#[inline(always)]
pub fn set_systicksel(&mut self, val: super::vals::Systicksel) {
self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
}
#[doc = "USB kernel clock source selection"]
#[inline(always)]
pub const fn usbsel(&self) -> super::vals::Usbsel {
let val = (self.0 >> 4usize) & 0x03;
super::vals::Usbsel::from_bits(val as u8)
}
#[doc = "USB kernel clock source selection"]
#[inline(always)]
pub fn set_usbsel(&mut self, val: super::vals::Usbsel) {
self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
}
#[doc = "SDMMC1 kernel clock source selection"]
#[inline(always)]
pub const fn sdmmc1sel(&self) -> super::vals::Sdmmcsel {
let val = (self.0 >> 6usize) & 0x01;
super::vals::Sdmmcsel::from_bits(val as u8)
}
#[doc = "SDMMC1 kernel clock source selection"]
#[inline(always)]
pub fn set_sdmmc1sel(&mut self, val: super::vals::Sdmmcsel) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
}
#[doc = "SDMMC2 kernel clock source selection"]
#[inline(always)]
pub const fn sdmmc2sel(&self) -> super::vals::Sdmmcsel {
let val = (self.0 >> 7usize) & 0x01;
super::vals::Sdmmcsel::from_bits(val as u8)
}
#[doc = "SDMMC2 kernel clock source selection"]
#[inline(always)]
pub fn set_sdmmc2sel(&mut self, val: super::vals::Sdmmcsel) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
}
#[doc = "I2C1 kernel clock source selection"]
#[inline(always)]
pub const fn i2c1sel(&self) -> super::vals::I2csel {
let val = (self.0 >> 16usize) & 0x03;
super::vals::I2csel::from_bits(val as u8)
}
#[doc = "I2C1 kernel clock source selection"]
#[inline(always)]
pub fn set_i2c1sel(&mut self, val: super::vals::I2csel) {
self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize);
}
#[doc = "I2C2 kernel clock source selection"]
#[inline(always)]
pub const fn i2c2sel(&self) -> super::vals::I2csel {
let val = (self.0 >> 18usize) & 0x03;
super::vals::I2csel::from_bits(val as u8)
}
#[doc = "I2C2 kernel clock source selection"]
#[inline(always)]
pub fn set_i2c2sel(&mut self, val: super::vals::I2csel) {
self.0 = (self.0 & !(0x03 << 18usize)) | (((val.to_bits() as u32) & 0x03) << 18usize);
}
#[doc = "I2C3 kernel clock source selection"]
#[inline(always)]
pub const fn i2c3sel(&self) -> super::vals::I2c34sel {
let val = (self.0 >> 20usize) & 0x03;
super::vals::I2c34sel::from_bits(val as u8)
}
#[doc = "I2C3 kernel clock source selection"]
#[inline(always)]
pub fn set_i2c3sel(&mut self, val: super::vals::I2c34sel) {
self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize);
}
#[doc = "I2C4 kernel clock source selection"]
#[inline(always)]
pub const fn i2c4sel(&self) -> super::vals::I2c34sel {
let val = (self.0 >> 22usize) & 0x03;
super::vals::I2c34sel::from_bits(val as u8)
}
#[doc = "I2C4 kernel clock source selection"]
#[inline(always)]
pub fn set_i2c4sel(&mut self, val: super::vals::I2c34sel) {
self.0 = (self.0 & !(0x03 << 22usize)) | (((val.to_bits() as u32) & 0x03) << 22usize);
}
#[doc = "I3C1 kernel clock source selection"]
#[inline(always)]
pub const fn i3c1sel(&self) -> super::vals::I2csel {
let val = (self.0 >> 24usize) & 0x03;
super::vals::I2csel::from_bits(val as u8)
}
#[doc = "I3C1 kernel clock source selection"]
#[inline(always)]
pub fn set_i3c1sel(&mut self, val: super::vals::I2csel) {
self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize);
}
}
impl Default for Ccipr4 {
#[inline(always)]
fn default() -> Ccipr4 {
Ccipr4(0)
}
}
impl core::fmt::Debug for Ccipr4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ccipr4")
.field("octospi1sel", &self.octospi1sel())
.field("systicksel", &self.systicksel())
.field("usbsel", &self.usbsel())
.field("sdmmc1sel", &self.sdmmc1sel())
.field("sdmmc2sel", &self.sdmmc2sel())
.field("i2c1sel", &self.i2c1sel())
.field("i2c2sel", &self.i2c2sel())
.field("i2c3sel", &self.i2c3sel())
.field("i2c4sel", &self.i2c4sel())
.field("i3c1sel", &self.i3c1sel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ccipr4 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ccipr4 {{ octospi1sel: {:?}, systicksel: {:?}, usbsel: {:?}, sdmmc1sel: {:?}, sdmmc2sel: {:?}, i2c1sel: {:?}, i2c2sel: {:?}, i2c3sel: {:?}, i2c4sel: {:?}, i3c1sel: {:?} }}" , self . octospi1sel () , self . systicksel () , self . usbsel () , self . sdmmc1sel () , self . sdmmc2sel () , self . i2c1sel () , self . i2c2sel () , self . i2c3sel () , self . i2c4sel () , self . i3c1sel ())
}
}
#[doc = "RCC kernel clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ccipr5(pub u32);
impl Ccipr5 {
#[doc = "ADC and DAC kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn adcdacsel(&self) -> super::vals::Adcdacsel {
let val = (self.0 >> 0usize) & 0x07;
super::vals::Adcdacsel::from_bits(val as u8)
}
#[doc = "ADC and DAC kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_adcdacsel(&mut self, val: super::vals::Adcdacsel) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
}
#[doc = "DAC hold clock"]
#[inline(always)]
pub const fn dacholdsel(&self) -> super::vals::Dacholdsel {
let val = (self.0 >> 3usize) & 0x01;
super::vals::Dacholdsel::from_bits(val as u8)
}
#[doc = "DAC hold clock"]
#[inline(always)]
pub fn set_dacholdsel(&mut self, val: super::vals::Dacholdsel) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize);
}
#[doc = "RNG kernel clock source selection"]
#[inline(always)]
pub const fn rngsel(&self) -> super::vals::Rngsel {
let val = (self.0 >> 4usize) & 0x03;
super::vals::Rngsel::from_bits(val as u8)
}
#[doc = "RNG kernel clock source selection"]
#[inline(always)]
pub fn set_rngsel(&mut self, val: super::vals::Rngsel) {
self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
}
#[doc = "HSMI-CEC kernel clock source selection"]
#[inline(always)]
pub const fn cecsel(&self) -> super::vals::Cecsel {
let val = (self.0 >> 6usize) & 0x03;
super::vals::Cecsel::from_bits(val as u8)
}
#[doc = "HSMI-CEC kernel clock source selection"]
#[inline(always)]
pub fn set_cecsel(&mut self, val: super::vals::Cecsel) {
self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize);
}
#[doc = "FDCAN1 and FDCAN2 kernel clock source selection"]
#[inline(always)]
pub const fn fdcan12sel(&self) -> super::vals::Fdcansel {
let val = (self.0 >> 8usize) & 0x03;
super::vals::Fdcansel::from_bits(val as u8)
}
#[doc = "FDCAN1 and FDCAN2 kernel clock source selection"]
#[inline(always)]
pub fn set_fdcan12sel(&mut self, val: super::vals::Fdcansel) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
}
#[doc = "SAI1 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn sai1sel(&self) -> super::vals::Saisel {
let val = (self.0 >> 16usize) & 0x07;
super::vals::Saisel::from_bits(val as u8)
}
#[doc = "SAI1 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_sai1sel(&mut self, val: super::vals::Saisel) {
self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize);
}
#[doc = "SAI2 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub const fn sai2sel(&self) -> super::vals::Saisel {
let val = (self.0 >> 19usize) & 0x07;
super::vals::Saisel::from_bits(val as u8)
}
#[doc = "SAI2 kernel clock source selection others: reserved, the kernel clock is disabled"]
#[inline(always)]
pub fn set_sai2sel(&mut self, val: super::vals::Saisel) {
self.0 = (self.0 & !(0x07 << 19usize)) | (((val.to_bits() as u32) & 0x07) << 19usize);
}
#[doc = "per_ck clock source selection"]
#[inline(always)]
pub const fn persel(&self) -> super::vals::Persel {
let val = (self.0 >> 30usize) & 0x03;
super::vals::Persel::from_bits(val as u8)
}
#[doc = "per_ck clock source selection"]
#[inline(always)]
pub fn set_persel(&mut self, val: super::vals::Persel) {
self.0 = (self.0 & !(0x03 << 30usize)) | (((val.to_bits() as u32) & 0x03) << 30usize);
}
}
impl Default for Ccipr5 {
#[inline(always)]
fn default() -> Ccipr5 {
Ccipr5(0)
}
}
impl core::fmt::Debug for Ccipr5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ccipr5")
.field("adcdacsel", &self.adcdacsel())
.field("dacholdsel", &self.dacholdsel())
.field("rngsel", &self.rngsel())
.field("cecsel", &self.cecsel())
.field("fdcan12sel", &self.fdcan12sel())
.field("sai1sel", &self.sai1sel())
.field("sai2sel", &self.sai2sel())
.field("persel", &self.persel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ccipr5 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ccipr5 {{ adcdacsel: {:?}, dacholdsel: {:?}, rngsel: {:?}, cecsel: {:?}, fdcan12sel: {:?}, sai1sel: {:?}, sai2sel: {:?}, persel: {:?} }}" , self . adcdacsel () , self . dacholdsel () , self . rngsel () , self . cecsel () , self . fdcan12sel () , self . sai1sel () , self . sai2sel () , self . persel ())
}
}
#[doc = "RCC clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfgr(pub u32);
impl Cfgr {
#[doc = "system clock and trace clock switch Set and reset by software to select system clock and trace clock sources (sys_ck). Set by hardware in order to: - force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode - force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock others: reserved"]
#[inline(always)]
pub const fn sw(&self) -> super::vals::Sw {
let val = (self.0 >> 0usize) & 0x07;
super::vals::Sw::from_bits(val as u8)
}
#[doc = "system clock and trace clock switch Set and reset by software to select system clock and trace clock sources (sys_ck). Set by hardware in order to: - force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode - force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock others: reserved"]
#[inline(always)]
pub fn set_sw(&mut self, val: super::vals::Sw) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
}
#[doc = "system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset). others: reserved"]
#[inline(always)]
pub const fn sws(&self) -> super::vals::Sw {
let val = (self.0 >> 3usize) & 0x07;
super::vals::Sw::from_bits(val as u8)
}
#[doc = "system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset). others: reserved"]
#[inline(always)]
pub fn set_sws(&mut self, val: super::vals::Sw) {
self.0 = (self.0 & !(0x07 << 3usize)) | (((val.to_bits() as u32) & 0x07) << 3usize);
}
#[doc = "system clock selection after a wakeup from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset) STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)."]
#[inline(always)]
pub const fn stopwuck(&self) -> super::vals::Stopwuck {
let val = (self.0 >> 6usize) & 0x01;
super::vals::Stopwuck::from_bits(val as u8)
}
#[doc = "system clock selection after a wakeup from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset) STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)."]
#[inline(always)]
pub fn set_stopwuck(&mut self, val: super::vals::Stopwuck) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
}
#[doc = "kernel clock selection after a wakeup from system Stop Set and reset by software to select the kernel wakeup clock from system Stop."]
#[inline(always)]
pub const fn stopkerwuck(&self) -> super::vals::Stopkerwuck {
let val = (self.0 >> 7usize) & 0x01;
super::vals::Stopkerwuck::from_bits(val as u8)
}
#[doc = "kernel clock selection after a wakeup from system Stop Set and reset by software to select the kernel wakeup clock from system Stop."]
#[inline(always)]
pub fn set_stopkerwuck(&mut self, val: super::vals::Stopkerwuck) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
}
#[doc = "HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ..."]
#[inline(always)]
pub const fn rtcpre(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x3f;
val as u8
}
#[doc = "HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ..."]
#[inline(always)]
pub fn set_rtcpre(&mut self, val: u8) {
self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize);
}
#[doc = "timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains."]
#[inline(always)]
pub const fn timpre(&self) -> super::vals::Timpre {
let val = (self.0 >> 15usize) & 0x01;
super::vals::Timpre::from_bits(val as u8)
}
#[doc = "timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains."]
#[inline(always)]
pub fn set_timpre(&mut self, val: super::vals::Timpre) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u32) & 0x01) << 15usize);
}
#[doc = "MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ..."]
#[inline(always)]
pub const fn mco1pre(&self) -> super::vals::Mcopre {
let val = (self.0 >> 18usize) & 0x0f;
super::vals::Mcopre::from_bits(val as u8)
}
#[doc = "MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ..."]
#[inline(always)]
pub fn set_mco1pre(&mut self, val: super::vals::Mcopre) {
self.0 = (self.0 & !(0x0f << 18usize)) | (((val.to_bits() as u32) & 0x0f) << 18usize);
}
#[doc = "Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved"]
#[inline(always)]
pub const fn mco1sel(&self) -> super::vals::Mco1sel {
let val = (self.0 >> 22usize) & 0x07;
super::vals::Mco1sel::from_bits(val as u8)
}
#[doc = "Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved"]
#[inline(always)]
pub fn set_mco1sel(&mut self, val: super::vals::Mco1sel) {
self.0 = (self.0 & !(0x07 << 22usize)) | (((val.to_bits() as u32) & 0x07) << 22usize);
}
#[doc = "MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ..."]
#[inline(always)]
pub const fn mco2pre(&self) -> super::vals::Mcopre {
let val = (self.0 >> 25usize) & 0x0f;
super::vals::Mcopre::from_bits(val as u8)
}
#[doc = "MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ..."]
#[inline(always)]
pub fn set_mco2pre(&mut self, val: super::vals::Mcopre) {
self.0 = (self.0 & !(0x0f << 25usize)) | (((val.to_bits() as u32) & 0x0f) << 25usize);
}
#[doc = "microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved"]
#[inline(always)]
pub const fn mco2sel(&self) -> super::vals::Mco2sel {
let val = (self.0 >> 29usize) & 0x07;
super::vals::Mco2sel::from_bits(val as u8)
}
#[doc = "microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved"]
#[inline(always)]
pub fn set_mco2sel(&mut self, val: super::vals::Mco2sel) {
self.0 = (self.0 & !(0x07 << 29usize)) | (((val.to_bits() as u32) & 0x07) << 29usize);
}
}
impl Default for Cfgr {
#[inline(always)]
fn default() -> Cfgr {
Cfgr(0)
}
}
impl core::fmt::Debug for Cfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cfgr")
.field("sw", &self.sw())
.field("sws", &self.sws())
.field("stopwuck", &self.stopwuck())
.field("stopkerwuck", &self.stopkerwuck())
.field("rtcpre", &self.rtcpre())
.field("timpre", &self.timpre())
.field("mco1pre", &self.mco1pre())
.field("mco1sel", &self.mco1sel())
.field("mco2pre", &self.mco2pre())
.field("mco2sel", &self.mco2sel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cfgr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cfgr {{ sw: {:?}, sws: {:?}, stopwuck: {:?}, stopkerwuck: {:?}, rtcpre: {=u8:?}, timpre: {:?}, mco1pre: {:?}, mco1sel: {:?}, mco2pre: {:?}, mco2sel: {:?} }}" , self . sw () , self . sws () , self . stopwuck () , self . stopkerwuck () , self . rtcpre () , self . timpre () , self . mco1pre () , self . mco1sel () , self . mco2pre () , self . mco2sel ())
}
}
#[doc = "RCC CPU domain clock configuration register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfgr2(pub u32);
impl Cfgr2 {
#[doc = "AHB prescaler Set and reset by software to control the division factor of rcc_hclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks 0xxx: rcc_hclk = sys_ck (default after reset)"]
#[inline(always)]
pub const fn hpre(&self) -> super::vals::Hpre {
let val = (self.0 >> 0usize) & 0x0f;
super::vals::Hpre::from_bits(val as u8)
}
#[doc = "AHB prescaler Set and reset by software to control the division factor of rcc_hclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks 0xxx: rcc_hclk = sys_ck (default after reset)"]
#[inline(always)]
pub fn set_hpre(&mut self, val: super::vals::Hpre) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize);
}
#[doc = "APB low-speed prescaler (APB1) Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write. 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)"]
#[inline(always)]
pub const fn ppre1(&self) -> super::vals::Ppre {
let val = (self.0 >> 4usize) & 0x07;
super::vals::Ppre::from_bits(val as u8)
}
#[doc = "APB low-speed prescaler (APB1) Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write. 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)"]
#[inline(always)]
pub fn set_ppre1(&mut self, val: super::vals::Ppre) {
self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
}
#[doc = "APB high-speed prescaler (APB2) Set and reset by software to control APB high-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write. 0xx: rcc_pclk2 = rcc_hclk1"]
#[inline(always)]
pub const fn ppre2(&self) -> super::vals::Ppre {
let val = (self.0 >> 8usize) & 0x07;
super::vals::Ppre::from_bits(val as u8)
}
#[doc = "APB high-speed prescaler (APB2) Set and reset by software to control APB high-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write. 0xx: rcc_pclk2 = rcc_hclk1"]
#[inline(always)]
pub fn set_ppre2(&mut self, val: super::vals::Ppre) {
self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
}
#[doc = "APB low-speed prescaler (APB3) Set and reset by software to control APB low-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write. 0xx: rcc_pclk3 = rcc_hclk1"]
#[inline(always)]
pub const fn ppre3(&self) -> super::vals::Ppre {
let val = (self.0 >> 12usize) & 0x07;
super::vals::Ppre::from_bits(val as u8)
}
#[doc = "APB low-speed prescaler (APB3) Set and reset by software to control APB low-speed clocks division factor. The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write. 0xx: rcc_pclk3 = rcc_hclk1"]
#[inline(always)]
pub fn set_ppre3(&mut self, val: super::vals::Ppre) {
self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize);
}
#[doc = "AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals from RCC_AHB1ENR are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from RCC_AHB1ENR are off. enable control bits"]
#[inline(always)]
pub const fn ahb1dis(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals from RCC_AHB1ENR are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from RCC_AHB1ENR are off. enable control bits"]
#[inline(always)]
pub fn set_ahb1dis(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "AHB2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR are used and when their clocks are disabled in RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR are off. enable control bits"]
#[inline(always)]
pub const fn ahb2dis(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "AHB2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR are used and when their clocks are disabled in RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR are off. enable control bits"]
#[inline(always)]
pub fn set_ahb2dis(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "AHB4 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB4 peripherals from RCC_AHB4ENR are used and when their clocks are disabled in RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from RCC_AHB4ENR are off. enable control bits"]
#[inline(always)]
pub const fn ahb4dis(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "AHB4 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB4 peripherals from RCC_AHB4ENR are used and when their clocks are disabled in RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from RCC_AHB4ENR are off. enable control bits"]
#[inline(always)]
pub fn set_ahb4dis(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "APB1 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. control bits"]
#[inline(always)]
pub const fn apb1dis(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "APB1 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. control bits"]
#[inline(always)]
pub fn set_apb1dis(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "APB2 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off. control bits"]
#[inline(always)]
pub const fn apb2dis(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "APB2 clock disable value This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off. control bits"]
#[inline(always)]
pub fn set_apb2dis(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "APB3 clock disable value.Set and cleared by software This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. control bits"]
#[inline(always)]
pub const fn apb3dis(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "APB3 clock disable value.Set and cleared by software This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. control bits"]
#[inline(always)]
pub fn set_apb3dis(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
}
impl Default for Cfgr2 {
#[inline(always)]
fn default() -> Cfgr2 {
Cfgr2(0)
}
}
impl core::fmt::Debug for Cfgr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cfgr2")
.field("hpre", &self.hpre())
.field("ppre1", &self.ppre1())
.field("ppre2", &self.ppre2())
.field("ppre3", &self.ppre3())
.field("ahb1dis", &self.ahb1dis())
.field("ahb2dis", &self.ahb2dis())
.field("ahb4dis", &self.ahb4dis())
.field("apb1dis", &self.apb1dis())
.field("apb2dis", &self.apb2dis())
.field("apb3dis", &self.apb3dis())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cfgr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cfgr2 {{ hpre: {:?}, ppre1: {:?}, ppre2: {:?}, ppre3: {:?}, ahb1dis: {=bool:?}, ahb2dis: {=bool:?}, ahb4dis: {=bool:?}, apb1dis: {=bool:?}, apb2dis: {=bool:?}, apb3dis: {=bool:?} }}" , self . hpre () , self . ppre1 () , self . ppre2 () , self . ppre3 () , self . ahb1dis () , self . ahb2dis () , self . ahb4dis () , self . apb1dis () , self . apb2dis () , self . apb3dis ())
}
}
#[doc = "RCC clock source interrupt clear register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cicr(pub u32);
impl Cicr {
#[doc = "LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done."]
#[inline(always)]
pub const fn lsirdyc(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done."]
#[inline(always)]
pub fn set_lsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done."]
#[inline(always)]
pub const fn lserdyc(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done."]
#[inline(always)]
pub fn set_lserdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "HSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done."]
#[inline(always)]
pub const fn csirdyc(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done."]
#[inline(always)]
pub fn set_csirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done."]
#[inline(always)]
pub const fn hsirdyc(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done."]
#[inline(always)]
pub fn set_hsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done."]
#[inline(always)]
pub const fn hserdyc(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done."]
#[inline(always)]
pub fn set_hserdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done."]
#[inline(always)]
pub const fn hsi48rdyc(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done."]
#[inline(always)]
pub fn set_hsi48rdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done."]
#[inline(always)]
pub const fn pllrdyc(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 6usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done."]
#[inline(always)]
pub fn set_pllrdyc(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 6usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done."]
#[inline(always)]
pub const fn hsecssc(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done."]
#[inline(always)]
pub fn set_hsecssc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
}
impl Default for Cicr {
#[inline(always)]
fn default() -> Cicr {
Cicr(0)
}
}
impl core::fmt::Debug for Cicr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cicr")
.field("lsirdyc", &self.lsirdyc())
.field("lserdyc", &self.lserdyc())
.field("csirdyc", &self.csirdyc())
.field("hsirdyc", &self.hsirdyc())
.field("hserdyc", &self.hserdyc())
.field("hsi48rdyc", &self.hsi48rdyc())
.field("pllrdyc[0]", &self.pllrdyc(0usize))
.field("pllrdyc[1]", &self.pllrdyc(1usize))
.field("pllrdyc[2]", &self.pllrdyc(2usize))
.field("hsecssc", &self.hsecssc())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cicr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cicr {{ lsirdyc: {=bool:?}, lserdyc: {=bool:?}, csirdyc: {=bool:?}, hsirdyc: {=bool:?}, hserdyc: {=bool:?}, hsi48rdyc: {=bool:?}, pllrdyc[0]: {=bool:?}, pllrdyc[1]: {=bool:?}, pllrdyc[2]: {=bool:?}, hsecssc: {=bool:?} }}" , self . lsirdyc () , self . lserdyc () , self . csirdyc () , self . hsirdyc () , self . hserdyc () , self . hsi48rdyc () , self . pllrdyc (0usize) , self . pllrdyc (1usize) , self . pllrdyc (2usize) , self . hsecssc ())
}
}
#[doc = "RCC clock source interrupt enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cier(pub u32);
impl Cier {
#[doc = "LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization."]
#[inline(always)]
pub const fn lsirdyie(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization."]
#[inline(always)]
pub fn set_lsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization."]
#[inline(always)]
pub const fn lserdyie(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization."]
#[inline(always)]
pub fn set_lserdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization."]
#[inline(always)]
pub const fn csirdyie(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization."]
#[inline(always)]
pub fn set_csirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization."]
#[inline(always)]
pub const fn hsirdyie(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization."]
#[inline(always)]
pub fn set_hsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization."]
#[inline(always)]
pub const fn hserdyie(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization."]
#[inline(always)]
pub fn set_hserdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization."]
#[inline(always)]
pub const fn hsi48rdyie(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization."]
#[inline(always)]
pub fn set_hsi48rdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock."]
#[inline(always)]
pub const fn pllrdyie(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 6usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock."]
#[inline(always)]
pub fn set_pllrdyie(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 6usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Cier {
#[inline(always)]
fn default() -> Cier {
Cier(0)
}
}
impl core::fmt::Debug for Cier {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cier")
.field("lsirdyie", &self.lsirdyie())
.field("lserdyie", &self.lserdyie())
.field("csirdyie", &self.csirdyie())
.field("hsirdyie", &self.hsirdyie())
.field("hserdyie", &self.hserdyie())
.field("hsi48rdyie", &self.hsi48rdyie())
.field("pllrdyie[0]", &self.pllrdyie(0usize))
.field("pllrdyie[1]", &self.pllrdyie(1usize))
.field("pllrdyie[2]", &self.pllrdyie(2usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cier {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cier {{ lsirdyie: {=bool:?}, lserdyie: {=bool:?}, csirdyie: {=bool:?}, hsirdyie: {=bool:?}, hserdyie: {=bool:?}, hsi48rdyie: {=bool:?}, pllrdyie[0]: {=bool:?}, pllrdyie[1]: {=bool:?}, pllrdyie[2]: {=bool:?} }}" , self . lsirdyie () , self . lserdyie () , self . csirdyie () , self . hsirdyie () , self . hserdyie () , self . hsi48rdyie () , self . pllrdyie (0usize) , self . pllrdyie (1usize) , self . pllrdyie (2usize))
}
}
#[doc = "RCC clock source interrupt flag register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cifr(pub u32);
impl Cifr {
#[doc = "LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set."]
#[inline(always)]
pub const fn lsirdyf(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set."]
#[inline(always)]
pub fn set_lsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set."]
#[inline(always)]
pub const fn lserdyf(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set."]
#[inline(always)]
pub fn set_lserdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set."]
#[inline(always)]
pub const fn csirdyf(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set."]
#[inline(always)]
pub fn set_csirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set."]
#[inline(always)]
pub const fn hsirdyf(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set."]
#[inline(always)]
pub fn set_hsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set."]
#[inline(always)]
pub const fn hserdyf(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set."]
#[inline(always)]
pub fn set_hserdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set."]
#[inline(always)]
pub const fn hsi48rdyf(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set."]
#[inline(always)]
pub fn set_hsi48rdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set."]
#[inline(always)]
pub const fn pllrdyf(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 6usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set."]
#[inline(always)]
pub fn set_pllrdyf(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 6usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure."]
#[inline(always)]
pub const fn hsecssf(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure."]
#[inline(always)]
pub fn set_hsecssf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
}
impl Default for Cifr {
#[inline(always)]
fn default() -> Cifr {
Cifr(0)
}
}
impl core::fmt::Debug for Cifr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cifr")
.field("lsirdyf", &self.lsirdyf())
.field("lserdyf", &self.lserdyf())
.field("csirdyf", &self.csirdyf())
.field("hsirdyf", &self.hsirdyf())
.field("hserdyf", &self.hserdyf())
.field("hsi48rdyf", &self.hsi48rdyf())
.field("pllrdyf[0]", &self.pllrdyf(0usize))
.field("pllrdyf[1]", &self.pllrdyf(1usize))
.field("pllrdyf[2]", &self.pllrdyf(2usize))
.field("hsecssf", &self.hsecssf())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cifr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cifr {{ lsirdyf: {=bool:?}, lserdyf: {=bool:?}, csirdyf: {=bool:?}, hsirdyf: {=bool:?}, hserdyf: {=bool:?}, hsi48rdyf: {=bool:?}, pllrdyf[0]: {=bool:?}, pllrdyf[1]: {=bool:?}, pllrdyf[2]: {=bool:?}, hsecssf: {=bool:?} }}" , self . lsirdyf () , self . lserdyf () , self . csirdyf () , self . hsirdyf () , self . hserdyf () , self . hsi48rdyf () , self . pllrdyf (0usize) , self . pllrdyf (1usize) , self . pllrdyf (2usize) , self . hsecssf ())
}
}
#[doc = "RCC clock control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr(pub u32);
impl Cr {
#[doc = "HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)."]
#[inline(always)]
pub const fn hsion(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)."]
#[inline(always)]
pub fn set_hsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable."]
#[inline(always)]
pub const fn hsirdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable."]
#[inline(always)]
pub fn set_hsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION."]
#[inline(always)]
pub const fn hsikeron(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION."]
#[inline(always)]
pub fn set_hsikeron(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored."]
#[inline(always)]
pub const fn hsidiv(&self) -> super::vals::Hsidiv {
let val = (self.0 >> 3usize) & 0x03;
super::vals::Hsidiv::from_bits(val as u8)
}
#[doc = "HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored."]
#[inline(always)]
pub fn set_hsidiv(&mut self, val: super::vals::Hsidiv) {
self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
}
#[doc = "HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV."]
#[inline(always)]
pub const fn hsidivf(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV."]
#[inline(always)]
pub fn set_hsidivf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)."]
#[inline(always)]
pub const fn csion(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)."]
#[inline(always)]
pub fn set_csion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)."]
#[inline(always)]
pub const fn csirdy(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)."]
#[inline(always)]
pub fn set_csirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION."]
#[inline(always)]
pub const fn csikeron(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION."]
#[inline(always)]
pub fn set_csikeron(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode."]
#[inline(always)]
pub const fn hsi48on(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode."]
#[inline(always)]
pub fn set_hsi48on(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable."]
#[inline(always)]
pub const fn hsi48rdy(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable."]
#[inline(always)]
pub fn set_hsi48rdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)."]
#[inline(always)]
pub const fn hseon(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)."]
#[inline(always)]
pub fn set_hseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable."]
#[inline(always)]
pub const fn hserdy(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable."]
#[inline(always)]
pub fn set_hserdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled."]
#[inline(always)]
pub const fn hsebyp(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled."]
#[inline(always)]
pub fn set_hsebyp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "HSE clock security system enable Set by software to enable clock security system on HSE. This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected."]
#[inline(always)]
pub const fn hsecsson(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "HSE clock security system enable Set by software to enable clock security system on HSE. This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected."]
#[inline(always)]
pub fn set_hsecsson(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled."]
#[inline(always)]
pub const fn hseext(&self) -> super::vals::Hseext {
let val = (self.0 >> 20usize) & 0x01;
super::vals::Hseext::from_bits(val as u8)
}
#[doc = "external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled."]
#[inline(always)]
pub fn set_hseext(&mut self, val: super::vals::Hseext) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val.to_bits() as u32) & 0x01) << 20usize);
}
#[doc = "PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock."]
#[inline(always)]
pub const fn pllon(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 24usize + n * 2usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock."]
#[inline(always)]
pub fn set_pllon(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 24usize + n * 2usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked."]
#[inline(always)]
pub const fn pllrdy(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 25usize + n * 2usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked."]
#[inline(always)]
pub fn set_pllrdy(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 25usize + n * 2usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Cr {
#[inline(always)]
fn default() -> Cr {
Cr(0)
}
}
impl core::fmt::Debug for Cr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cr")
.field("hsion", &self.hsion())
.field("hsirdy", &self.hsirdy())
.field("hsikeron", &self.hsikeron())
.field("hsidiv", &self.hsidiv())
.field("hsidivf", &self.hsidivf())
.field("csion", &self.csion())
.field("csirdy", &self.csirdy())
.field("csikeron", &self.csikeron())
.field("hsi48on", &self.hsi48on())
.field("hsi48rdy", &self.hsi48rdy())
.field("hseon", &self.hseon())
.field("hserdy", &self.hserdy())
.field("hsebyp", &self.hsebyp())
.field("hsecsson", &self.hsecsson())
.field("hseext", &self.hseext())
.field("pllon[0]", &self.pllon(0usize))
.field("pllon[1]", &self.pllon(1usize))
.field("pllon[2]", &self.pllon(2usize))
.field("pllrdy[0]", &self.pllrdy(0usize))
.field("pllrdy[1]", &self.pllrdy(1usize))
.field("pllrdy[2]", &self.pllrdy(2usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cr {{ hsion: {=bool:?}, hsirdy: {=bool:?}, hsikeron: {=bool:?}, hsidiv: {:?}, hsidivf: {=bool:?}, csion: {=bool:?}, csirdy: {=bool:?}, csikeron: {=bool:?}, hsi48on: {=bool:?}, hsi48rdy: {=bool:?}, hseon: {=bool:?}, hserdy: {=bool:?}, hsebyp: {=bool:?}, hsecsson: {=bool:?}, hseext: {:?}, pllon[0]: {=bool:?}, pllon[1]: {=bool:?}, pllon[2]: {=bool:?}, pllrdy[0]: {=bool:?}, pllrdy[1]: {=bool:?}, pllrdy[2]: {=bool:?} }}" , self . hsion () , self . hsirdy () , self . hsikeron () , self . hsidiv () , self . hsidivf () , self . csion () , self . csirdy () , self . csikeron () , self . hsi48on () , self . hsi48rdy () , self . hseon () , self . hserdy () , self . hsebyp () , self . hsecsson () , self . hseext () , self . pllon (0usize) , self . pllon (1usize) , self . pllon (2usize) , self . pllrdy (0usize) , self . pllrdy (1usize) , self . pllrdy (2usize))
}
}
#[doc = "RCC clock recovery RC register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Crrcr(pub u32);
impl Crrcr {
#[doc = "Internal RC 48 MHz clock calibration Set by hardware by option-byte loading during system reset NRESET. Read-only."]
#[inline(always)]
pub const fn hsi48cal(&self) -> u16 {
let val = (self.0 >> 0usize) & 0x03ff;
val as u16
}
#[doc = "Internal RC 48 MHz clock calibration Set by hardware by option-byte loading during system reset NRESET. Read-only."]
#[inline(always)]
pub fn set_hsi48cal(&mut self, val: u16) {
self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
}
}
impl Default for Crrcr {
#[inline(always)]
fn default() -> Crrcr {
Crrcr(0)
}
}
impl core::fmt::Debug for Crrcr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Crrcr").field("hsi48cal", &self.hsi48cal()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Crrcr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Crrcr {{ hsi48cal: {=u16:?} }}", self.hsi48cal())
}
}
#[doc = "RCC CSI calibration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csicfgr(pub u32);
impl Csicfgr {
#[doc = "CSI clock calibration Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value."]
#[inline(always)]
pub const fn csical(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[doc = "CSI clock calibration Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value."]
#[inline(always)]
pub fn set_csical(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
#[doc = "CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_OPT. Note: The reset value of the field is 0x20."]
#[inline(always)]
pub const fn csitrim(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x3f;
val as u8
}
#[doc = "CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_OPT. Note: The reset value of the field is 0x20."]
#[inline(always)]
pub fn set_csitrim(&mut self, val: u8) {
self.0 = (self.0 & !(0x3f << 16usize)) | (((val as u32) & 0x3f) << 16usize);
}
}
impl Default for Csicfgr {
#[inline(always)]
fn default() -> Csicfgr {
Csicfgr(0)
}
}
impl core::fmt::Debug for Csicfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Csicfgr")
.field("csical", &self.csical())
.field("csitrim", &self.csitrim())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Csicfgr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Csicfgr {{ csical: {=u8:?}, csitrim: {=u8:?} }}",
self.csical(),
self.csitrim()
)
}
}
#[doc = "RCC HSI calibration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Hsicfgr(pub u32);
impl Hsicfgr {
#[doc = "HSI clock calibration Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value."]
#[inline(always)]
pub const fn hsical(&self) -> u16 {
let val = (self.0 >> 0usize) & 0x0fff;
val as u16
}
#[doc = "HSI clock calibration Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value."]
#[inline(always)]
pub fn set_hsical(&mut self, val: u16) {
self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
}
#[doc = "HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_OPT. After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated Note: The reset value of the field is 0x40."]
#[inline(always)]
pub const fn hsitrim(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x7f;
val as u8
}
#[doc = "HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_OPT. After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated Note: The reset value of the field is 0x40."]
#[inline(always)]
pub fn set_hsitrim(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
}
}
impl Default for Hsicfgr {
#[inline(always)]
fn default() -> Hsicfgr {
Hsicfgr(0)
}
}
impl core::fmt::Debug for Hsicfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Hsicfgr")
.field("hsical", &self.hsical())
.field("hsitrim", &self.hsitrim())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Hsicfgr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Hsicfgr {{ hsical: {=u16:?}, hsitrim: {=u8:?} }}",
self.hsical(),
self.hsitrim()
)
}
}
#[doc = "RCC PLL clock source selection register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pllcfgr(pub u32);
impl Pllcfgr {
#[doc = "DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset)."]
#[inline(always)]
pub const fn pllsrc(&self) -> super::vals::Pllsrc {
let val = (self.0 >> 0usize) & 0x03;
super::vals::Pllsrc::from_bits(val as u8)
}
#[doc = "DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset)."]
#[inline(always)]
pub fn set_pllsrc(&mut self, val: super::vals::Pllsrc) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1."]
#[inline(always)]
pub const fn pllrge(&self) -> super::vals::Pllrge {
let val = (self.0 >> 2usize) & 0x03;
super::vals::Pllrge::from_bits(val as u8)
}
#[doc = "PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1."]
#[inline(always)]
pub fn set_pllrge(&mut self, val: super::vals::Pllrge) {
self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
}
#[doc = "PLL1 fractional latch enable Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator. In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator."]
#[inline(always)]
pub const fn pllfracen(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "PLL1 fractional latch enable Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator. In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator."]
#[inline(always)]
pub fn set_pllfracen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1."]
#[inline(always)]
pub const fn pllvcosel(&self) -> super::vals::Pllvcosel {
let val = (self.0 >> 5usize) & 0x01;
super::vals::Pllvcosel::from_bits(val as u8)
}
#[doc = "PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1."]
#[inline(always)]
pub fn set_pllvcosel(&mut self, val: super::vals::Pllvcosel) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize);
}
#[doc = "prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ..."]
#[inline(always)]
pub const fn divm(&self) -> super::vals::Pllm {
let val = (self.0 >> 8usize) & 0x3f;
super::vals::Pllm::from_bits(val as u8)
}
#[doc = "prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ..."]
#[inline(always)]
pub fn set_divm(&mut self, val: super::vals::Pllm) {
self.0 = (self.0 & !(0x3f << 8usize)) | (((val.to_bits() as u32) & 0x3f) << 8usize);
}
#[doc = "PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled."]
#[inline(always)]
pub const fn pllpen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled."]
#[inline(always)]
pub fn set_pllpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)."]
#[inline(always)]
pub const fn pllqen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)."]
#[inline(always)]
pub fn set_pllqen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)."]
#[inline(always)]
pub const fn pllren(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)."]
#[inline(always)]
pub fn set_pllren(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for Pllcfgr {
#[inline(always)]
fn default() -> Pllcfgr {
Pllcfgr(0)
}
}
impl core::fmt::Debug for Pllcfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pllcfgr")
.field("pllsrc", &self.pllsrc())
.field("pllrge", &self.pllrge())
.field("pllfracen", &self.pllfracen())
.field("pllvcosel", &self.pllvcosel())
.field("divm", &self.divm())
.field("pllpen", &self.pllpen())
.field("pllqen", &self.pllqen())
.field("pllren", &self.pllren())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pllcfgr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Pllcfgr {{ pllsrc: {:?}, pllrge: {:?}, pllfracen: {=bool:?}, pllvcosel: {:?}, divm: {:?}, pllpen: {=bool:?}, pllqen: {=bool:?}, pllren: {=bool:?} }}" , self . pllsrc () , self . pllrge () , self . pllfracen () , self . pllvcosel () , self . divm () , self . pllpen () , self . pllqen () , self . pllren ())
}
}
#[doc = "RCC PLL1 dividers register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Plldivr(pub u32);
impl Plldivr {
#[doc = "Multiplication factor for PLL1VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved"]
#[inline(always)]
pub const fn plln(&self) -> super::vals::Plln {
let val = (self.0 >> 0usize) & 0x01ff;
super::vals::Plln::from_bits(val as u16)
}
#[doc = "Multiplication factor for PLL1VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved"]
#[inline(always)]
pub fn set_plln(&mut self, val: super::vals::Plln) {
self.0 = (self.0 & !(0x01ff << 0usize)) | (((val.to_bits() as u32) & 0x01ff) << 0usize);
}
#[doc = "PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ..."]
#[inline(always)]
pub const fn pllp(&self) -> super::vals::Plldiv {
let val = (self.0 >> 9usize) & 0x7f;
super::vals::Plldiv::from_bits(val as u8)
}
#[doc = "PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ..."]
#[inline(always)]
pub fn set_pllp(&mut self, val: super::vals::Plldiv) {
self.0 = (self.0 & !(0x7f << 9usize)) | (((val.to_bits() as u32) & 0x7f) << 9usize);
}
#[doc = "PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ..."]
#[inline(always)]
pub const fn pllq(&self) -> super::vals::Plldiv {
let val = (self.0 >> 16usize) & 0x7f;
super::vals::Plldiv::from_bits(val as u8)
}
#[doc = "PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ..."]
#[inline(always)]
pub fn set_pllq(&mut self, val: super::vals::Plldiv) {
self.0 = (self.0 & !(0x7f << 16usize)) | (((val.to_bits() as u32) & 0x7f) << 16usize);
}
#[doc = "PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ..."]
#[inline(always)]
pub const fn pllr(&self) -> super::vals::Plldiv {
let val = (self.0 >> 24usize) & 0x7f;
super::vals::Plldiv::from_bits(val as u8)
}
#[doc = "PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ..."]
#[inline(always)]
pub fn set_pllr(&mut self, val: super::vals::Plldiv) {
self.0 = (self.0 & !(0x7f << 24usize)) | (((val.to_bits() as u32) & 0x7f) << 24usize);
}
}
impl Default for Plldivr {
#[inline(always)]
fn default() -> Plldivr {
Plldivr(0)
}
}
impl core::fmt::Debug for Plldivr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Plldivr")
.field("plln", &self.plln())
.field("pllp", &self.pllp())
.field("pllq", &self.pllq())
.field("pllr", &self.pllr())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Plldivr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Plldivr {{ plln: {:?}, pllp: {:?}, pllq: {:?}, pllr: {:?} }}",
self.plln(),
self.pllp(),
self.pllq(),
self.pllr()
)
}
}
#[doc = "RCC PLL1 fractional divider register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pllfracr(pub u32);
impl Pllfracr {
#[doc = "fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: * 128 to 560 MHz if PLL1VCOSEL = 0 * 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with * PLL1N between 8 and 420 * PLL1FRACN can be between 0 and 213- 1 * The input frequency Fref1_ck must be between 1 and 16 MHz. To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: * Set the bit PLL1FRACEN to 0 * Write the new fractional value into PLL1FRACN * Set the bit PLL1FRACEN to 1"]
#[inline(always)]
pub const fn pllfracn(&self) -> u16 {
let val = (self.0 >> 3usize) & 0x1fff;
val as u16
}
#[doc = "fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: * 128 to 560 MHz if PLL1VCOSEL = 0 * 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with * PLL1N between 8 and 420 * PLL1FRACN can be between 0 and 213- 1 * The input frequency Fref1_ck must be between 1 and 16 MHz. To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: * Set the bit PLL1FRACEN to 0 * Write the new fractional value into PLL1FRACN * Set the bit PLL1FRACEN to 1"]
#[inline(always)]
pub fn set_pllfracn(&mut self, val: u16) {
self.0 = (self.0 & !(0x1fff << 3usize)) | (((val as u32) & 0x1fff) << 3usize);
}
}
impl Default for Pllfracr {
#[inline(always)]
fn default() -> Pllfracr {
Pllfracr(0)
}
}
impl core::fmt::Debug for Pllfracr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pllfracr").field("pllfracn", &self.pllfracn()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pllfracr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Pllfracr {{ pllfracn: {=u16:?} }}", self.pllfracn())
}
}
#[doc = "RCC privilege configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Privcfgr(pub u32);
impl Privcfgr {
#[doc = "RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access."]
#[inline(always)]
pub const fn spriv(&self) -> super::vals::Spriv {
let val = (self.0 >> 0usize) & 0x01;
super::vals::Spriv::from_bits(val as u8)
}
#[doc = "RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access."]
#[inline(always)]
pub fn set_spriv(&mut self, val: super::vals::Spriv) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
}
#[doc = "RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure."]
#[inline(always)]
pub const fn nspriv(&self) -> super::vals::Nspriv {
let val = (self.0 >> 1usize) & 0x01;
super::vals::Nspriv::from_bits(val as u8)
}
#[doc = "RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure."]
#[inline(always)]
pub fn set_nspriv(&mut self, val: super::vals::Nspriv) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize);
}
}
impl Default for Privcfgr {
#[inline(always)]
fn default() -> Privcfgr {
Privcfgr(0)
}
}
impl core::fmt::Debug for Privcfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Privcfgr")
.field("spriv", &self.spriv())
.field("nspriv", &self.nspriv())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Privcfgr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Privcfgr {{ spriv: {:?}, nspriv: {:?} }}",
self.spriv(),
self.nspriv()
)
}
}
#[doc = "RCC reset status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Rsr(pub u32);
impl Rsr {
#[doc = "remove reset flag Set and reset by software to reset the value of the reset flags."]
#[inline(always)]
pub const fn rmvf(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "remove reset flag Set and reset by software to reset the value of the reset flags."]
#[inline(always)]
pub fn set_rmvf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "pin reset flag (NRST) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs."]
#[inline(always)]
pub const fn pinrstf(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "pin reset flag (NRST) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs."]
#[inline(always)]
pub fn set_pinrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "BOR reset flag Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst)."]
#[inline(always)]
pub const fn borrstf(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "BOR reset flag Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst)."]
#[inline(always)]
pub fn set_borrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "system reset from CPU reset flag Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33."]
#[inline(always)]
pub const fn sftrstf(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "system reset from CPU reset flag Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33."]
#[inline(always)]
pub fn set_sftrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "independent watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs."]
#[inline(always)]
pub const fn iwdgrstf(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "independent watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs."]
#[inline(always)]
pub fn set_iwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "window watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs."]
#[inline(always)]
pub const fn wwdgrstf(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "window watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs."]
#[inline(always)]
pub fn set_wwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "Low-power reset flag Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared. Cleared by writing to the RMVF bit."]
#[inline(always)]
pub const fn lpwrrstf(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Low-power reset flag Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared. Cleared by writing to the RMVF bit."]
#[inline(always)]
pub fn set_lpwrrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Rsr {
#[inline(always)]
fn default() -> Rsr {
Rsr(0)
}
}
impl core::fmt::Debug for Rsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Rsr")
.field("rmvf", &self.rmvf())
.field("pinrstf", &self.pinrstf())
.field("borrstf", &self.borrstf())
.field("sftrstf", &self.sftrstf())
.field("iwdgrstf", &self.iwdgrstf())
.field("wwdgrstf", &self.wwdgrstf())
.field("lpwrrstf", &self.lpwrrstf())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Rsr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Rsr {{ rmvf: {=bool:?}, pinrstf: {=bool:?}, borrstf: {=bool:?}, sftrstf: {=bool:?}, iwdgrstf: {=bool:?}, wwdgrstf: {=bool:?}, lpwrrstf: {=bool:?} }}" , self . rmvf () , self . pinrstf () , self . borrstf () , self . sftrstf () , self . iwdgrstf () , self . wwdgrstf () , self . lpwrrstf ())
}
}
#[doc = "RCC secure configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Seccfgr(pub u32);
impl Seccfgr {
#[doc = "HSI clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub const fn hsisec(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "HSI clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub fn set_hsisec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "HSE clock configuration bits, status bits and HSE_CSS security Set and reset by software."]
#[inline(always)]
pub const fn hsesec(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "HSE clock configuration bits, status bits and HSE_CSS security Set and reset by software."]
#[inline(always)]
pub fn set_hsesec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "CSI clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub const fn csisec(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "CSI clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub fn set_csisec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "LSI clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub const fn lsisec(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "LSI clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub fn set_lsisec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "LSE clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub const fn lsesec(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "LSE clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub fn set_lsesec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security Set and reset by software."]
#[inline(always)]
pub const fn sysclksec(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security Set and reset by software."]
#[inline(always)]
pub fn set_sysclksec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "AHBx/APBx prescaler configuration bits security Set and reset by software."]
#[inline(always)]
pub const fn prescsec(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "AHBx/APBx prescaler configuration bits security Set and reset by software."]
#[inline(always)]
pub fn set_prescsec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "PLL1 clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub const fn pllsec(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 7usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "PLL1 clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub fn set_pllsec(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 7usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "HSI48 clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub const fn hsi48sec(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "HSI48 clock configuration and status bits security Set and reset by software."]
#[inline(always)]
pub fn set_hsi48sec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "Remove reset flag security Set and reset by software."]
#[inline(always)]
pub const fn rmvfsec(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "Remove reset flag security Set and reset by software."]
#[inline(always)]
pub fn set_rmvfsec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "per_ck selection security Set and reset by software."]
#[inline(always)]
pub const fn perselsec(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "per_ck selection security Set and reset by software."]
#[inline(always)]
pub fn set_perselsec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
}
impl Default for Seccfgr {
#[inline(always)]
fn default() -> Seccfgr {
Seccfgr(0)
}
}
impl core::fmt::Debug for Seccfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Seccfgr")
.field("hsisec", &self.hsisec())
.field("hsesec", &self.hsesec())
.field("csisec", &self.csisec())
.field("lsisec", &self.lsisec())
.field("lsesec", &self.lsesec())
.field("sysclksec", &self.sysclksec())
.field("prescsec", &self.prescsec())
.field("pllsec[0]", &self.pllsec(0usize))
.field("pllsec[1]", &self.pllsec(1usize))
.field("pllsec[2]", &self.pllsec(2usize))
.field("hsi48sec", &self.hsi48sec())
.field("rmvfsec", &self.rmvfsec())
.field("perselsec", &self.perselsec())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Seccfgr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Seccfgr {{ hsisec: {=bool:?}, hsesec: {=bool:?}, csisec: {=bool:?}, lsisec: {=bool:?}, lsesec: {=bool:?}, sysclksec: {=bool:?}, prescsec: {=bool:?}, pllsec[0]: {=bool:?}, pllsec[1]: {=bool:?}, pllsec[2]: {=bool:?}, hsi48sec: {=bool:?}, rmvfsec: {=bool:?}, perselsec: {=bool:?} }}" , self . hsisec () , self . hsesec () , self . csisec () , self . lsisec () , self . lsesec () , self . sysclksec () , self . prescsec () , self . pllsec (0usize) , self . pllsec (1usize) , self . pllsec (2usize) , self . hsi48sec () , self . rmvfsec () , self . perselsec ())
}
}
}
pub mod vals {
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Adcdacsel {
#[doc = "rcc_hclk selected as kernel clock (default after reset)"]
HCLK2 = 0x0,
#[doc = "sys_ck selected as kernel clock"]
SYS = 0x01,
#[doc = "pll2_r_ck selected as kernel clock"]
PLL2_R = 0x02,
#[doc = "hse_ck selected as kernel clock"]
HSE = 0x03,
#[doc = "hsi_ker_ck selected as kernel clock"]
HSI = 0x04,
#[doc = "csi_ker_ck selected as kernel clock"]
CSI = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Adcdacsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Adcdacsel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Adcdacsel {
#[inline(always)]
fn from(val: u8) -> Adcdacsel {
Adcdacsel::from_bits(val)
}
}
impl From<Adcdacsel> for u8 {
#[inline(always)]
fn from(val: Adcdacsel) -> u8 {
Adcdacsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Cecsel {
#[doc = "lse_ck selected as kernel clock (default after reset)"]
LSE = 0x0,
#[doc = "lsi_ker_ck selected as kernel clock"]
LSI = 0x01,
#[doc = "csi_ker_ck/122 selected as kernel clock"]
CSI_DIV_122 = 0x02,
_RESERVED_3 = 0x03,
}
impl Cecsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Cecsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Cecsel {
#[inline(always)]
fn from(val: u8) -> Cecsel {
Cecsel::from_bits(val)
}
}
impl From<Cecsel> for u8 {
#[inline(always)]
fn from(val: Cecsel) -> u8 {
Cecsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Dacholdsel {
#[doc = "dac_hold_ck selected as kernel clock (default after reset)"]
DAC_HOLD = 0x0,
#[doc = "dac_hold_ck selected as kernel clock"]
DAC_HOLD_2 = 0x01,
}
impl Dacholdsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Dacholdsel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Dacholdsel {
#[inline(always)]
fn from(val: u8) -> Dacholdsel {
Dacholdsel::from_bits(val)
}
}
impl From<Dacholdsel> for u8 {
#[inline(always)]
fn from(val: Dacholdsel) -> u8 {
Dacholdsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Fdcansel {
#[doc = "hse_ck selected as kernel clock (default after reset)"]
HSE = 0x0,
#[doc = "pll1_q_ck selected as kernel clock"]
PLL1_Q = 0x01,
#[doc = "pll2_q_ck selected as kernel clock"]
PLL2_Q = 0x02,
_RESERVED_3 = 0x03,
}
impl Fdcansel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Fdcansel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Fdcansel {
#[inline(always)]
fn from(val: u8) -> Fdcansel {
Fdcansel::from_bits(val)
}
}
impl From<Fdcansel> for u8 {
#[inline(always)]
fn from(val: Fdcansel) -> u8 {
Fdcansel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Hpre {
#[doc = "sys_ck not divided"]
DIV1 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
_RESERVED_3 = 0x03,
_RESERVED_4 = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
#[doc = "sys_ck divided by 2"]
DIV2 = 0x08,
#[doc = "sys_ck divided by 4"]
DIV4 = 0x09,
#[doc = "sys_ck divided by 8"]
DIV8 = 0x0a,
#[doc = "sys_ck divided by 16"]
DIV16 = 0x0b,
#[doc = "sys_ck divided by 64"]
DIV64 = 0x0c,
#[doc = "sys_ck divided by 128"]
DIV128 = 0x0d,
#[doc = "sys_ck divided by 256"]
DIV256 = 0x0e,
#[doc = "sys_ck divided by 512"]
DIV512 = 0x0f,
}
impl Hpre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Hpre {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Hpre {
#[inline(always)]
fn from(val: u8) -> Hpre {
Hpre::from_bits(val)
}
}
impl From<Hpre> for u8 {
#[inline(always)]
fn from(val: Hpre) -> u8 {
Hpre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Hseext {
#[doc = "HSE in analog mode (default after reset)"]
ANALOG = 0x0,
#[doc = "HSE in digital mode"]
DIGITAL = 0x01,
}
impl Hseext {
#[inline(always)]
pub const fn from_bits(val: u8) -> Hseext {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Hseext {
#[inline(always)]
fn from(val: u8) -> Hseext {
Hseext::from_bits(val)
}
}
impl From<Hseext> for u8 {
#[inline(always)]
fn from(val: Hseext) -> u8 {
Hseext::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Hsidiv {
#[doc = "No division"]
DIV1 = 0x0,
#[doc = "Division by 2"]
DIV2 = 0x01,
#[doc = "Division by 4"]
DIV4 = 0x02,
#[doc = "Division by 8"]
DIV8 = 0x03,
}
impl Hsidiv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Hsidiv {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Hsidiv {
#[inline(always)]
fn from(val: u8) -> Hsidiv {
Hsidiv::from_bits(val)
}
}
impl From<Hsidiv> for u8 {
#[inline(always)]
fn from(val: Hsidiv) -> u8 {
Hsidiv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum I2c34sel {
#[doc = "rcc_pclk3 selected as peripheral clock"]
PCLK3 = 0x0,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R = 0x01,
#[doc = "hsi_ker selected as peripheral clock"]
HSI = 0x02,
#[doc = "csi_ker selected as peripheral clock"]
CSI = 0x03,
}
impl I2c34sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> I2c34sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for I2c34sel {
#[inline(always)]
fn from(val: u8) -> I2c34sel {
I2c34sel::from_bits(val)
}
}
impl From<I2c34sel> for u8 {
#[inline(always)]
fn from(val: I2c34sel) -> u8 {
I2c34sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum I2csel {
#[doc = "rcc_pclk1 selected as peripheral clock"]
PCLK1 = 0x0,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R = 0x01,
#[doc = "hsi_ker selected as peripheral clock"]
HSI = 0x02,
#[doc = "csi_ker selected as peripheral clock"]
CSI = 0x03,
}
impl I2csel {
#[inline(always)]
pub const fn from_bits(val: u8) -> I2csel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for I2csel {
#[inline(always)]
fn from(val: u8) -> I2csel {
I2csel::from_bits(val)
}
}
impl From<I2csel> for u8 {
#[inline(always)]
fn from(val: I2csel) -> u8 {
I2csel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lptim2sel {
#[doc = "rcc_pclk1 selected as peripheral clock"]
PCLK1 = 0x0,
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P = 0x01,
_RESERVED_2 = 0x02,
#[doc = "LSE selected as peripheral clock"]
LSE = 0x03,
#[doc = "LSI selected as peripheral clock"]
LSI = 0x04,
#[doc = "PER selected as peripheral clock"]
PER = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Lptim2sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lptim2sel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lptim2sel {
#[inline(always)]
fn from(val: u8) -> Lptim2sel {
Lptim2sel::from_bits(val)
}
}
impl From<Lptim2sel> for u8 {
#[inline(always)]
fn from(val: Lptim2sel) -> u8 {
Lptim2sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lptimsel {
#[doc = "rcc_pclk3 selected as peripheral clock"]
PCLK3 = 0x0,
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P = 0x01,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R = 0x02,
#[doc = "LSE selected as peripheral clock"]
LSE = 0x03,
#[doc = "LSI selected as peripheral clock"]
LSI = 0x04,
#[doc = "PER selected as peripheral clock"]
PER = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Lptimsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lptimsel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lptimsel {
#[inline(always)]
fn from(val: u8) -> Lptimsel {
Lptimsel::from_bits(val)
}
}
impl From<Lptimsel> for u8 {
#[inline(always)]
fn from(val: Lptimsel) -> u8 {
Lptimsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lpusartsel {
#[doc = "rcc_pclk3 selected as kernel clock (default after reset)"]
PCLK3 = 0x0,
#[doc = "pll2_q_ck selected as kernel clock"]
PLL2_Q = 0x01,
#[doc = "pll3_q_ck selected as kernel clock"]
PLL3_Q = 0x02,
#[doc = "hsi_ker_ck selected as kernel clock"]
HSI = 0x03,
#[doc = "csi_ker_ck selected as kernel clock"]
CSI = 0x04,
#[doc = "lse_ck selected as kernel clock"]
LSE = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Lpusartsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lpusartsel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lpusartsel {
#[inline(always)]
fn from(val: u8) -> Lpusartsel {
Lpusartsel::from_bits(val)
}
}
impl From<Lpusartsel> for u8 {
#[inline(always)]
fn from(val: Lpusartsel) -> u8 {
Lpusartsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lscosel {
#[doc = "LSI clock selected"]
LSI = 0x0,
#[doc = "LSE clock selected"]
LSE = 0x01,
}
impl Lscosel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lscosel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lscosel {
#[inline(always)]
fn from(val: u8) -> Lscosel {
Lscosel::from_bits(val)
}
}
impl From<Lscosel> for u8 {
#[inline(always)]
fn from(val: Lscosel) -> u8 {
Lscosel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lsedrv {
#[doc = "Low driving capability"]
LOW = 0x0,
#[doc = "Medium low driving capability"]
MEDIUM_LOW = 0x01,
#[doc = "Medium high driving capability"]
MEDIUM_HIGH = 0x02,
#[doc = "High driving capability"]
HIGH = 0x03,
}
impl Lsedrv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lsedrv {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lsedrv {
#[inline(always)]
fn from(val: u8) -> Lsedrv {
Lsedrv::from_bits(val)
}
}
impl From<Lsedrv> for u8 {
#[inline(always)]
fn from(val: Lsedrv) -> u8 {
Lsedrv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lseext {
#[doc = "LSE in analog mode (default after Backup domain reset)"]
ANALOG = 0x0,
#[doc = "LSE in digital mode (do not use if RTC is active)."]
DIGITAL = 0x01,
}
impl Lseext {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lseext {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lseext {
#[inline(always)]
fn from(val: u8) -> Lseext {
Lseext::from_bits(val)
}
}
impl From<Lseext> for u8 {
#[inline(always)]
fn from(val: Lseext) -> u8 {
Lseext::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Mco1sel {
#[doc = "HSI selected for micro-controller clock output"]
HSI = 0x0,
#[doc = "LSE selected for micro-controller clock output"]
LSE = 0x01,
#[doc = "HSE selected for micro-controller clock output"]
HSE = 0x02,
#[doc = "pll1_q selected for micro-controller clock output"]
PLL1_Q = 0x03,
#[doc = "HSI48 selected for micro-controller clock output"]
HSI48 = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Mco1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Mco1sel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Mco1sel {
#[inline(always)]
fn from(val: u8) -> Mco1sel {
Mco1sel::from_bits(val)
}
}
impl From<Mco1sel> for u8 {
#[inline(always)]
fn from(val: Mco1sel) -> u8 {
Mco1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Mco2sel {
#[doc = "System clock selected for micro-controller clock output"]
SYS = 0x0,
#[doc = "pll2_p selected for micro-controller clock output"]
PLL2_P = 0x01,
#[doc = "HSE selected for micro-controller clock output"]
HSE = 0x02,
#[doc = "pll1_p selected for micro-controller clock output"]
PLL1_P = 0x03,
#[doc = "CSI selected for micro-controller clock output"]
CSI = 0x04,
#[doc = "LSI selected for micro-controller clock output"]
LSI = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Mco2sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Mco2sel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Mco2sel {
#[inline(always)]
fn from(val: u8) -> Mco2sel {
Mco2sel::from_bits(val)
}
}
impl From<Mco2sel> for u8 {
#[inline(always)]
fn from(val: Mco2sel) -> u8 {
Mco2sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Mcopre {
_RESERVED_0 = 0x0,
#[doc = "Divide by 1"]
DIV1 = 0x01,
#[doc = "Divide by 2"]
DIV2 = 0x02,
#[doc = "Divide by 3"]
DIV3 = 0x03,
#[doc = "Divide by 4"]
DIV4 = 0x04,
#[doc = "Divide by 5"]
DIV5 = 0x05,
#[doc = "Divide by 6"]
DIV6 = 0x06,
#[doc = "Divide by 7"]
DIV7 = 0x07,
#[doc = "Divide by 8"]
DIV8 = 0x08,
#[doc = "Divide by 9"]
DIV9 = 0x09,
#[doc = "Divide by 10"]
DIV10 = 0x0a,
#[doc = "Divide by 11"]
DIV11 = 0x0b,
#[doc = "Divide by 12"]
DIV12 = 0x0c,
#[doc = "Divide by 13"]
DIV13 = 0x0d,
#[doc = "Divide by 14"]
DIV14 = 0x0e,
#[doc = "Divide by 15"]
DIV15 = 0x0f,
}
impl Mcopre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Mcopre {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Mcopre {
#[inline(always)]
fn from(val: u8) -> Mcopre {
Mcopre::from_bits(val)
}
}
impl From<Mcopre> for u8 {
#[inline(always)]
fn from(val: Mcopre) -> u8 {
Mcopre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Nspriv {
#[doc = "Read and write to RCC non-secure functions can be done by privileged or unprivileged access."]
B_0X0 = 0x0,
#[doc = "Read and write to RCC non-secure functions can be done by privileged access only"]
B_0X1 = 0x01,
}
impl Nspriv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Nspriv {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Nspriv {
#[inline(always)]
fn from(val: u8) -> Nspriv {
Nspriv::from_bits(val)
}
}
impl From<Nspriv> for u8 {
#[inline(always)]
fn from(val: Nspriv) -> u8 {
Nspriv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Octospisel {
#[doc = "rcc_hclk selected as kernel clock (default after reset)"]
HCLK4 = 0x0,
#[doc = "pll1_q_ck selected as kernel clock"]
PLL1_Q = 0x01,
#[doc = "pll2_r_ck selected as kernel clock"]
PLL2_R = 0x02,
#[doc = "per_ck selected as kernel clock"]
PER = 0x03,
}
impl Octospisel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Octospisel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Octospisel {
#[inline(always)]
fn from(val: u8) -> Octospisel {
Octospisel::from_bits(val)
}
}
impl From<Octospisel> for u8 {
#[inline(always)]
fn from(val: Octospisel) -> u8 {
Octospisel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Persel {
#[doc = "hsi_ker_ck selected as kernel clock (default after reset)"]
HSI = 0x0,
#[doc = "csi_ker_ck selected as kernel clock"]
CSI = 0x01,
#[doc = "hse_ck selected as kernel clock"]
HSE = 0x02,
_RESERVED_3 = 0x03,
}
impl Persel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Persel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Persel {
#[inline(always)]
fn from(val: u8) -> Persel {
Persel::from_bits(val)
}
}
impl From<Persel> for u8 {
#[inline(always)]
fn from(val: Persel) -> u8 {
Persel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Plldiv {
DIV1 = 0x0,
DIV2 = 0x01,
DIV3 = 0x02,
DIV4 = 0x03,
DIV5 = 0x04,
DIV6 = 0x05,
DIV7 = 0x06,
DIV8 = 0x07,
DIV9 = 0x08,
DIV10 = 0x09,
DIV11 = 0x0a,
DIV12 = 0x0b,
DIV13 = 0x0c,
DIV14 = 0x0d,
DIV15 = 0x0e,
DIV16 = 0x0f,
DIV17 = 0x10,
DIV18 = 0x11,
DIV19 = 0x12,
DIV20 = 0x13,
DIV21 = 0x14,
DIV22 = 0x15,
DIV23 = 0x16,
DIV24 = 0x17,
DIV25 = 0x18,
DIV26 = 0x19,
DIV27 = 0x1a,
DIV28 = 0x1b,
DIV29 = 0x1c,
DIV30 = 0x1d,
DIV31 = 0x1e,
DIV32 = 0x1f,
DIV33 = 0x20,
DIV34 = 0x21,
DIV35 = 0x22,
DIV36 = 0x23,
DIV37 = 0x24,
DIV38 = 0x25,
DIV39 = 0x26,
DIV40 = 0x27,
DIV41 = 0x28,
DIV42 = 0x29,
DIV43 = 0x2a,
DIV44 = 0x2b,
DIV45 = 0x2c,
DIV46 = 0x2d,
DIV47 = 0x2e,
DIV48 = 0x2f,
DIV49 = 0x30,
DIV50 = 0x31,
DIV51 = 0x32,
DIV52 = 0x33,
DIV53 = 0x34,
DIV54 = 0x35,
DIV55 = 0x36,
DIV56 = 0x37,
DIV57 = 0x38,
DIV58 = 0x39,
DIV59 = 0x3a,
DIV60 = 0x3b,
DIV61 = 0x3c,
DIV62 = 0x3d,
DIV63 = 0x3e,
DIV64 = 0x3f,
DIV65 = 0x40,
DIV66 = 0x41,
DIV67 = 0x42,
DIV68 = 0x43,
DIV69 = 0x44,
DIV70 = 0x45,
DIV71 = 0x46,
DIV72 = 0x47,
DIV73 = 0x48,
DIV74 = 0x49,
DIV75 = 0x4a,
DIV76 = 0x4b,
DIV77 = 0x4c,
DIV78 = 0x4d,
DIV79 = 0x4e,
DIV80 = 0x4f,
DIV81 = 0x50,
DIV82 = 0x51,
DIV83 = 0x52,
DIV84 = 0x53,
DIV85 = 0x54,
DIV86 = 0x55,
DIV87 = 0x56,
DIV88 = 0x57,
DIV89 = 0x58,
DIV90 = 0x59,
DIV91 = 0x5a,
DIV92 = 0x5b,
DIV93 = 0x5c,
DIV94 = 0x5d,
DIV95 = 0x5e,
DIV96 = 0x5f,
DIV97 = 0x60,
DIV98 = 0x61,
DIV99 = 0x62,
DIV100 = 0x63,
DIV101 = 0x64,
DIV102 = 0x65,
DIV103 = 0x66,
DIV104 = 0x67,
DIV105 = 0x68,
DIV106 = 0x69,
DIV107 = 0x6a,
DIV108 = 0x6b,
DIV109 = 0x6c,
DIV110 = 0x6d,
DIV111 = 0x6e,
DIV112 = 0x6f,
DIV113 = 0x70,
DIV114 = 0x71,
DIV115 = 0x72,
DIV116 = 0x73,
DIV117 = 0x74,
DIV118 = 0x75,
DIV119 = 0x76,
DIV120 = 0x77,
DIV121 = 0x78,
DIV122 = 0x79,
DIV123 = 0x7a,
DIV124 = 0x7b,
DIV125 = 0x7c,
DIV126 = 0x7d,
DIV127 = 0x7e,
DIV128 = 0x7f,
}
impl Plldiv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Plldiv {
unsafe { core::mem::transmute(val & 0x7f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Plldiv {
#[inline(always)]
fn from(val: u8) -> Plldiv {
Plldiv::from_bits(val)
}
}
impl From<Plldiv> for u8 {
#[inline(always)]
fn from(val: Plldiv) -> u8 {
Plldiv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllm {
_RESERVED_0 = 0x0,
DIV1 = 0x01,
DIV2 = 0x02,
DIV3 = 0x03,
DIV4 = 0x04,
DIV5 = 0x05,
DIV6 = 0x06,
DIV7 = 0x07,
DIV8 = 0x08,
DIV9 = 0x09,
DIV10 = 0x0a,
DIV11 = 0x0b,
DIV12 = 0x0c,
DIV13 = 0x0d,
DIV14 = 0x0e,
DIV15 = 0x0f,
DIV16 = 0x10,
DIV17 = 0x11,
DIV18 = 0x12,
DIV19 = 0x13,
DIV20 = 0x14,
DIV21 = 0x15,
DIV22 = 0x16,
DIV23 = 0x17,
DIV24 = 0x18,
DIV25 = 0x19,
DIV26 = 0x1a,
DIV27 = 0x1b,
DIV28 = 0x1c,
DIV29 = 0x1d,
DIV30 = 0x1e,
DIV31 = 0x1f,
DIV32 = 0x20,
DIV33 = 0x21,
DIV34 = 0x22,
DIV35 = 0x23,
DIV36 = 0x24,
DIV37 = 0x25,
DIV38 = 0x26,
DIV39 = 0x27,
DIV40 = 0x28,
DIV41 = 0x29,
DIV42 = 0x2a,
DIV43 = 0x2b,
DIV44 = 0x2c,
DIV45 = 0x2d,
DIV46 = 0x2e,
DIV47 = 0x2f,
DIV48 = 0x30,
DIV49 = 0x31,
DIV50 = 0x32,
DIV51 = 0x33,
DIV52 = 0x34,
DIV53 = 0x35,
DIV54 = 0x36,
DIV55 = 0x37,
DIV56 = 0x38,
DIV57 = 0x39,
DIV58 = 0x3a,
DIV59 = 0x3b,
DIV60 = 0x3c,
DIV61 = 0x3d,
DIV62 = 0x3e,
_RESERVED_3f = 0x3f,
}
impl Pllm {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllm {
unsafe { core::mem::transmute(val & 0x3f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllm {
#[inline(always)]
fn from(val: u8) -> Pllm {
Pllm::from_bits(val)
}
}
impl From<Pllm> for u8 {
#[inline(always)]
fn from(val: Pllm) -> u8 {
Pllm::to_bits(val)
}
}
#[repr(u16)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Plln {
_RESERVED_0 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
MUL4 = 0x03,
MUL5 = 0x04,
MUL6 = 0x05,
MUL7 = 0x06,
MUL8 = 0x07,
MUL9 = 0x08,
MUL10 = 0x09,
MUL11 = 0x0a,
MUL12 = 0x0b,
MUL13 = 0x0c,
MUL14 = 0x0d,
MUL15 = 0x0e,
MUL16 = 0x0f,
MUL17 = 0x10,
MUL18 = 0x11,
MUL19 = 0x12,
MUL20 = 0x13,
MUL21 = 0x14,
MUL22 = 0x15,
MUL23 = 0x16,
MUL24 = 0x17,
MUL25 = 0x18,
MUL26 = 0x19,
MUL27 = 0x1a,
MUL28 = 0x1b,
MUL29 = 0x1c,
MUL30 = 0x1d,
MUL31 = 0x1e,
MUL32 = 0x1f,
MUL33 = 0x20,
MUL34 = 0x21,
MUL35 = 0x22,
MUL36 = 0x23,
MUL37 = 0x24,
MUL38 = 0x25,
MUL39 = 0x26,
MUL40 = 0x27,
MUL41 = 0x28,
MUL42 = 0x29,
MUL43 = 0x2a,
MUL44 = 0x2b,
MUL45 = 0x2c,
MUL46 = 0x2d,
MUL47 = 0x2e,
MUL48 = 0x2f,
MUL49 = 0x30,
MUL50 = 0x31,
MUL51 = 0x32,
MUL52 = 0x33,
MUL53 = 0x34,
MUL54 = 0x35,
MUL55 = 0x36,
MUL56 = 0x37,
MUL57 = 0x38,
MUL58 = 0x39,
MUL59 = 0x3a,
MUL60 = 0x3b,
MUL61 = 0x3c,
MUL62 = 0x3d,
MUL63 = 0x3e,
MUL64 = 0x3f,
MUL65 = 0x40,
MUL66 = 0x41,
MUL67 = 0x42,
MUL68 = 0x43,
MUL69 = 0x44,
MUL70 = 0x45,
MUL71 = 0x46,
MUL72 = 0x47,
MUL73 = 0x48,
MUL74 = 0x49,
MUL75 = 0x4a,
MUL76 = 0x4b,
MUL77 = 0x4c,
MUL78 = 0x4d,
MUL79 = 0x4e,
MUL80 = 0x4f,
MUL81 = 0x50,
MUL82 = 0x51,
MUL83 = 0x52,
MUL84 = 0x53,
MUL85 = 0x54,
MUL86 = 0x55,
MUL87 = 0x56,
MUL88 = 0x57,
MUL89 = 0x58,
MUL90 = 0x59,
MUL91 = 0x5a,
MUL92 = 0x5b,
MUL93 = 0x5c,
MUL94 = 0x5d,
MUL95 = 0x5e,
MUL96 = 0x5f,
MUL97 = 0x60,
MUL98 = 0x61,
MUL99 = 0x62,
MUL100 = 0x63,
MUL101 = 0x64,
MUL102 = 0x65,
MUL103 = 0x66,
MUL104 = 0x67,
MUL105 = 0x68,
MUL106 = 0x69,
MUL107 = 0x6a,
MUL108 = 0x6b,
MUL109 = 0x6c,
MUL110 = 0x6d,
MUL111 = 0x6e,
MUL112 = 0x6f,
MUL113 = 0x70,
MUL114 = 0x71,
MUL115 = 0x72,
MUL116 = 0x73,
MUL117 = 0x74,
MUL118 = 0x75,
MUL119 = 0x76,
MUL120 = 0x77,
MUL121 = 0x78,
MUL122 = 0x79,
MUL123 = 0x7a,
MUL124 = 0x7b,
MUL125 = 0x7c,
MUL126 = 0x7d,
MUL127 = 0x7e,
MUL128 = 0x7f,
MUL129 = 0x80,
MUL130 = 0x81,
MUL131 = 0x82,
MUL132 = 0x83,
MUL133 = 0x84,
MUL134 = 0x85,
MUL135 = 0x86,
MUL136 = 0x87,
MUL137 = 0x88,
MUL138 = 0x89,
MUL139 = 0x8a,
MUL140 = 0x8b,
MUL141 = 0x8c,
MUL142 = 0x8d,
MUL143 = 0x8e,
MUL144 = 0x8f,
MUL145 = 0x90,
MUL146 = 0x91,
MUL147 = 0x92,
MUL148 = 0x93,
MUL149 = 0x94,
MUL150 = 0x95,
MUL151 = 0x96,
MUL152 = 0x97,
MUL153 = 0x98,
MUL154 = 0x99,
MUL155 = 0x9a,
MUL156 = 0x9b,
MUL157 = 0x9c,
MUL158 = 0x9d,
MUL159 = 0x9e,
MUL160 = 0x9f,
MUL161 = 0xa0,
MUL162 = 0xa1,
MUL163 = 0xa2,
MUL164 = 0xa3,
MUL165 = 0xa4,
MUL166 = 0xa5,
MUL167 = 0xa6,
MUL168 = 0xa7,
MUL169 = 0xa8,
MUL170 = 0xa9,
MUL171 = 0xaa,
MUL172 = 0xab,
MUL173 = 0xac,
MUL174 = 0xad,
MUL175 = 0xae,
MUL176 = 0xaf,
MUL177 = 0xb0,
MUL178 = 0xb1,
MUL179 = 0xb2,
MUL180 = 0xb3,
MUL181 = 0xb4,
MUL182 = 0xb5,
MUL183 = 0xb6,
MUL184 = 0xb7,
MUL185 = 0xb8,
MUL186 = 0xb9,
MUL187 = 0xba,
MUL188 = 0xbb,
MUL189 = 0xbc,
MUL190 = 0xbd,
MUL191 = 0xbe,
MUL192 = 0xbf,
MUL193 = 0xc0,
MUL194 = 0xc1,
MUL195 = 0xc2,
MUL196 = 0xc3,
MUL197 = 0xc4,
MUL198 = 0xc5,
MUL199 = 0xc6,
MUL200 = 0xc7,
MUL201 = 0xc8,
MUL202 = 0xc9,
MUL203 = 0xca,
MUL204 = 0xcb,
MUL205 = 0xcc,
MUL206 = 0xcd,
MUL207 = 0xce,
MUL208 = 0xcf,
MUL209 = 0xd0,
MUL210 = 0xd1,
MUL211 = 0xd2,
MUL212 = 0xd3,
MUL213 = 0xd4,
MUL214 = 0xd5,
MUL215 = 0xd6,
MUL216 = 0xd7,
MUL217 = 0xd8,
MUL218 = 0xd9,
MUL219 = 0xda,
MUL220 = 0xdb,
MUL221 = 0xdc,
MUL222 = 0xdd,
MUL223 = 0xde,
MUL224 = 0xdf,
MUL225 = 0xe0,
MUL226 = 0xe1,
MUL227 = 0xe2,
MUL228 = 0xe3,
MUL229 = 0xe4,
MUL230 = 0xe5,
MUL231 = 0xe6,
MUL232 = 0xe7,
MUL233 = 0xe8,
MUL234 = 0xe9,
MUL235 = 0xea,
MUL236 = 0xeb,
MUL237 = 0xec,
MUL238 = 0xed,
MUL239 = 0xee,
MUL240 = 0xef,
MUL241 = 0xf0,
MUL242 = 0xf1,
MUL243 = 0xf2,
MUL244 = 0xf3,
MUL245 = 0xf4,
MUL246 = 0xf5,
MUL247 = 0xf6,
MUL248 = 0xf7,
MUL249 = 0xf8,
MUL250 = 0xf9,
MUL251 = 0xfa,
MUL252 = 0xfb,
MUL253 = 0xfc,
MUL254 = 0xfd,
MUL255 = 0xfe,
MUL256 = 0xff,
MUL257 = 0x0100,
MUL258 = 0x0101,
MUL259 = 0x0102,
MUL260 = 0x0103,
MUL261 = 0x0104,
MUL262 = 0x0105,
MUL263 = 0x0106,
MUL264 = 0x0107,
MUL265 = 0x0108,
MUL266 = 0x0109,
MUL267 = 0x010a,
MUL268 = 0x010b,
MUL269 = 0x010c,
MUL270 = 0x010d,
MUL271 = 0x010e,
MUL272 = 0x010f,
MUL273 = 0x0110,
MUL274 = 0x0111,
MUL275 = 0x0112,
MUL276 = 0x0113,
MUL277 = 0x0114,
MUL278 = 0x0115,
MUL279 = 0x0116,
MUL280 = 0x0117,
MUL281 = 0x0118,
MUL282 = 0x0119,
MUL283 = 0x011a,
MUL284 = 0x011b,
MUL285 = 0x011c,
MUL286 = 0x011d,
MUL287 = 0x011e,
MUL288 = 0x011f,
MUL289 = 0x0120,
MUL290 = 0x0121,
MUL291 = 0x0122,
MUL292 = 0x0123,
MUL293 = 0x0124,
MUL294 = 0x0125,
MUL295 = 0x0126,
MUL296 = 0x0127,
MUL297 = 0x0128,
MUL298 = 0x0129,
MUL299 = 0x012a,
MUL300 = 0x012b,
MUL301 = 0x012c,
MUL302 = 0x012d,
MUL303 = 0x012e,
MUL304 = 0x012f,
MUL305 = 0x0130,
MUL306 = 0x0131,
MUL307 = 0x0132,
MUL308 = 0x0133,
MUL309 = 0x0134,
MUL310 = 0x0135,
MUL311 = 0x0136,
MUL312 = 0x0137,
MUL313 = 0x0138,
MUL314 = 0x0139,
MUL315 = 0x013a,
MUL316 = 0x013b,
MUL317 = 0x013c,
MUL318 = 0x013d,
MUL319 = 0x013e,
MUL320 = 0x013f,
MUL321 = 0x0140,
MUL322 = 0x0141,
MUL323 = 0x0142,
MUL324 = 0x0143,
MUL325 = 0x0144,
MUL326 = 0x0145,
MUL327 = 0x0146,
MUL328 = 0x0147,
MUL329 = 0x0148,
MUL330 = 0x0149,
MUL331 = 0x014a,
MUL332 = 0x014b,
MUL333 = 0x014c,
MUL334 = 0x014d,
MUL335 = 0x014e,
MUL336 = 0x014f,
MUL337 = 0x0150,
MUL338 = 0x0151,
MUL339 = 0x0152,
MUL340 = 0x0153,
MUL341 = 0x0154,
MUL342 = 0x0155,
MUL343 = 0x0156,
MUL344 = 0x0157,
MUL345 = 0x0158,
MUL346 = 0x0159,
MUL347 = 0x015a,
MUL348 = 0x015b,
MUL349 = 0x015c,
MUL350 = 0x015d,
MUL351 = 0x015e,
MUL352 = 0x015f,
MUL353 = 0x0160,
MUL354 = 0x0161,
MUL355 = 0x0162,
MUL356 = 0x0163,
MUL357 = 0x0164,
MUL358 = 0x0165,
MUL359 = 0x0166,
MUL360 = 0x0167,
MUL361 = 0x0168,
MUL362 = 0x0169,
MUL363 = 0x016a,
MUL364 = 0x016b,
MUL365 = 0x016c,
MUL366 = 0x016d,
MUL367 = 0x016e,
MUL368 = 0x016f,
MUL369 = 0x0170,
MUL370 = 0x0171,
MUL371 = 0x0172,
MUL372 = 0x0173,
MUL373 = 0x0174,
MUL374 = 0x0175,
MUL375 = 0x0176,
MUL376 = 0x0177,
MUL377 = 0x0178,
MUL378 = 0x0179,
MUL379 = 0x017a,
MUL380 = 0x017b,
MUL381 = 0x017c,
MUL382 = 0x017d,
MUL383 = 0x017e,
MUL384 = 0x017f,
MUL385 = 0x0180,
MUL386 = 0x0181,
MUL387 = 0x0182,
MUL388 = 0x0183,
MUL389 = 0x0184,
MUL390 = 0x0185,
MUL391 = 0x0186,
MUL392 = 0x0187,
MUL393 = 0x0188,
MUL394 = 0x0189,
MUL395 = 0x018a,
MUL396 = 0x018b,
MUL397 = 0x018c,
MUL398 = 0x018d,
MUL399 = 0x018e,
MUL400 = 0x018f,
MUL401 = 0x0190,
MUL402 = 0x0191,
MUL403 = 0x0192,
MUL404 = 0x0193,
MUL405 = 0x0194,
MUL406 = 0x0195,
MUL407 = 0x0196,
MUL408 = 0x0197,
MUL409 = 0x0198,
MUL410 = 0x0199,
MUL411 = 0x019a,
MUL412 = 0x019b,
MUL413 = 0x019c,
MUL414 = 0x019d,
MUL415 = 0x019e,
MUL416 = 0x019f,
MUL417 = 0x01a0,
MUL418 = 0x01a1,
MUL419 = 0x01a2,
MUL420 = 0x01a3,
MUL421 = 0x01a4,
MUL422 = 0x01a5,
MUL423 = 0x01a6,
MUL424 = 0x01a7,
MUL425 = 0x01a8,
MUL426 = 0x01a9,
MUL427 = 0x01aa,
MUL428 = 0x01ab,
MUL429 = 0x01ac,
MUL430 = 0x01ad,
MUL431 = 0x01ae,
MUL432 = 0x01af,
MUL433 = 0x01b0,
MUL434 = 0x01b1,
MUL435 = 0x01b2,
MUL436 = 0x01b3,
MUL437 = 0x01b4,
MUL438 = 0x01b5,
MUL439 = 0x01b6,
MUL440 = 0x01b7,
MUL441 = 0x01b8,
MUL442 = 0x01b9,
MUL443 = 0x01ba,
MUL444 = 0x01bb,
MUL445 = 0x01bc,
MUL446 = 0x01bd,
MUL447 = 0x01be,
MUL448 = 0x01bf,
MUL449 = 0x01c0,
MUL450 = 0x01c1,
MUL451 = 0x01c2,
MUL452 = 0x01c3,
MUL453 = 0x01c4,
MUL454 = 0x01c5,
MUL455 = 0x01c6,
MUL456 = 0x01c7,
MUL457 = 0x01c8,
MUL458 = 0x01c9,
MUL459 = 0x01ca,
MUL460 = 0x01cb,
MUL461 = 0x01cc,
MUL462 = 0x01cd,
MUL463 = 0x01ce,
MUL464 = 0x01cf,
MUL465 = 0x01d0,
MUL466 = 0x01d1,
MUL467 = 0x01d2,
MUL468 = 0x01d3,
MUL469 = 0x01d4,
MUL470 = 0x01d5,
MUL471 = 0x01d6,
MUL472 = 0x01d7,
MUL473 = 0x01d8,
MUL474 = 0x01d9,
MUL475 = 0x01da,
MUL476 = 0x01db,
MUL477 = 0x01dc,
MUL478 = 0x01dd,
MUL479 = 0x01de,
MUL480 = 0x01df,
MUL481 = 0x01e0,
MUL482 = 0x01e1,
MUL483 = 0x01e2,
MUL484 = 0x01e3,
MUL485 = 0x01e4,
MUL486 = 0x01e5,
MUL487 = 0x01e6,
MUL488 = 0x01e7,
MUL489 = 0x01e8,
MUL490 = 0x01e9,
MUL491 = 0x01ea,
MUL492 = 0x01eb,
MUL493 = 0x01ec,
MUL494 = 0x01ed,
MUL495 = 0x01ee,
MUL496 = 0x01ef,
MUL497 = 0x01f0,
MUL498 = 0x01f1,
MUL499 = 0x01f2,
MUL500 = 0x01f3,
MUL501 = 0x01f4,
MUL502 = 0x01f5,
MUL503 = 0x01f6,
MUL504 = 0x01f7,
MUL505 = 0x01f8,
MUL506 = 0x01f9,
MUL507 = 0x01fa,
MUL508 = 0x01fb,
MUL509 = 0x01fc,
MUL510 = 0x01fd,
MUL511 = 0x01fe,
MUL512 = 0x01ff,
}
impl Plln {
#[inline(always)]
pub const fn from_bits(val: u16) -> Plln {
unsafe { core::mem::transmute(val & 0x01ff) }
}
#[inline(always)]
pub const fn to_bits(self) -> u16 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u16> for Plln {
#[inline(always)]
fn from(val: u16) -> Plln {
Plln::from_bits(val)
}
}
impl From<Plln> for u16 {
#[inline(always)]
fn from(val: Plln) -> u16 {
Plln::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllrge {
#[doc = "Frequency is between 1 and 2 MHz"]
RANGE1 = 0x0,
#[doc = "Frequency is between 2 and 4 MHz"]
RANGE2 = 0x01,
#[doc = "Frequency is between 4 and 8 MHz"]
RANGE4 = 0x02,
#[doc = "Frequency is between 8 and 16 MHz"]
RANGE8 = 0x03,
}
impl Pllrge {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllrge {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllrge {
#[inline(always)]
fn from(val: u8) -> Pllrge {
Pllrge::from_bits(val)
}
}
impl From<Pllrge> for u8 {
#[inline(always)]
fn from(val: Pllrge) -> u8 {
Pllrge::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllsrc {
#[doc = "no clock send to DIVMx divider and PLLs (default after reset)"]
DISABLE = 0x0,
#[doc = "HSI selected as PLL clock (hsi_ck)"]
HSI = 0x01,
#[doc = "CSI selected as PLL clock (csi_ck)"]
CSI = 0x02,
#[doc = "HSE selected as PLL clock (hse_ck)"]
HSE = 0x03,
}
impl Pllsrc {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllsrc {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllsrc {
#[inline(always)]
fn from(val: u8) -> Pllsrc {
Pllsrc::from_bits(val)
}
}
impl From<Pllsrc> for u8 {
#[inline(always)]
fn from(val: Pllsrc) -> u8 {
Pllsrc::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllvcosel {
#[doc = "VCO frequency range 192 to 836 MHz"]
WIDE_VCO = 0x0,
#[doc = "VCO frequency range 150 to 420 MHz"]
MEDIUM_VCO = 0x01,
}
impl Pllvcosel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllvcosel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllvcosel {
#[inline(always)]
fn from(val: u8) -> Pllvcosel {
Pllvcosel::from_bits(val)
}
}
impl From<Pllvcosel> for u8 {
#[inline(always)]
fn from(val: Pllvcosel) -> u8 {
Pllvcosel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Ppre {
#[doc = "rcc_pclk3 = rcc_hclk1 / 1"]
DIV1 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
_RESERVED_3 = 0x03,
#[doc = "rcc_pclk3 = rcc_hclk1 / 2"]
DIV2 = 0x04,
#[doc = "rcc_pclk3 = rcc_hclk1 / 4"]
DIV4 = 0x05,
#[doc = "rcc_pclk3 = rcc_hclk1 / 8"]
DIV8 = 0x06,
#[doc = "rcc_pclk3 = rcc_hclk1 / 16"]
DIV16 = 0x07,
}
impl Ppre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Ppre {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Ppre {
#[inline(always)]
fn from(val: u8) -> Ppre {
Ppre::from_bits(val)
}
}
impl From<Ppre> for u8 {
#[inline(always)]
fn from(val: Ppre) -> u8 {
Ppre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Rngsel {
#[doc = "hsi48_ker_ck selected as kernel clock (default after reset)"]
HSI48 = 0x0,
#[doc = "pll1_q_ck selected as kernel clock"]
PLL1_Q = 0x01,
#[doc = "lse_ck selected as kernel clock"]
LSE = 0x02,
#[doc = "lsi_ker_ck selected as kernel clock"]
LSI = 0x03,
}
impl Rngsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Rngsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Rngsel {
#[inline(always)]
fn from(val: u8) -> Rngsel {
Rngsel::from_bits(val)
}
}
impl From<Rngsel> for u8 {
#[inline(always)]
fn from(val: Rngsel) -> u8 {
Rngsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Rtcsel {
#[doc = "no clock (default after Backup domain reset)"]
DISABLE = 0x0,
#[doc = "LSE selected as RTC clock"]
LSE = 0x01,
#[doc = "LSI selected as RTC clock"]
LSI = 0x02,
#[doc = "HSE divided by RTCPRE value selected as RTC clock"]
HSE_DIV_RTCPRE = 0x03,
}
impl Rtcsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Rtcsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Rtcsel {
#[inline(always)]
fn from(val: u8) -> Rtcsel {
Rtcsel::from_bits(val)
}
}
impl From<Rtcsel> for u8 {
#[inline(always)]
fn from(val: Rtcsel) -> u8 {
Rtcsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Saisel {
#[doc = "pll1_q_ck selected as kernel clock (default after reset)"]
PLL1_Q = 0x0,
#[doc = "pll2_p_ck selected as kernel clock"]
PLL2_P = 0x01,
#[doc = "pll3_p_ck selected as kernel clock"]
PLL3_P = 0x02,
#[doc = "AUDIOCLK selected as kernel clock"]
AUDIOCLK = 0x03,
#[doc = "per_ck selected as kernel clock"]
PER = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Saisel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Saisel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Saisel {
#[inline(always)]
fn from(val: u8) -> Saisel {
Saisel::from_bits(val)
}
}
impl From<Saisel> for u8 {
#[inline(always)]
fn from(val: Saisel) -> u8 {
Saisel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Sdmmcsel {
#[doc = "pll1_q_ck selected as kernel clock (default after reset)"]
PLL1_Q = 0x0,
#[doc = "pll2_r_ck selected as kernel clock"]
PLL2_R = 0x01,
}
impl Sdmmcsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Sdmmcsel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Sdmmcsel {
#[inline(always)]
fn from(val: u8) -> Sdmmcsel {
Sdmmcsel::from_bits(val)
}
}
impl From<Sdmmcsel> for u8 {
#[inline(always)]
fn from(val: Sdmmcsel) -> u8 {
Sdmmcsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Spi1sel {
#[doc = "pll1_q_ck selected as kernel clock (default after reset)"]
PLL1_Q = 0x0,
#[doc = "pll2_p_ck selected as kernel clock"]
PLL2_P = 0x01,
#[doc = "pll3_p_ck selected as kernel clock"]
PLL3_P = 0x02,
#[doc = "AUDIOCLK selected as kernel clock"]
AUDIOCLK = 0x03,
#[doc = "per_ck selected as kernel clock"]
PER = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Spi1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Spi1sel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Spi1sel {
#[inline(always)]
fn from(val: u8) -> Spi1sel {
Spi1sel::from_bits(val)
}
}
impl From<Spi1sel> for u8 {
#[inline(always)]
fn from(val: Spi1sel) -> u8 {
Spi1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Spi2sel {
#[doc = "pll1_q_ck selected as kernel clock (default after reset)"]
PLL1_Q = 0x0,
#[doc = "pll2_p_ck selected as kernel clock"]
PLL2_P = 0x01,
#[doc = "pll3_p_ck selected as kernel clock"]
PLL3_P = 0x02,
#[doc = "AUDIOCLK selected as kernel clock"]
AUDIOCLK = 0x03,
#[doc = "per_ck selected as kernel clock"]
PER = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Spi2sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Spi2sel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Spi2sel {
#[inline(always)]
fn from(val: u8) -> Spi2sel {
Spi2sel::from_bits(val)
}
}
impl From<Spi2sel> for u8 {
#[inline(always)]
fn from(val: Spi2sel) -> u8 {
Spi2sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Spi3sel {
#[doc = "pll1_q_ck selected as kernel clock (default after reset)"]
PLL1_Q = 0x0,
#[doc = "pll2_p_ck selected as kernel clock"]
PLL2_P = 0x01,
#[doc = "pll3_p_ck selected as kernel clock"]
PLL3_P = 0x02,
#[doc = "AUDIOCLK selected as kernel clock"]
AUDIOCLK = 0x03,
#[doc = "per_ck selected as kernel clock"]
PER = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Spi3sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Spi3sel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Spi3sel {
#[inline(always)]
fn from(val: u8) -> Spi3sel {
Spi3sel::from_bits(val)
}
}
impl From<Spi3sel> for u8 {
#[inline(always)]
fn from(val: Spi3sel) -> u8 {
Spi3sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Spi4sel {
#[doc = "rcc_pclk2 selected as kernel clock (default after reset)"]
PCLK2 = 0x0,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q = 0x01,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q = 0x02,
#[doc = "hsi_ker selected as peripheral clock"]
HSI = 0x03,
#[doc = "csi_ker selected as peripheral clock"]
CSI = 0x04,
#[doc = "HSE selected as peripheral clock"]
HSE = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Spi4sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Spi4sel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Spi4sel {
#[inline(always)]
fn from(val: u8) -> Spi4sel {
Spi4sel::from_bits(val)
}
}
impl From<Spi4sel> for u8 {
#[inline(always)]
fn from(val: Spi4sel) -> u8 {
Spi4sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Spi5sel {
#[doc = "rcc_pclk3 selected as kernel clock (default after reset)"]
PCLK3 = 0x0,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q = 0x01,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q = 0x02,
#[doc = "hsi_ker selected as peripheral clock"]
HSI = 0x03,
#[doc = "csi_ker selected as peripheral clock"]
CSI = 0x04,
#[doc = "HSE selected as peripheral clock"]
HSE = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Spi5sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Spi5sel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Spi5sel {
#[inline(always)]
fn from(val: u8) -> Spi5sel {
Spi5sel::from_bits(val)
}
}
impl From<Spi5sel> for u8 {
#[inline(always)]
fn from(val: Spi5sel) -> u8 {
Spi5sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Spi6sel {
#[doc = "rcc_pclk2 selected as peripheral clock"]
PCLK2 = 0x0,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q = 0x01,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q = 0x02,
#[doc = "hsi_ker selected as peripheral clock"]
HSI = 0x03,
#[doc = "csi_ker selected as peripheral clock"]
CSI = 0x04,
#[doc = "HSE selected as peripheral clock"]
HSE = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Spi6sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Spi6sel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Spi6sel {
#[inline(always)]
fn from(val: u8) -> Spi6sel {
Spi6sel::from_bits(val)
}
}
impl From<Spi6sel> for u8 {
#[inline(always)]
fn from(val: Spi6sel) -> u8 {
Spi6sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Spriv {
#[doc = "Read and write to RCC secure functions can be done by privileged or unprivileged access."]
ANY = 0x0,
#[doc = "Read and write to RCC secure functions can be done by privileged access only"]
PRIVILEGED = 0x01,
}
impl Spriv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Spriv {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Spriv {
#[inline(always)]
fn from(val: u8) -> Spriv {
Spriv::from_bits(val)
}
}
impl From<Spriv> for u8 {
#[inline(always)]
fn from(val: Spriv) -> u8 {
Spriv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Stopkerwuck {
#[doc = "HSI selected as wakeup clock from system Stop (default after reset)"]
HSI = 0x0,
#[doc = "CSI selected as wakeup clock from system Stop"]
CSI = 0x01,
}
impl Stopkerwuck {
#[inline(always)]
pub const fn from_bits(val: u8) -> Stopkerwuck {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Stopkerwuck {
#[inline(always)]
fn from(val: u8) -> Stopkerwuck {
Stopkerwuck::from_bits(val)
}
}
impl From<Stopkerwuck> for u8 {
#[inline(always)]
fn from(val: Stopkerwuck) -> u8 {
Stopkerwuck::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Stopwuck {
_RESERVED_0 = 0x0,
#[doc = "CSI selected as wakeup clock from system Stop"]
CSI = 0x01,
}
impl Stopwuck {
#[inline(always)]
pub const fn from_bits(val: u8) -> Stopwuck {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Stopwuck {
#[inline(always)]
fn from(val: u8) -> Stopwuck {
Stopwuck::from_bits(val)
}
}
impl From<Stopwuck> for u8 {
#[inline(always)]
fn from(val: Stopwuck) -> u8 {
Stopwuck::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Sw {
#[doc = "HSI selected as system clock"]
HSI = 0x0,
#[doc = "CSI selected as system clock"]
CSI = 0x01,
#[doc = "HSE selected as system clock"]
HSE = 0x02,
#[doc = "PLL1 selected as system clock"]
PLL1_P = 0x03,
_RESERVED_4 = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Sw {
#[inline(always)]
pub const fn from_bits(val: u8) -> Sw {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Sw {
#[inline(always)]
fn from(val: u8) -> Sw {
Sw::from_bits(val)
}
}
impl From<Sw> for u8 {
#[inline(always)]
fn from(val: Sw) -> u8 {
Sw::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Systicksel {
#[doc = "rcc_hclk/8 selected as clock source (default after reset)"]
HCLK1_DIV_8 = 0x0,
#[doc = "lsi_ker_ck\\[1\\]
selected as clock source"]
LSI = 0x01,
#[doc = "lse_ck\\[1\\]
selected as clock source"]
LSE = 0x02,
_RESERVED_3 = 0x03,
}
impl Systicksel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Systicksel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Systicksel {
#[inline(always)]
fn from(val: u8) -> Systicksel {
Systicksel::from_bits(val)
}
}
impl From<Systicksel> for u8 {
#[inline(always)]
fn from(val: Systicksel) -> u8 {
Systicksel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Timicsel {
#[doc = "No internal clock available for timers input capture (default after reset)"]
B_0X0 = 0x0,
#[doc = "hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture"]
B_0X1 = 0x01,
}
impl Timicsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Timicsel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Timicsel {
#[inline(always)]
fn from(val: u8) -> Timicsel {
Timicsel::from_bits(val)
}
}
impl From<Timicsel> for u8 {
#[inline(always)]
fn from(val: Timicsel) -> u8 {
Timicsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Timpre {
#[doc = "The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset)"]
DEFAULT_X2 = 0x0,
#[doc = "The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2"]
DEFAULT_X4 = 0x01,
}
impl Timpre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Timpre {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Timpre {
#[inline(always)]
fn from(val: u8) -> Timpre {
Timpre::from_bits(val)
}
}
impl From<Timpre> for u8 {
#[inline(always)]
fn from(val: Timpre) -> u8 {
Timpre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Usart1sel {
#[doc = "rcc_pclk2 selected as peripheral clock"]
PCLK2 = 0x0,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q = 0x01,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q = 0x02,
#[doc = "hsi_ker selected as peripheral clock"]
HSI = 0x03,
#[doc = "csi_ker selected as peripheral clock"]
CSI = 0x04,
#[doc = "LSE selected as peripheral clock"]
LSE = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Usart1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Usart1sel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Usart1sel {
#[inline(always)]
fn from(val: u8) -> Usart1sel {
Usart1sel::from_bits(val)
}
}
impl From<Usart1sel> for u8 {
#[inline(always)]
fn from(val: Usart1sel) -> u8 {
Usart1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Usartsel {
#[doc = "rcc_pclk1 selected as peripheral clock"]
PCLK1 = 0x0,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q = 0x01,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q = 0x02,
#[doc = "hsi_ker selected as peripheral clock"]
HSI = 0x03,
#[doc = "csi_ker selected as peripheral clock"]
CSI = 0x04,
#[doc = "LSE selected as peripheral clock"]
LSE = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Usartsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Usartsel {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Usartsel {
#[inline(always)]
fn from(val: u8) -> Usartsel {
Usartsel::from_bits(val)
}
}
impl From<Usartsel> for u8 {
#[inline(always)]
fn from(val: Usartsel) -> u8 {
Usartsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Usbsel {
#[doc = "Disable the kernel clock"]
DISABLE = 0x0,
#[doc = "pll1_q selected as peripheral clock"]
PLL1_Q = 0x01,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q = 0x02,
#[doc = "HSI48 selected as peripheral clock"]
HSI48 = 0x03,
}
impl Usbsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Usbsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Usbsel {
#[inline(always)]
fn from(val: u8) -> Usbsel {
Usbsel::from_bits(val)
}
}
impl From<Usbsel> for u8 {
#[inline(always)]
fn from(val: Usbsel) -> u8 {
Usbsel::to_bits(val)
}
}
}