#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
#[doc = "RCC address block description"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Rcc {
ptr: *mut u8,
}
unsafe impl Send for Rcc {}
unsafe impl Sync for Rcc {}
impl Rcc {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "RCC clock control register"]
#[inline(always)]
pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "RCC internal clock source calibration register"]
#[inline(always)]
pub const fn icscr(self) -> crate::common::Reg<regs::Icscr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "RCC clock configuration register"]
#[inline(always)]
pub const fn cfgr(self) -> crate::common::Reg<regs::Cfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
}
#[doc = "RCC clock recovery RC register."]
#[inline(always)]
pub const fn crrcr(self) -> crate::common::Reg<regs::Crrcr, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
}
#[doc = "RCC clock interrupt enable register"]
#[inline(always)]
pub const fn cier(self) -> crate::common::Reg<regs::Cier, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
}
#[doc = "RCC clock interrupt flag register"]
#[inline(always)]
pub const fn cifr(self) -> crate::common::Reg<regs::Cifr, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
}
#[doc = "RCC clock interrupt clear register"]
#[inline(always)]
pub const fn cicr(self) -> crate::common::Reg<regs::Cicr, crate::common::W> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
}
#[doc = "RCC I/O port reset register"]
#[inline(always)]
pub const fn gpiorstr(self) -> crate::common::Reg<regs::Gpiorstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
}
#[doc = "RCC AHB peripheral reset register"]
#[inline(always)]
pub const fn ahbrstr(self) -> crate::common::Reg<regs::Ahbrstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
}
#[doc = "RCC APB peripheral reset register 1"]
#[inline(always)]
pub const fn apbrstr1(self) -> crate::common::Reg<regs::Apbrstr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
}
#[doc = "RCC APB peripheral reset register 2"]
#[inline(always)]
pub const fn apbrstr2(self) -> crate::common::Reg<regs::Apbrstr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
}
#[doc = "RCC I/O port clock enable register"]
#[inline(always)]
pub const fn gpioenr(self) -> crate::common::Reg<regs::Gpioenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
}
#[doc = "RCC AHB peripheral clock enable register"]
#[inline(always)]
pub const fn ahbenr(self) -> crate::common::Reg<regs::Ahbenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
}
#[doc = "RCC APB peripheral clock enable register 1"]
#[inline(always)]
pub const fn apbenr1(self) -> crate::common::Reg<regs::Apbenr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
}
#[doc = "RCC APB peripheral clock enable register 2"]
#[inline(always)]
pub const fn apbenr2(self) -> crate::common::Reg<regs::Apbenr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
}
#[doc = "RCC I/O port in Sleep mode clock enable register"]
#[inline(always)]
pub const fn gpiosmenr(self) -> crate::common::Reg<regs::Gpiosmenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
}
#[doc = "RCC AHB peripheral clock enable in Sleep/Stop mode register"]
#[inline(always)]
pub const fn ahbsmenr(self) -> crate::common::Reg<regs::Ahbsmenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
}
#[doc = "RCC APB peripheral clock enable in Sleep/Stop mode register 1"]
#[inline(always)]
pub const fn apbsmenr1(self) -> crate::common::Reg<regs::Apbsmenr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
}
#[doc = "RCC APB peripheral clock enable in Sleep/Stop mode register 2"]
#[inline(always)]
pub const fn apbsmenr2(self) -> crate::common::Reg<regs::Apbsmenr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
}
#[doc = "RCC peripherals independent clock configuration register 1"]
#[inline(always)]
pub const fn ccipr(self) -> crate::common::Reg<regs::Ccipr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
}
#[doc = "RCC peripherals independent clock configuration register 2."]
#[inline(always)]
pub const fn ccipr2(self) -> crate::common::Reg<regs::Ccipr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
}
#[doc = "RCC control/status register 1"]
#[inline(always)]
pub const fn csr1(self) -> crate::common::Reg<regs::Csr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
}
#[doc = "RCC control/status register 2"]
#[inline(always)]
pub const fn csr2(self) -> crate::common::Reg<regs::Csr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
}
}
pub mod regs {
#[doc = "RCC AHB peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahbenr(pub u32);
impl Ahbenr {
#[doc = "DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled."]
#[inline(always)]
pub const fn dma1en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled."]
#[inline(always)]
pub fn set_dma1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the Flash memory is in power down mode."]
#[inline(always)]
pub const fn flashen(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the Flash memory is in power down mode."]
#[inline(always)]
pub fn set_flashen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "CRC clock enable Set and cleared by software."]
#[inline(always)]
pub const fn crcen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_crcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
}
impl Default for Ahbenr {
#[inline(always)]
fn default() -> Ahbenr {
Ahbenr(0)
}
}
impl core::fmt::Debug for Ahbenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahbenr")
.field("dma1en", &self.dma1en())
.field("flashen", &self.flashen())
.field("crcen", &self.crcen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahbenr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ahbenr {{ dma1en: {=bool:?}, flashen: {=bool:?}, crcen: {=bool:?} }}",
self.dma1en(),
self.flashen(),
self.crcen()
)
}
}
#[doc = "RCC AHB peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahbrstr(pub u32);
impl Ahbrstr {
#[doc = "DMA1 and DMAMUX reset Set and cleared by software."]
#[inline(always)]
pub const fn dma1rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "DMA1 and DMAMUX reset Set and cleared by software."]
#[inline(always)]
pub fn set_dma1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Flash memory interface reset Set and cleared by software. This bit can only be set when the Flash memory is in power down mode."]
#[inline(always)]
pub const fn flashrst(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Flash memory interface reset Set and cleared by software. This bit can only be set when the Flash memory is in power down mode."]
#[inline(always)]
pub fn set_flashrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "CRC reset Set and cleared by software."]
#[inline(always)]
pub const fn crcrst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC reset Set and cleared by software."]
#[inline(always)]
pub fn set_crcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
}
impl Default for Ahbrstr {
#[inline(always)]
fn default() -> Ahbrstr {
Ahbrstr(0)
}
}
impl core::fmt::Debug for Ahbrstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahbrstr")
.field("dma1rst", &self.dma1rst())
.field("flashrst", &self.flashrst())
.field("crcrst", &self.crcrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahbrstr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ahbrstr {{ dma1rst: {=bool:?}, flashrst: {=bool:?}, crcrst: {=bool:?} }}",
self.dma1rst(),
self.flashrst(),
self.crcrst()
)
}
}
#[doc = "RCC AHB peripheral clock enable in Sleep/Stop mode register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahbsmenr(pub u32);
impl Ahbsmenr {
#[doc = "DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral."]
#[inline(always)]
pub const fn dma1smen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral."]
#[inline(always)]
pub fn set_dma1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode."]
#[inline(always)]
pub const fn flashsmen(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode."]
#[inline(always)]
pub fn set_flashsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "SRAM clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn sramsmen(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "SRAM clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_sramsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "CRC clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn crcsmen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_crcsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
}
impl Default for Ahbsmenr {
#[inline(always)]
fn default() -> Ahbsmenr {
Ahbsmenr(0)
}
}
impl core::fmt::Debug for Ahbsmenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahbsmenr")
.field("dma1smen", &self.dma1smen())
.field("flashsmen", &self.flashsmen())
.field("sramsmen", &self.sramsmen())
.field("crcsmen", &self.crcsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahbsmenr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ahbsmenr {{ dma1smen: {=bool:?}, flashsmen: {=bool:?}, sramsmen: {=bool:?}, crcsmen: {=bool:?} }}",
self.dma1smen(),
self.flashsmen(),
self.sramsmen(),
self.crcsmen()
)
}
}
#[doc = "RCC APB peripheral clock enable register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbenr1(pub u32);
impl Apbenr1 {
#[doc = "TIM2 timer clock enable Set and cleared by software."]
#[inline(always)]
pub const fn tim2en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 timer clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_tim2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM3 timer clock enable Set and cleared by software."]
#[inline(always)]
pub const fn tim3en(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "TIM3 timer clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_tim3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "RTC APB clock enable Set and cleared by software."]
#[inline(always)]
pub const fn rtcapben(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "RTC APB clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_rtcapben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0."]
#[inline(always)]
pub const fn wwdgen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0."]
#[inline(always)]
pub fn set_wwdgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "FDCAN1 clock enable Set and cleared by software."]
#[inline(always)]
pub const fn fdcan1en(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "FDCAN1 clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_fdcan1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USB clock enable Set and cleared by software."]
#[inline(always)]
pub const fn usben(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "USB clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_usben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "SPI2 clock enable Set and cleared by software."]
#[inline(always)]
pub const fn spi2en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_spi2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "CRS clock enable Set and cleared by software."]
#[inline(always)]
pub const fn crsen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "CRS clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_crsen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "USART2 clock enable Set and cleared by software."]
#[inline(always)]
pub const fn usart2en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_usart2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART3 clock enable Set and cleared by software."]
#[inline(always)]
pub const fn usart3en(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART3 clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_usart3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "USART4 clock enable Set and cleared by software."]
#[inline(always)]
pub const fn usart4en(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "USART4 clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_usart4en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "I2C1 clock enable Set and cleared by software."]
#[inline(always)]
pub const fn i2c1en(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_i2c1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 clock enable Set and cleared by software."]
#[inline(always)]
pub const fn i2c2en(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_i2c2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "Debug support clock enable Set and cleared by software."]
#[inline(always)]
pub const fn dbgen(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "Debug support clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_dbgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Power interface clock enable Set and cleared by software."]
#[inline(always)]
pub const fn pwren(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Power interface clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_pwren(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
}
impl Default for Apbenr1 {
#[inline(always)]
fn default() -> Apbenr1 {
Apbenr1(0)
}
}
impl core::fmt::Debug for Apbenr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbenr1")
.field("tim2en", &self.tim2en())
.field("tim3en", &self.tim3en())
.field("rtcapben", &self.rtcapben())
.field("wwdgen", &self.wwdgen())
.field("fdcan1en", &self.fdcan1en())
.field("usben", &self.usben())
.field("spi2en", &self.spi2en())
.field("crsen", &self.crsen())
.field("usart2en", &self.usart2en())
.field("usart3en", &self.usart3en())
.field("usart4en", &self.usart4en())
.field("i2c1en", &self.i2c1en())
.field("i2c2en", &self.i2c2en())
.field("dbgen", &self.dbgen())
.field("pwren", &self.pwren())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbenr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbenr1 {{ tim2en: {=bool:?}, tim3en: {=bool:?}, rtcapben: {=bool:?}, wwdgen: {=bool:?}, fdcan1en: {=bool:?}, usben: {=bool:?}, spi2en: {=bool:?}, crsen: {=bool:?}, usart2en: {=bool:?}, usart3en: {=bool:?}, usart4en: {=bool:?}, i2c1en: {=bool:?}, i2c2en: {=bool:?}, dbgen: {=bool:?}, pwren: {=bool:?} }}" , self . tim2en () , self . tim3en () , self . rtcapben () , self . wwdgen () , self . fdcan1en () , self . usben () , self . spi2en () , self . crsen () , self . usart2en () , self . usart3en () , self . usart4en () , self . i2c1en () , self . i2c2en () , self . dbgen () , self . pwren ())
}
}
#[doc = "RCC APB peripheral clock enable register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbenr2(pub u32);
impl Apbenr2 {
#[doc = "SYSCFG clock enable Set and cleared by software."]
#[inline(always)]
pub const fn syscfgen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "SYSCFG clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_syscfgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM1 timer clock enable Set and cleared by software."]
#[inline(always)]
pub const fn tim1en(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 timer clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_tim1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 clock enable Set and cleared by software."]
#[inline(always)]
pub const fn spi1en(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_spi1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1 clock enable Set and cleared by software."]
#[inline(always)]
pub const fn usart1en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_usart1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM14 timer clock enable Set and cleared by software."]
#[inline(always)]
pub const fn tim14en(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "TIM14 timer clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_tim14en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "TIM15 timer clock enable Set and cleared by software."]
#[inline(always)]
pub const fn tim15en(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "TIM15 timer clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_tim15en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "TIM16 timer clock enable Set and cleared by software."]
#[inline(always)]
pub const fn tim16en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_tim16en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM16 timer clock enable Set and cleared by software."]
#[inline(always)]
pub const fn tim17en(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_tim17en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "ADC clock enable Set and cleared by software."]
#[inline(always)]
pub const fn adc1en(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "ADC clock enable Set and cleared by software."]
#[inline(always)]
pub fn set_adc1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Apbenr2 {
#[inline(always)]
fn default() -> Apbenr2 {
Apbenr2(0)
}
}
impl core::fmt::Debug for Apbenr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbenr2")
.field("syscfgen", &self.syscfgen())
.field("tim1en", &self.tim1en())
.field("spi1en", &self.spi1en())
.field("usart1en", &self.usart1en())
.field("tim14en", &self.tim14en())
.field("tim15en", &self.tim15en())
.field("tim16en", &self.tim16en())
.field("tim17en", &self.tim17en())
.field("adc1en", &self.adc1en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbenr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbenr2 {{ syscfgen: {=bool:?}, tim1en: {=bool:?}, spi1en: {=bool:?}, usart1en: {=bool:?}, tim14en: {=bool:?}, tim15en: {=bool:?}, tim16en: {=bool:?}, tim17en: {=bool:?}, adc1en: {=bool:?} }}" , self . syscfgen () , self . tim1en () , self . spi1en () , self . usart1en () , self . tim14en () , self . tim15en () , self . tim16en () , self . tim17en () , self . adc1en ())
}
}
#[doc = "RCC APB peripheral reset register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbrstr1(pub u32);
impl Apbrstr1 {
#[doc = "TIM2 timer reset Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn tim2rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 timer reset Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_tim2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM3 timer reset Set and cleared by software."]
#[inline(always)]
pub const fn tim3rst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "TIM3 timer reset Set and cleared by software."]
#[inline(always)]
pub fn set_tim3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "FDCAN1 reset Set and cleared by software."]
#[inline(always)]
pub const fn fdcan1rst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "FDCAN1 reset Set and cleared by software."]
#[inline(always)]
pub fn set_fdcan1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USB reset Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn usbrst(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "USB reset Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_usbrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "SPI2 reset Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn spi2rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 reset Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_spi2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "CRS reset Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn crsrst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "CRS reset Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_crsrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "USART2 reset Set and cleared by software."]
#[inline(always)]
pub const fn usart2rst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 reset Set and cleared by software."]
#[inline(always)]
pub fn set_usart2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART3 reset Set and cleared by software."]
#[inline(always)]
pub const fn usart3rst(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART3 reset Set and cleared by software."]
#[inline(always)]
pub fn set_usart3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "USART4 reset Set and cleared by software."]
#[inline(always)]
pub const fn usart4rst(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "USART4 reset Set and cleared by software."]
#[inline(always)]
pub fn set_usart4rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "I2C1 reset Set and cleared by software."]
#[inline(always)]
pub const fn i2c1rst(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 reset Set and cleared by software."]
#[inline(always)]
pub fn set_i2c1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 reset Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn i2c2rst(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 reset Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_i2c2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "Debug support reset Set and cleared by software."]
#[inline(always)]
pub const fn dbgrst(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "Debug support reset Set and cleared by software."]
#[inline(always)]
pub fn set_dbgrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Power interface reset Set and cleared by software."]
#[inline(always)]
pub const fn pwrrst(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Power interface reset Set and cleared by software."]
#[inline(always)]
pub fn set_pwrrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
}
impl Default for Apbrstr1 {
#[inline(always)]
fn default() -> Apbrstr1 {
Apbrstr1(0)
}
}
impl core::fmt::Debug for Apbrstr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbrstr1")
.field("tim2rst", &self.tim2rst())
.field("tim3rst", &self.tim3rst())
.field("fdcan1rst", &self.fdcan1rst())
.field("usbrst", &self.usbrst())
.field("spi2rst", &self.spi2rst())
.field("crsrst", &self.crsrst())
.field("usart2rst", &self.usart2rst())
.field("usart3rst", &self.usart3rst())
.field("usart4rst", &self.usart4rst())
.field("i2c1rst", &self.i2c1rst())
.field("i2c2rst", &self.i2c2rst())
.field("dbgrst", &self.dbgrst())
.field("pwrrst", &self.pwrrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbrstr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbrstr1 {{ tim2rst: {=bool:?}, tim3rst: {=bool:?}, fdcan1rst: {=bool:?}, usbrst: {=bool:?}, spi2rst: {=bool:?}, crsrst: {=bool:?}, usart2rst: {=bool:?}, usart3rst: {=bool:?}, usart4rst: {=bool:?}, i2c1rst: {=bool:?}, i2c2rst: {=bool:?}, dbgrst: {=bool:?}, pwrrst: {=bool:?} }}" , self . tim2rst () , self . tim3rst () , self . fdcan1rst () , self . usbrst () , self . spi2rst () , self . crsrst () , self . usart2rst () , self . usart3rst () , self . usart4rst () , self . i2c1rst () , self . i2c2rst () , self . dbgrst () , self . pwrrst ())
}
}
#[doc = "RCC APB peripheral reset register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbrstr2(pub u32);
impl Apbrstr2 {
#[doc = "SYSCFG reset Set and cleared by software."]
#[inline(always)]
pub const fn syscfgrst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "SYSCFG reset Set and cleared by software."]
#[inline(always)]
pub fn set_syscfgrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM1 timer reset Set and cleared by software."]
#[inline(always)]
pub const fn tim1rst(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 timer reset Set and cleared by software."]
#[inline(always)]
pub fn set_tim1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 reset Set and cleared by software."]
#[inline(always)]
pub const fn spi1rst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 reset Set and cleared by software."]
#[inline(always)]
pub fn set_spi1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1 reset Set and cleared by software."]
#[inline(always)]
pub const fn usart1rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 reset Set and cleared by software."]
#[inline(always)]
pub fn set_usart1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM14 timer reset Set and cleared by software."]
#[inline(always)]
pub const fn tim14rst(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "TIM14 timer reset Set and cleared by software."]
#[inline(always)]
pub fn set_tim14rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "TIM15 timer reset Set and cleared by software."]
#[inline(always)]
pub const fn tim15rst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "TIM15 timer reset Set and cleared by software."]
#[inline(always)]
pub fn set_tim15rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "TIM16 timer reset Set and cleared by software."]
#[inline(always)]
pub const fn tim16rst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer reset Set and cleared by software."]
#[inline(always)]
pub fn set_tim16rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM16 timer reset Set and cleared by software."]
#[inline(always)]
pub const fn tim17rst(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer reset Set and cleared by software."]
#[inline(always)]
pub fn set_tim17rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "ADC reset Set and cleared by software."]
#[inline(always)]
pub const fn adc1rst(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "ADC reset Set and cleared by software."]
#[inline(always)]
pub fn set_adc1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Apbrstr2 {
#[inline(always)]
fn default() -> Apbrstr2 {
Apbrstr2(0)
}
}
impl core::fmt::Debug for Apbrstr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbrstr2")
.field("syscfgrst", &self.syscfgrst())
.field("tim1rst", &self.tim1rst())
.field("spi1rst", &self.spi1rst())
.field("usart1rst", &self.usart1rst())
.field("tim14rst", &self.tim14rst())
.field("tim15rst", &self.tim15rst())
.field("tim16rst", &self.tim16rst())
.field("tim17rst", &self.tim17rst())
.field("adc1rst", &self.adc1rst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbrstr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbrstr2 {{ syscfgrst: {=bool:?}, tim1rst: {=bool:?}, spi1rst: {=bool:?}, usart1rst: {=bool:?}, tim14rst: {=bool:?}, tim15rst: {=bool:?}, tim16rst: {=bool:?}, tim17rst: {=bool:?}, adc1rst: {=bool:?} }}" , self . syscfgrst () , self . tim1rst () , self . spi1rst () , self . usart1rst () , self . tim14rst () , self . tim15rst () , self . tim16rst () , self . tim17rst () , self . adc1rst ())
}
}
#[doc = "RCC APB peripheral clock enable in Sleep/Stop mode register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbsmenr1(pub u32);
impl Apbsmenr1 {
#[doc = "TIM2 timer clock enable during Sleep mode Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn tim2smen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 timer clock enable during Sleep mode Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_tim2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM3 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn tim3smen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "TIM3 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_tim3smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "RTC APB clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn rtcapbsmen(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "RTC APB clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_rtcapbsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "WWDG clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub const fn wwdgsmen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "WWDG clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub fn set_wwdgsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "FDCAN1 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub const fn fdcan1en(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "FDCAN1 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub fn set_fdcan1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USB clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn usbsmen(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "USB clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_usbsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "SPI2 clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn spi2smen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_spi2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "CRS clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn crssmen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "CRS clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_crssmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "USART2 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub const fn usart2smen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub fn set_usart2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART3 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub const fn usart3smen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART3 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub fn set_usart3smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "USART4 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub const fn usart4smen(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "USART4 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub fn set_usart4smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "I2C1 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub const fn i2c1smen(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub fn set_i2c1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn i2c2smen(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 clock enable during Sleep and Stop modes Set and cleared by software. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_i2c2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "Debug support clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn dbgsmen(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "Debug support clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_dbgsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Power interface clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn pwrsmen(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Power interface clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_pwrsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
}
impl Default for Apbsmenr1 {
#[inline(always)]
fn default() -> Apbsmenr1 {
Apbsmenr1(0)
}
}
impl core::fmt::Debug for Apbsmenr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbsmenr1")
.field("tim2smen", &self.tim2smen())
.field("tim3smen", &self.tim3smen())
.field("rtcapbsmen", &self.rtcapbsmen())
.field("wwdgsmen", &self.wwdgsmen())
.field("fdcan1en", &self.fdcan1en())
.field("usbsmen", &self.usbsmen())
.field("spi2smen", &self.spi2smen())
.field("crssmen", &self.crssmen())
.field("usart2smen", &self.usart2smen())
.field("usart3smen", &self.usart3smen())
.field("usart4smen", &self.usart4smen())
.field("i2c1smen", &self.i2c1smen())
.field("i2c2smen", &self.i2c2smen())
.field("dbgsmen", &self.dbgsmen())
.field("pwrsmen", &self.pwrsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbsmenr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbsmenr1 {{ tim2smen: {=bool:?}, tim3smen: {=bool:?}, rtcapbsmen: {=bool:?}, wwdgsmen: {=bool:?}, fdcan1en: {=bool:?}, usbsmen: {=bool:?}, spi2smen: {=bool:?}, crssmen: {=bool:?}, usart2smen: {=bool:?}, usart3smen: {=bool:?}, usart4smen: {=bool:?}, i2c1smen: {=bool:?}, i2c2smen: {=bool:?}, dbgsmen: {=bool:?}, pwrsmen: {=bool:?} }}" , self . tim2smen () , self . tim3smen () , self . rtcapbsmen () , self . wwdgsmen () , self . fdcan1en () , self . usbsmen () , self . spi2smen () , self . crssmen () , self . usart2smen () , self . usart3smen () , self . usart4smen () , self . i2c1smen () , self . i2c2smen () , self . dbgsmen () , self . pwrsmen ())
}
}
#[doc = "RCC APB peripheral clock enable in Sleep/Stop mode register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbsmenr2(pub u32);
impl Apbsmenr2 {
#[doc = "SYSCFG clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub const fn syscfgsmen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "SYSCFG clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub fn set_syscfgsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM1 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn tim1smen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_tim1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn spi1smen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_spi1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub const fn usart1smen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 clock enable during Sleep and Stop modes Set and cleared by software."]
#[inline(always)]
pub fn set_usart1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM14 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn tim14smen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "TIM14 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_tim14smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "TIM15 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn tim15smen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "TIM15 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_tim15smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "TIM16 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn tim16smen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_tim16smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM16 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn tim17smen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_tim17smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "ADC clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn adc1smen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "ADC clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_adc1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Apbsmenr2 {
#[inline(always)]
fn default() -> Apbsmenr2 {
Apbsmenr2(0)
}
}
impl core::fmt::Debug for Apbsmenr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbsmenr2")
.field("syscfgsmen", &self.syscfgsmen())
.field("tim1smen", &self.tim1smen())
.field("spi1smen", &self.spi1smen())
.field("usart1smen", &self.usart1smen())
.field("tim14smen", &self.tim14smen())
.field("tim15smen", &self.tim15smen())
.field("tim16smen", &self.tim16smen())
.field("tim17smen", &self.tim17smen())
.field("adc1smen", &self.adc1smen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbsmenr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbsmenr2 {{ syscfgsmen: {=bool:?}, tim1smen: {=bool:?}, spi1smen: {=bool:?}, usart1smen: {=bool:?}, tim14smen: {=bool:?}, tim15smen: {=bool:?}, tim16smen: {=bool:?}, tim17smen: {=bool:?}, adc1smen: {=bool:?} }}" , self . syscfgsmen () , self . tim1smen () , self . spi1smen () , self . usart1smen () , self . tim14smen () , self . tim15smen () , self . tim16smen () , self . tim17smen () , self . adc1smen ())
}
}
#[doc = "RCC peripherals independent clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ccipr(pub u32);
impl Ccipr {
#[doc = "USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows:"]
#[inline(always)]
pub const fn usart1sel(&self) -> super::vals::Usart1sel {
let val = (self.0 >> 0usize) & 0x03;
super::vals::Usart1sel::from_bits(val as u8)
}
#[doc = "USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows:"]
#[inline(always)]
pub fn set_usart1sel(&mut self, val: super::vals::Usart1sel) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows:"]
#[inline(always)]
pub const fn i2c1sel(&self) -> super::vals::I2c1sel {
let val = (self.0 >> 12usize) & 0x03;
super::vals::I2c1sel::from_bits(val as u8)
}
#[doc = "I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows:"]
#[inline(always)]
pub fn set_i2c1sel(&mut self, val: super::vals::I2c1sel) {
self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
}
#[doc = "I2S1 clock source selection This bitfield is controlled by software to select I2S1 clock source as follows:"]
#[inline(always)]
pub const fn i2s1sel(&self) -> super::vals::I2s1sel {
let val = (self.0 >> 14usize) & 0x03;
super::vals::I2s1sel::from_bits(val as u8)
}
#[doc = "I2S1 clock source selection This bitfield is controlled by software to select I2S1 clock source as follows:"]
#[inline(always)]
pub fn set_i2s1sel(&mut self, val: super::vals::I2s1sel) {
self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize);
}
#[doc = "ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC:"]
#[inline(always)]
pub const fn adc1sel(&self) -> super::vals::Adcsel {
let val = (self.0 >> 30usize) & 0x03;
super::vals::Adcsel::from_bits(val as u8)
}
#[doc = "ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC:"]
#[inline(always)]
pub fn set_adc1sel(&mut self, val: super::vals::Adcsel) {
self.0 = (self.0 & !(0x03 << 30usize)) | (((val.to_bits() as u32) & 0x03) << 30usize);
}
}
impl Default for Ccipr {
#[inline(always)]
fn default() -> Ccipr {
Ccipr(0)
}
}
impl core::fmt::Debug for Ccipr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ccipr")
.field("usart1sel", &self.usart1sel())
.field("i2c1sel", &self.i2c1sel())
.field("i2s1sel", &self.i2s1sel())
.field("adc1sel", &self.adc1sel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ccipr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ccipr {{ usart1sel: {:?}, i2c1sel: {:?}, i2s1sel: {:?}, adc1sel: {:?} }}",
self.usart1sel(),
self.i2c1sel(),
self.i2s1sel(),
self.adc1sel()
)
}
}
#[doc = "RCC peripherals independent clock configuration register 2."]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ccipr2(pub u32);
impl Ccipr2 {
#[doc = "USB clock source selection Set and cleared by software."]
#[inline(always)]
pub const fn usbsel(&self) -> super::vals::Usbsel {
let val = (self.0 >> 12usize) & 0x01;
super::vals::Usbsel::from_bits(val as u8)
}
#[doc = "USB clock source selection Set and cleared by software."]
#[inline(always)]
pub fn set_usbsel(&mut self, val: super::vals::Usbsel) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize);
}
}
impl Default for Ccipr2 {
#[inline(always)]
fn default() -> Ccipr2 {
Ccipr2(0)
}
}
impl core::fmt::Debug for Ccipr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ccipr2").field("usbsel", &self.usbsel()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ccipr2 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Ccipr2 {{ usbsel: {:?} }}", self.usbsel())
}
}
#[doc = "RCC clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfgr(pub u32);
impl Cfgr {
#[doc = "System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected."]
#[inline(always)]
pub const fn sw(&self) -> super::vals::Sw {
let val = (self.0 >> 0usize) & 0x07;
super::vals::Sw::from_bits(val as u8)
}
#[doc = "System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected."]
#[inline(always)]
pub fn set_sw(&mut self, val: super::vals::Sw) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
}
#[doc = "System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved"]
#[inline(always)]
pub const fn sws(&self) -> super::vals::Sw {
let val = (self.0 >> 3usize) & 0x07;
super::vals::Sw::from_bits(val as u8)
}
#[doc = "System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved"]
#[inline(always)]
pub fn set_sws(&mut self, val: super::vals::Sw) {
self.0 = (self.0 & !(0x07 << 3usize)) | (((val.to_bits() as u32) & 0x07) << 3usize);
}
#[doc = "AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1"]
#[inline(always)]
pub const fn hpre(&self) -> super::vals::Hpre {
let val = (self.0 >> 8usize) & 0x0f;
super::vals::Hpre::from_bits(val as u8)
}
#[doc = "AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1"]
#[inline(always)]
pub fn set_hpre(&mut self, val: super::vals::Hpre) {
self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize);
}
#[doc = "APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1"]
#[inline(always)]
pub const fn ppre(&self) -> super::vals::Ppre {
let val = (self.0 >> 12usize) & 0x07;
super::vals::Ppre::from_bits(val as u8)
}
#[doc = "APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1"]
#[inline(always)]
pub fn set_ppre(&mut self, val: super::vals::Ppre) {
self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize);
}
#[doc = "Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching."]
#[inline(always)]
pub const fn mco2sel(&self) -> super::vals::Mcosel {
let val = (self.0 >> 16usize) & 0x0f;
super::vals::Mcosel::from_bits(val as u8)
}
#[doc = "Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching."]
#[inline(always)]
pub fn set_mco2sel(&mut self, val: super::vals::Mcosel) {
self.0 = (self.0 & !(0x0f << 16usize)) | (((val.to_bits() as u32) & 0x0f) << 16usize);
}
#[doc = "Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... It is highly recommended to set this field before the MCO2 output is enabled."]
#[inline(always)]
pub const fn mco2pre(&self) -> super::vals::Mcopre {
let val = (self.0 >> 20usize) & 0x0f;
super::vals::Mcopre::from_bits(val as u8)
}
#[doc = "Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... It is highly recommended to set this field before the MCO2 output is enabled."]
#[inline(always)]
pub fn set_mco2pre(&mut self, val: super::vals::Mcopre) {
self.0 = (self.0 & !(0x0f << 20usize)) | (((val.to_bits() as u32) & 0x0f) << 20usize);
}
#[doc = "Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO."]
#[inline(always)]
pub const fn mco1sel(&self) -> super::vals::Mcosel {
let val = (self.0 >> 24usize) & 0x0f;
super::vals::Mcosel::from_bits(val as u8)
}
#[doc = "Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO."]
#[inline(always)]
pub fn set_mco1sel(&mut self, val: super::vals::Mcosel) {
self.0 = (self.0 & !(0x0f << 24usize)) | (((val.to_bits() as u32) & 0x0f) << 24usize);
}
#[doc = "Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... It is highly recommended to set this field before the MCO output is enabled."]
#[inline(always)]
pub const fn mco1pre(&self) -> super::vals::Mcopre {
let val = (self.0 >> 28usize) & 0x0f;
super::vals::Mcopre::from_bits(val as u8)
}
#[doc = "Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... It is highly recommended to set this field before the MCO output is enabled."]
#[inline(always)]
pub fn set_mco1pre(&mut self, val: super::vals::Mcopre) {
self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
}
}
impl Default for Cfgr {
#[inline(always)]
fn default() -> Cfgr {
Cfgr(0)
}
}
impl core::fmt::Debug for Cfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cfgr")
.field("sw", &self.sw())
.field("sws", &self.sws())
.field("hpre", &self.hpre())
.field("ppre", &self.ppre())
.field("mco2sel", &self.mco2sel())
.field("mco2pre", &self.mco2pre())
.field("mco1sel", &self.mco1sel())
.field("mco1pre", &self.mco1pre())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cfgr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cfgr {{ sw: {:?}, sws: {:?}, hpre: {:?}, ppre: {:?}, mco2sel: {:?}, mco2pre: {:?}, mco1sel: {:?}, mco1pre: {:?} }}" , self . sw () , self . sws () , self . hpre () , self . ppre () , self . mco2sel () , self . mco2pre () , self . mco1sel () , self . mco1pre ())
}
}
#[doc = "RCC clock interrupt clear register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cicr(pub u32);
impl Cicr {
#[doc = "LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag."]
#[inline(always)]
pub const fn lsirdyc(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag."]
#[inline(always)]
pub fn set_lsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag."]
#[inline(always)]
pub const fn lserdyc(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag."]
#[inline(always)]
pub fn set_lserdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "HSI48 ready interrupt clear This bit is set software to clear the HSI48RDYF flag. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn hsi48rdyc(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "HSI48 ready interrupt clear This bit is set software to clear the HSI48RDYF flag. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_hsi48rdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag."]
#[inline(always)]
pub const fn hsirdyc(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag."]
#[inline(always)]
pub fn set_hsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag."]
#[inline(always)]
pub const fn hserdyc(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag."]
#[inline(always)]
pub fn set_hserdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag."]
#[inline(always)]
pub const fn cssc(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag."]
#[inline(always)]
pub fn set_cssc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag."]
#[inline(always)]
pub const fn lsecssc(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag."]
#[inline(always)]
pub fn set_lsecssc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
}
impl Default for Cicr {
#[inline(always)]
fn default() -> Cicr {
Cicr(0)
}
}
impl core::fmt::Debug for Cicr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cicr")
.field("lsirdyc", &self.lsirdyc())
.field("lserdyc", &self.lserdyc())
.field("hsi48rdyc", &self.hsi48rdyc())
.field("hsirdyc", &self.hsirdyc())
.field("hserdyc", &self.hserdyc())
.field("cssc", &self.cssc())
.field("lsecssc", &self.lsecssc())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cicr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cicr {{ lsirdyc: {=bool:?}, lserdyc: {=bool:?}, hsi48rdyc: {=bool:?}, hsirdyc: {=bool:?}, hserdyc: {=bool:?}, cssc: {=bool:?}, lsecssc: {=bool:?} }}" , self . lsirdyc () , self . lserdyc () , self . hsi48rdyc () , self . hsirdyc () , self . hserdyc () , self . cssc () , self . lsecssc ())
}
}
#[doc = "RCC clock interrupt enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cier(pub u32);
impl Cier {
#[doc = "LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:"]
#[inline(always)]
pub const fn lsirdyie(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:"]
#[inline(always)]
pub fn set_lsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:"]
#[inline(always)]
pub const fn lserdyie(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:"]
#[inline(always)]
pub fn set_lserdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization: Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn hsi48rdyie(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization: Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_hsi48rdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization:"]
#[inline(always)]
pub const fn hsirdyie(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization:"]
#[inline(always)]
pub fn set_hsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:"]
#[inline(always)]
pub const fn hserdyie(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:"]
#[inline(always)]
pub fn set_hserdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
}
impl Default for Cier {
#[inline(always)]
fn default() -> Cier {
Cier(0)
}
}
impl core::fmt::Debug for Cier {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cier")
.field("lsirdyie", &self.lsirdyie())
.field("lserdyie", &self.lserdyie())
.field("hsi48rdyie", &self.hsi48rdyie())
.field("hsirdyie", &self.hsirdyie())
.field("hserdyie", &self.hserdyie())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cier {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cier {{ lsirdyie: {=bool:?}, lserdyie: {=bool:?}, hsi48rdyie: {=bool:?}, hsirdyie: {=bool:?}, hserdyie: {=bool:?} }}" , self . lsirdyie () , self . lserdyie () , self . hsi48rdyie () , self . hsirdyie () , self . hserdyie ())
}
}
#[doc = "RCC clock interrupt flag register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cifr(pub u32);
impl Cifr {
#[doc = "LSI ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit."]
#[inline(always)]
pub const fn lsirdyf(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit."]
#[inline(always)]
pub fn set_lsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit."]
#[inline(always)]
pub const fn lserdyf(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit."]
#[inline(always)]
pub fn set_lserdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set as a response to setting HSI48ON (refer to RCC clock control register (CR)). When HSI48ON is not set but the HSI48 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSI48RDYC bit. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn hsi48rdyf(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set as a response to setting HSI48ON (refer to RCC clock control register (CR)). When HSI48ON is not set but the HSI48 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSI48RDYC bit. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_hsi48rdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "HSI ready interrupt flag This flag indicates a pending interrupt upon HSI clock getting ready. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit."]
#[inline(always)]
pub const fn hsirdyf(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt flag This flag indicates a pending interrupt upon HSI clock getting ready. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit."]
#[inline(always)]
pub fn set_hsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt flag This flag indicates a pending interrupt upon HSE clock getting ready. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit."]
#[inline(always)]
pub const fn hserdyf(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt flag This flag indicates a pending interrupt upon HSE clock getting ready. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit."]
#[inline(always)]
pub fn set_hserdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "HSE clock security system interrupt flag This flag indicates a pending interrupt upon HSE clock failure. Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit."]
#[inline(always)]
pub const fn cssf(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "HSE clock security system interrupt flag This flag indicates a pending interrupt upon HSE clock failure. Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit."]
#[inline(always)]
pub fn set_cssf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "LSE clock security system interrupt flag This flag indicates a pending interrupt upon LSE clock failure. Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit."]
#[inline(always)]
pub const fn lsecssf(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LSE clock security system interrupt flag This flag indicates a pending interrupt upon LSE clock failure. Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit."]
#[inline(always)]
pub fn set_lsecssf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
}
impl Default for Cifr {
#[inline(always)]
fn default() -> Cifr {
Cifr(0)
}
}
impl core::fmt::Debug for Cifr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cifr")
.field("lsirdyf", &self.lsirdyf())
.field("lserdyf", &self.lserdyf())
.field("hsi48rdyf", &self.hsi48rdyf())
.field("hsirdyf", &self.hsirdyf())
.field("hserdyf", &self.hserdyf())
.field("cssf", &self.cssf())
.field("lsecssf", &self.lsecssf())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cifr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cifr {{ lsirdyf: {=bool:?}, lserdyf: {=bool:?}, hsi48rdyf: {=bool:?}, hsirdyf: {=bool:?}, hserdyf: {=bool:?}, cssf: {=bool:?}, lsecssf: {=bool:?} }}" , self . lsirdyf () , self . lserdyf () , self . hsi48rdyf () , self . hsirdyf () , self . hserdyf () , self . cssf () , self . lsecssf ())
}
}
#[doc = "RCC clock control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr(pub u32);
impl Cr {
#[doc = "Clock division factor for system clock Set and cleared by software. SYSCLK is result of the division by: Note: This bitfield is only available on STM32C071xx."]
#[inline(always)]
pub const fn sysdiv(&self) -> super::vals::Sysdiv {
let val = (self.0 >> 2usize) & 0x07;
super::vals::Sysdiv::from_bits(val as u8)
}
#[doc = "Clock division factor for system clock Set and cleared by software. SYSCLK is result of the division by: Note: This bitfield is only available on STM32C071xx."]
#[inline(always)]
pub fn set_sysdiv(&mut self, val: super::vals::Sysdiv) {
self.0 = (self.0 & !(0x07 << 2usize)) | (((val.to_bits() as u32) & 0x07) << 2usize);
}
#[doc = "HSI kernel clock division factor This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:"]
#[inline(always)]
pub const fn hsikerdiv(&self) -> super::vals::Hsikerdiv {
let val = (self.0 >> 5usize) & 0x07;
super::vals::Hsikerdiv::from_bits(val as u8)
}
#[doc = "HSI kernel clock division factor This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:"]
#[inline(always)]
pub fn set_hsikerdiv(&mut self, val: super::vals::Hsikerdiv) {
self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
}
#[doc = "HSI clock enable Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked with a clock derived from HSI. This includes the exit from low-power modes and the system clock fall-back to HSI upon failing HSE oscillator clock selected as system clock source."]
#[inline(always)]
pub const fn hsion(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "HSI clock enable Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked with a clock derived from HSI. This includes the exit from low-power modes and the system clock fall-back to HSI upon failing HSE oscillator clock selected as system clock source."]
#[inline(always)]
pub fn set_hsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "HSI always-enable for peripheral kernels. Set and cleared by software. Setting the bit activates the HSI oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI as kernel clock. Note: Keeping the HSI active in Stop mode allows speeding up the serial interface communication as the HSI clock is ready immediately upon exiting Stop mode."]
#[inline(always)]
pub const fn hsikeron(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "HSI always-enable for peripheral kernels. Set and cleared by software. Setting the bit activates the HSI oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI as kernel clock. Note: Keeping the HSI active in Stop mode allows speeding up the serial interface communication as the HSI clock is ready immediately upon exiting Stop mode."]
#[inline(always)]
pub fn set_hsikeron(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "HSI clock ready flag Set by hardware when the HSI oscillator is enabled through HSION and ready to use (stable). Note: Upon clearing HSION, HSIRDY goes low after six HSI clock cycles."]
#[inline(always)]
pub const fn hsirdy(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "HSI clock ready flag Set by hardware when the HSI oscillator is enabled through HSION and ready to use (stable). Note: Upon clearing HSION, HSIRDY goes low after six HSI clock cycles."]
#[inline(always)]
pub fn set_hsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "HSI clock division factor This bitfield controlled by software sets the division factor of the HSI clock divider to produce HSISYS clock:"]
#[inline(always)]
pub const fn hsidiv(&self) -> super::vals::Hsidiv {
let val = (self.0 >> 11usize) & 0x07;
super::vals::Hsidiv::from_bits(val as u8)
}
#[doc = "HSI clock division factor This bitfield controlled by software sets the division factor of the HSI clock divider to produce HSISYS clock:"]
#[inline(always)]
pub fn set_hsidiv(&mut self, val: super::vals::Hsidiv) {
self.0 = (self.0 & !(0x07 << 11usize)) | (((val.to_bits() as u32) & 0x07) << 11usize);
}
#[doc = "HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock."]
#[inline(always)]
pub const fn hseon(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock."]
#[inline(always)]
pub fn set_hseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable and ready for use. Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles."]
#[inline(always)]
pub const fn hserdy(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable and ready for use. Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles."]
#[inline(always)]
pub fn set_hserdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "HSE crystal oscillator bypass Set and cleared by software. When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled."]
#[inline(always)]
pub const fn hsebyp(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "HSE crystal oscillator bypass Set and cleared by software. When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled."]
#[inline(always)]
pub fn set_hsebyp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "Clock security system enable Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset."]
#[inline(always)]
pub const fn csson(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "Clock security system enable Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset."]
#[inline(always)]
pub fn set_csson(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "HSI48 clock enable Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked from HSI48. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn hsi48on(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "HSI48 clock enable Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked from HSI48. Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_hsi48on(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "HSI48 clock ready flag Set by hardware when the HSI48 oscillator is enabled through HSI48ON and ready to use (stable). Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub const fn hsi48rdy(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "HSI48 clock ready flag Set by hardware when the HSI48 oscillator is enabled through HSI48ON and ready to use (stable). Note: Only applicable on STM32C071xx, reserved on other devices."]
#[inline(always)]
pub fn set_hsi48rdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
}
impl Default for Cr {
#[inline(always)]
fn default() -> Cr {
Cr(0)
}
}
impl core::fmt::Debug for Cr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cr")
.field("sysdiv", &self.sysdiv())
.field("hsikerdiv", &self.hsikerdiv())
.field("hsion", &self.hsion())
.field("hsikeron", &self.hsikeron())
.field("hsirdy", &self.hsirdy())
.field("hsidiv", &self.hsidiv())
.field("hseon", &self.hseon())
.field("hserdy", &self.hserdy())
.field("hsebyp", &self.hsebyp())
.field("csson", &self.csson())
.field("hsi48on", &self.hsi48on())
.field("hsi48rdy", &self.hsi48rdy())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cr {{ sysdiv: {:?}, hsikerdiv: {:?}, hsion: {=bool:?}, hsikeron: {=bool:?}, hsirdy: {=bool:?}, hsidiv: {:?}, hseon: {=bool:?}, hserdy: {=bool:?}, hsebyp: {=bool:?}, csson: {=bool:?}, hsi48on: {=bool:?}, hsi48rdy: {=bool:?} }}" , self . sysdiv () , self . hsikerdiv () , self . hsion () , self . hsikeron () , self . hsirdy () , self . hsidiv () , self . hseon () , self . hserdy () , self . hsebyp () , self . csson () , self . hsi48on () , self . hsi48rdy ())
}
}
#[doc = "RCC clock recovery RC register."]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Crrcr(pub u32);
impl Crrcr {
#[doc = "HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value."]
#[inline(always)]
pub const fn hsi48cal(&self) -> u16 {
let val = (self.0 >> 0usize) & 0x01ff;
val as u16
}
#[doc = "HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value."]
#[inline(always)]
pub fn set_hsi48cal(&mut self, val: u16) {
self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
}
}
impl Default for Crrcr {
#[inline(always)]
fn default() -> Crrcr {
Crrcr(0)
}
}
impl core::fmt::Debug for Crrcr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Crrcr").field("hsi48cal", &self.hsi48cal()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Crrcr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Crrcr {{ hsi48cal: {=u16:?} }}", self.hsi48cal())
}
}
#[doc = "RCC control/status register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csr1(pub u32);
impl Csr1 {
#[doc = "LSE oscillator enable Set and cleared by software to enable LSE oscillator:"]
#[inline(always)]
pub const fn lseon(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator enable Set and cleared by software to enable LSE oscillator:"]
#[inline(always)]
pub fn set_lseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles."]
#[inline(always)]
pub const fn lserdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles."]
#[inline(always)]
pub fn set_lserdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0)."]
#[inline(always)]
pub const fn lsebyp(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0)."]
#[inline(always)]
pub fn set_lsebyp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode."]
#[inline(always)]
pub const fn lsedrv(&self) -> super::vals::Lsedrv {
let val = (self.0 >> 3usize) & 0x03;
super::vals::Lsedrv::from_bits(val as u8)
}
#[doc = "LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode."]
#[inline(always)]
pub fn set_lsedrv(&mut self, val: super::vals::Lsedrv) {
self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
}
#[doc = "CSS on LSE enable Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit."]
#[inline(always)]
pub const fn lsecsson(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "CSS on LSE enable Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit."]
#[inline(always)]
pub fn set_lsecsson(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 32 kHz oscillator (LSE):"]
#[inline(always)]
pub const fn lsecssd(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 32 kHz oscillator (LSE):"]
#[inline(always)]
pub fn set_lsecssd(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00."]
#[inline(always)]
pub const fn rtcsel(&self) -> super::vals::Rtcsel {
let val = (self.0 >> 8usize) & 0x03;
super::vals::Rtcsel::from_bits(val as u8)
}
#[doc = "RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00."]
#[inline(always)]
pub fn set_rtcsel(&mut self, val: super::vals::Rtcsel) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
}
#[doc = "RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP."]
#[inline(always)]
pub const fn rtcen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP."]
#[inline(always)]
pub fn set_rtcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "RTC domain software reset Set and cleared by software to reset the RTC domain:"]
#[inline(always)]
pub const fn rtcrst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "RTC domain software reset Set and cleared by software to reset the RTC domain:"]
#[inline(always)]
pub fn set_rtcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Low-speed clock output (LSCO) enable Set and cleared by software."]
#[inline(always)]
pub const fn lscoen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Low-speed clock output (LSCO) enable Set and cleared by software."]
#[inline(always)]
pub fn set_lscoen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Low-speed clock output selection Set and cleared by software to select the low-speed output clock:"]
#[inline(always)]
pub const fn lscosel(&self) -> super::vals::Lscosel {
let val = (self.0 >> 25usize) & 0x01;
super::vals::Lscosel::from_bits(val as u8)
}
#[doc = "Low-speed clock output selection Set and cleared by software to select the low-speed output clock:"]
#[inline(always)]
pub fn set_lscosel(&mut self, val: super::vals::Lscosel) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32) & 0x01) << 25usize);
}
}
impl Default for Csr1 {
#[inline(always)]
fn default() -> Csr1 {
Csr1(0)
}
}
impl core::fmt::Debug for Csr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Csr1")
.field("lseon", &self.lseon())
.field("lserdy", &self.lserdy())
.field("lsebyp", &self.lsebyp())
.field("lsedrv", &self.lsedrv())
.field("lsecsson", &self.lsecsson())
.field("lsecssd", &self.lsecssd())
.field("rtcsel", &self.rtcsel())
.field("rtcen", &self.rtcen())
.field("rtcrst", &self.rtcrst())
.field("lscoen", &self.lscoen())
.field("lscosel", &self.lscosel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Csr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Csr1 {{ lseon: {=bool:?}, lserdy: {=bool:?}, lsebyp: {=bool:?}, lsedrv: {:?}, lsecsson: {=bool:?}, lsecssd: {=bool:?}, rtcsel: {:?}, rtcen: {=bool:?}, rtcrst: {=bool:?}, lscoen: {=bool:?}, lscosel: {:?} }}" , self . lseon () , self . lserdy () , self . lsebyp () , self . lsedrv () , self . lsecsson () , self . lsecssd () , self . rtcsel () , self . rtcen () , self . rtcrst () , self . lscoen () , self . lscosel ())
}
}
#[doc = "RCC control/status register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csr2(pub u32);
impl Csr2 {
#[doc = "LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator:"]
#[inline(always)]
pub const fn lsion(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator:"]
#[inline(always)]
pub fn set_lsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC."]
#[inline(always)]
pub const fn lsirdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC."]
#[inline(always)]
pub fn set_lsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Remove reset flags Set by software to clear the reset flags."]
#[inline(always)]
pub const fn rmvf(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Remove reset flags Set by software to clear the reset flags."]
#[inline(always)]
pub fn set_rmvf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub const fn oblrstf(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub fn set_oblrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub const fn pinrstf(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub fn set_pinrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub const fn pwrrstf(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub fn set_pwrrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub const fn sftrstf(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub fn set_sftrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub const fn iwdgrstf(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub fn set_iwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub const fn wwdgrstf(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit."]
#[inline(always)]
pub fn set_wwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared."]
#[inline(always)]
pub const fn lpwrrstf(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared."]
#[inline(always)]
pub fn set_lpwrrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Csr2 {
#[inline(always)]
fn default() -> Csr2 {
Csr2(0)
}
}
impl core::fmt::Debug for Csr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Csr2")
.field("lsion", &self.lsion())
.field("lsirdy", &self.lsirdy())
.field("rmvf", &self.rmvf())
.field("oblrstf", &self.oblrstf())
.field("pinrstf", &self.pinrstf())
.field("pwrrstf", &self.pwrrstf())
.field("sftrstf", &self.sftrstf())
.field("iwdgrstf", &self.iwdgrstf())
.field("wwdgrstf", &self.wwdgrstf())
.field("lpwrrstf", &self.lpwrrstf())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Csr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Csr2 {{ lsion: {=bool:?}, lsirdy: {=bool:?}, rmvf: {=bool:?}, oblrstf: {=bool:?}, pinrstf: {=bool:?}, pwrrstf: {=bool:?}, sftrstf: {=bool:?}, iwdgrstf: {=bool:?}, wwdgrstf: {=bool:?}, lpwrrstf: {=bool:?} }}" , self . lsion () , self . lsirdy () , self . rmvf () , self . oblrstf () , self . pinrstf () , self . pwrrstf () , self . sftrstf () , self . iwdgrstf () , self . wwdgrstf () , self . lpwrrstf ())
}
}
#[doc = "RCC I/O port clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Gpioenr(pub u32);
impl Gpioenr {
#[doc = "I/O port A clock enable This bit is set and cleared by software."]
#[inline(always)]
pub const fn gpioaen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "I/O port A clock enable This bit is set and cleared by software."]
#[inline(always)]
pub fn set_gpioaen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "I/O port B clock enable This bit is set and cleared by software."]
#[inline(always)]
pub const fn gpioben(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "I/O port B clock enable This bit is set and cleared by software."]
#[inline(always)]
pub fn set_gpioben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "I/O port C clock enable This bit is set and cleared by software."]
#[inline(always)]
pub const fn gpiocen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "I/O port C clock enable This bit is set and cleared by software."]
#[inline(always)]
pub fn set_gpiocen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "I/O port D clock enable This bit is set and cleared by software."]
#[inline(always)]
pub const fn gpioden(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "I/O port D clock enable This bit is set and cleared by software."]
#[inline(always)]
pub fn set_gpioden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "I/O port F clock enable This bit is set and cleared by software."]
#[inline(always)]
pub const fn gpiofen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "I/O port F clock enable This bit is set and cleared by software."]
#[inline(always)]
pub fn set_gpiofen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
}
impl Default for Gpioenr {
#[inline(always)]
fn default() -> Gpioenr {
Gpioenr(0)
}
}
impl core::fmt::Debug for Gpioenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpioenr")
.field("gpioaen", &self.gpioaen())
.field("gpioben", &self.gpioben())
.field("gpiocen", &self.gpiocen())
.field("gpioden", &self.gpioden())
.field("gpiofen", &self.gpiofen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Gpioenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Gpioenr {{ gpioaen: {=bool:?}, gpioben: {=bool:?}, gpiocen: {=bool:?}, gpioden: {=bool:?}, gpiofen: {=bool:?} }}" , self . gpioaen () , self . gpioben () , self . gpiocen () , self . gpioden () , self . gpiofen ())
}
}
#[doc = "RCC I/O port reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Gpiorstr(pub u32);
impl Gpiorstr {
#[doc = "I/O port A reset This bit is set and cleared by software."]
#[inline(always)]
pub const fn gpioarst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "I/O port A reset This bit is set and cleared by software."]
#[inline(always)]
pub fn set_gpioarst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "I/O port B reset This bit is set and cleared by software."]
#[inline(always)]
pub const fn gpiobrst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "I/O port B reset This bit is set and cleared by software."]
#[inline(always)]
pub fn set_gpiobrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "I/O port C reset This bit is set and cleared by software."]
#[inline(always)]
pub const fn gpiocrst(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "I/O port C reset This bit is set and cleared by software."]
#[inline(always)]
pub fn set_gpiocrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "I/O port D reset This bit is set and cleared by software."]
#[inline(always)]
pub const fn gpiodrst(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "I/O port D reset This bit is set and cleared by software."]
#[inline(always)]
pub fn set_gpiodrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "I/O port F reset This bit is set and cleared by software."]
#[inline(always)]
pub const fn gpiofrst(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "I/O port F reset This bit is set and cleared by software."]
#[inline(always)]
pub fn set_gpiofrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
}
impl Default for Gpiorstr {
#[inline(always)]
fn default() -> Gpiorstr {
Gpiorstr(0)
}
}
impl core::fmt::Debug for Gpiorstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpiorstr")
.field("gpioarst", &self.gpioarst())
.field("gpiobrst", &self.gpiobrst())
.field("gpiocrst", &self.gpiocrst())
.field("gpiodrst", &self.gpiodrst())
.field("gpiofrst", &self.gpiofrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Gpiorstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Gpiorstr {{ gpioarst: {=bool:?}, gpiobrst: {=bool:?}, gpiocrst: {=bool:?}, gpiodrst: {=bool:?}, gpiofrst: {=bool:?} }}" , self . gpioarst () , self . gpiobrst () , self . gpiocrst () , self . gpiodrst () , self . gpiofrst ())
}
}
#[doc = "RCC I/O port in Sleep mode clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Gpiosmenr(pub u32);
impl Gpiosmenr {
#[doc = "I/O port A clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn gpioasmen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "I/O port A clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_gpioasmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "I/O port B clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn gpiobsmen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "I/O port B clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_gpiobsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "I/O port C clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn gpiocsmen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "I/O port C clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_gpiocsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "I/O port D clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn gpiodsmen(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "I/O port D clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_gpiodsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "I/O port F clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub const fn gpiofsmen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "I/O port F clock enable during Sleep mode Set and cleared by software."]
#[inline(always)]
pub fn set_gpiofsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
}
impl Default for Gpiosmenr {
#[inline(always)]
fn default() -> Gpiosmenr {
Gpiosmenr(0)
}
}
impl core::fmt::Debug for Gpiosmenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpiosmenr")
.field("gpioasmen", &self.gpioasmen())
.field("gpiobsmen", &self.gpiobsmen())
.field("gpiocsmen", &self.gpiocsmen())
.field("gpiodsmen", &self.gpiodsmen())
.field("gpiofsmen", &self.gpiofsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Gpiosmenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Gpiosmenr {{ gpioasmen: {=bool:?}, gpiobsmen: {=bool:?}, gpiocsmen: {=bool:?}, gpiodsmen: {=bool:?}, gpiofsmen: {=bool:?} }}" , self . gpioasmen () , self . gpiobsmen () , self . gpiocsmen () , self . gpiodsmen () , self . gpiofsmen ())
}
}
#[doc = "RCC internal clock source calibration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Icscr(pub u32);
impl Icscr {
#[doc = "HSI clock calibration This bitfield directly acts on the HSI clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM\\[6:0\\]
bitfield. In the factory, the internal number is set to calibrate the HSI clock frequency to 48 MHz (with HSITRIM\\[6:0\\]
left at its reset value). Refer to the device datasheet for HSI calibration accuracy and for the frequency trimming granularity. Note: The trimming effect presents discontinuities at HSICAL\\[7:0\\]
multiples of 64."]
#[inline(always)]
pub const fn hsical(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[doc = "HSI clock calibration This bitfield directly acts on the HSI clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM\\[6:0\\]
bitfield. In the factory, the internal number is set to calibrate the HSI clock frequency to 48 MHz (with HSITRIM\\[6:0\\]
left at its reset value). Refer to the device datasheet for HSI calibration accuracy and for the frequency trimming granularity. Note: The trimming effect presents discontinuities at HSICAL\\[7:0\\]
multiples of 64."]
#[inline(always)]
pub fn set_hsical(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
#[doc = "HSI clock trimming The value of this bitfield contributes to the HSICAL\\[7:0\\]
bitfield value. It allows HSI clock frequency user trimming. The HSI frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value."]
#[inline(always)]
pub const fn hsitrim(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x7f;
val as u8
}
#[doc = "HSI clock trimming The value of this bitfield contributes to the HSICAL\\[7:0\\]
bitfield value. It allows HSI clock frequency user trimming. The HSI frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value."]
#[inline(always)]
pub fn set_hsitrim(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 8usize)) | (((val as u32) & 0x7f) << 8usize);
}
}
impl Default for Icscr {
#[inline(always)]
fn default() -> Icscr {
Icscr(0)
}
}
impl core::fmt::Debug for Icscr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Icscr")
.field("hsical", &self.hsical())
.field("hsitrim", &self.hsitrim())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Icscr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Icscr {{ hsical: {=u8:?}, hsitrim: {=u8:?} }}",
self.hsical(),
self.hsitrim()
)
}
}
}
pub mod vals {
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Adcsel {
#[doc = "System clock"]
SYS = 0x0,
_RESERVED_1 = 0x01,
#[doc = "HSIKER"]
HSIKER = 0x02,
_RESERVED_3 = 0x03,
}
impl Adcsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Adcsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Adcsel {
#[inline(always)]
fn from(val: u8) -> Adcsel {
Adcsel::from_bits(val)
}
}
impl From<Adcsel> for u8 {
#[inline(always)]
fn from(val: Adcsel) -> u8 {
Adcsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Hpre {
#[doc = "SYSCLK not divided"]
DIV1 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
_RESERVED_3 = 0x03,
_RESERVED_4 = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
#[doc = "SYSCLK is divided by 2"]
DIV2 = 0x08,
#[doc = "SYSCLK is divided by 4"]
DIV4 = 0x09,
#[doc = "SYSCLK is divided by 8"]
DIV8 = 0x0a,
#[doc = "SYSCLK is divided by 16"]
DIV16 = 0x0b,
#[doc = "SYSCLK is divided by 64"]
DIV64 = 0x0c,
#[doc = "SYSCLK is divided by 128"]
DIV128 = 0x0d,
#[doc = "SYSCLK is divided by 256"]
DIV256 = 0x0e,
#[doc = "SYSCLK is divided by 512"]
DIV512 = 0x0f,
}
impl Hpre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Hpre {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Hpre {
#[inline(always)]
fn from(val: u8) -> Hpre {
Hpre::from_bits(val)
}
}
impl From<Hpre> for u8 {
#[inline(always)]
fn from(val: Hpre) -> u8 {
Hpre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Hsidiv {
#[doc = "HSI clock is not divided"]
DIV1 = 0x0,
#[doc = "HSI clock is divided by 2"]
DIV2 = 0x01,
#[doc = "HSI clock is divided by 4"]
DIV4 = 0x02,
#[doc = "HSI clock is divided by 8"]
DIV8 = 0x03,
#[doc = "HSI clock is divided by 16"]
DIV16 = 0x04,
#[doc = "HSI clock is divided by 32"]
DIV32 = 0x05,
#[doc = "HSI clock is divided by 64"]
DIV64 = 0x06,
#[doc = "HSI clock is divided by 128"]
DIV128 = 0x07,
}
impl Hsidiv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Hsidiv {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Hsidiv {
#[inline(always)]
fn from(val: u8) -> Hsidiv {
Hsidiv::from_bits(val)
}
}
impl From<Hsidiv> for u8 {
#[inline(always)]
fn from(val: Hsidiv) -> u8 {
Hsidiv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Hsikerdiv {
#[doc = "1"]
DIV1 = 0x0,
#[doc = "2"]
DIV2 = 0x01,
#[doc = "3 (reset value)"]
DIV3 = 0x02,
#[doc = "4"]
DIV4 = 0x03,
#[doc = "5"]
DIV5 = 0x04,
#[doc = "6"]
DIV6 = 0x05,
#[doc = "7"]
DIV7 = 0x06,
#[doc = "8"]
DIV8 = 0x07,
}
impl Hsikerdiv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Hsikerdiv {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Hsikerdiv {
#[inline(always)]
fn from(val: u8) -> Hsikerdiv {
Hsikerdiv::from_bits(val)
}
}
impl From<Hsikerdiv> for u8 {
#[inline(always)]
fn from(val: Hsikerdiv) -> u8 {
Hsikerdiv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum I2c1sel {
#[doc = "PCLK"]
PCLK1 = 0x0,
#[doc = "SYSCLK"]
SYS = 0x01,
#[doc = "HSIKER"]
HSIKER = 0x02,
_RESERVED_3 = 0x03,
}
impl I2c1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> I2c1sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for I2c1sel {
#[inline(always)]
fn from(val: u8) -> I2c1sel {
I2c1sel::from_bits(val)
}
}
impl From<I2c1sel> for u8 {
#[inline(always)]
fn from(val: I2c1sel) -> u8 {
I2c1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum I2s1sel {
#[doc = "SYSCLK"]
SYS = 0x0,
_RESERVED_1 = 0x01,
#[doc = "HSIKER"]
HSIKER = 0x02,
#[doc = "I2S_CKIN"]
I2S_CKIN = 0x03,
}
impl I2s1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> I2s1sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for I2s1sel {
#[inline(always)]
fn from(val: u8) -> I2s1sel {
I2s1sel::from_bits(val)
}
}
impl From<I2s1sel> for u8 {
#[inline(always)]
fn from(val: I2s1sel) -> u8 {
I2s1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lscosel {
#[doc = "LSI"]
LSI = 0x0,
#[doc = "LSE"]
LSE = 0x01,
}
impl Lscosel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lscosel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lscosel {
#[inline(always)]
fn from(val: u8) -> Lscosel {
Lscosel::from_bits(val)
}
}
impl From<Lscosel> for u8 {
#[inline(always)]
fn from(val: Lscosel) -> u8 {
Lscosel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lsedrv {
#[doc = "Low driving capability"]
LOW = 0x0,
#[doc = "Medium low driving capability"]
MEDIUM_LOW = 0x01,
#[doc = "Medium high driving capability"]
MEDIUM_HIGH = 0x02,
#[doc = "High driving capability"]
HIGH = 0x03,
}
impl Lsedrv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lsedrv {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lsedrv {
#[inline(always)]
fn from(val: u8) -> Lsedrv {
Lsedrv::from_bits(val)
}
}
impl From<Lsedrv> for u8 {
#[inline(always)]
fn from(val: Lsedrv) -> u8 {
Lsedrv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Mcopre {
#[doc = "MCO2 not divided"]
DIV1 = 0x0,
#[doc = "MCO clock is divided by 2"]
DIV2 = 0x01,
#[doc = "MCO clock is divided by 4"]
DIV4 = 0x02,
#[doc = "MCO clock is divided by 8"]
DIV8 = 0x03,
#[doc = "MCO clock is divided divided by 16"]
DIV16 = 0x04,
#[doc = "MCO clock is divided divided by 32"]
DIV32 = 0x05,
#[doc = "MCO clock is divided divided by 64"]
DIV64 = 0x06,
#[doc = "MCO clock is divided divided by 128"]
DIV128 = 0x07,
#[doc = "MCO clock is divided divided by 256"]
DIV256 = 0x08,
#[doc = "MCO clock is divided divided by 512"]
DIV512 = 0x09,
#[doc = "MCO clock is divided divided by 1024"]
DIV1024 = 0x0a,
_RESERVED_b = 0x0b,
_RESERVED_c = 0x0c,
_RESERVED_d = 0x0d,
_RESERVED_e = 0x0e,
_RESERVED_f = 0x0f,
}
impl Mcopre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Mcopre {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Mcopre {
#[inline(always)]
fn from(val: u8) -> Mcopre {
Mcopre::from_bits(val)
}
}
impl From<Mcopre> for u8 {
#[inline(always)]
fn from(val: Mcopre) -> u8 {
Mcopre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Mcosel {
#[doc = "No clock, MCO output disabled"]
DISABLE = 0x0,
#[doc = "SYSCLK selected as MCO source"]
SYS = 0x01,
_RESERVED_2 = 0x02,
#[doc = "HSI selected as MCO source"]
HSI = 0x03,
#[doc = "HSE selected as MCO source"]
HSE = 0x04,
_RESERVED_5 = 0x05,
#[doc = "LSI selected as MCO source"]
LSI = 0x06,
#[doc = "LSE selected as MCO source"]
LSE = 0x07,
#[doc = "HSI48 selected as MCO source"]
HSI48 = 0x08,
_RESERVED_9 = 0x09,
_RESERVED_a = 0x0a,
_RESERVED_b = 0x0b,
_RESERVED_c = 0x0c,
_RESERVED_d = 0x0d,
_RESERVED_e = 0x0e,
_RESERVED_f = 0x0f,
}
impl Mcosel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Mcosel {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Mcosel {
#[inline(always)]
fn from(val: u8) -> Mcosel {
Mcosel::from_bits(val)
}
}
impl From<Mcosel> for u8 {
#[inline(always)]
fn from(val: Mcosel) -> u8 {
Mcosel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Ppre {
#[doc = "HCLK not divided"]
DIV1 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
_RESERVED_3 = 0x03,
#[doc = "HCLK is divided by 2"]
DIV2 = 0x04,
#[doc = "HCLK is divided by 4"]
DIV4 = 0x05,
#[doc = "HCLK is divided by 8"]
DIV8 = 0x06,
#[doc = "HCLK is divided by 16"]
DIV16 = 0x07,
}
impl Ppre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Ppre {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Ppre {
#[inline(always)]
fn from(val: u8) -> Ppre {
Ppre::from_bits(val)
}
}
impl From<Ppre> for u8 {
#[inline(always)]
fn from(val: Ppre) -> u8 {
Ppre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Rtcsel {
#[doc = "No clock used as RTC clock"]
DISABLE = 0x0,
#[doc = "LSE used as RTC clock"]
LSE = 0x01,
#[doc = "LSI used as RTC clock"]
LSI = 0x02,
#[doc = "HSE divided by 32 used as RTC clock"]
HSE_DIV_32 = 0x03,
}
impl Rtcsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Rtcsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Rtcsel {
#[inline(always)]
fn from(val: u8) -> Rtcsel {
Rtcsel::from_bits(val)
}
}
impl From<Rtcsel> for u8 {
#[inline(always)]
fn from(val: Rtcsel) -> u8 {
Rtcsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Sw {
#[doc = "HSISYS (HSI divided by HSIDIV) selected as system clock"]
HSISYS = 0x0,
#[doc = "HSE selected as system clock"]
HSE = 0x01,
_RESERVED_2 = 0x02,
#[doc = "LSI selected as system clock"]
LSI = 0x03,
#[doc = "LSE selected as system clock"]
LSE = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Sw {
#[inline(always)]
pub const fn from_bits(val: u8) -> Sw {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Sw {
#[inline(always)]
fn from(val: u8) -> Sw {
Sw::from_bits(val)
}
}
impl From<Sw> for u8 {
#[inline(always)]
fn from(val: Sw) -> u8 {
Sw::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Sysdiv {
#[doc = "1 (no division, reset value)."]
DIV1 = 0x0,
#[doc = "2."]
DIV2 = 0x01,
#[doc = "3."]
DIV3 = 0x02,
#[doc = "4."]
DIV4 = 0x03,
#[doc = "5."]
DIV5 = 0x04,
#[doc = "6."]
DIV6 = 0x05,
#[doc = "7."]
DIV7 = 0x06,
#[doc = "8."]
DIV8 = 0x07,
}
impl Sysdiv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Sysdiv {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Sysdiv {
#[inline(always)]
fn from(val: u8) -> Sysdiv {
Sysdiv::from_bits(val)
}
}
impl From<Sysdiv> for u8 {
#[inline(always)]
fn from(val: Sysdiv) -> u8 {
Sysdiv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Usart1sel {
#[doc = "PCLK"]
PCLK1 = 0x0,
#[doc = "SYSCLK"]
SYS = 0x01,
#[doc = "HSIKER"]
HSIKER = 0x02,
#[doc = "LSE"]
LSE = 0x03,
}
impl Usart1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Usart1sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Usart1sel {
#[inline(always)]
fn from(val: u8) -> Usart1sel {
Usart1sel::from_bits(val)
}
}
impl From<Usart1sel> for u8 {
#[inline(always)]
fn from(val: Usart1sel) -> u8 {
Usart1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Usbsel {
#[doc = "HSI48."]
HSI48 = 0x0,
#[doc = "HSE."]
HSE = 0x01,
}
impl Usbsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Usbsel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Usbsel {
#[inline(always)]
fn from(val: u8) -> Usbsel {
Usbsel::from_bits(val)
}
}
impl From<Usbsel> for u8 {
#[inline(always)]
fn from(val: Usbsel) -> u8 {
Usbsel::to_bits(val)
}
}
}