#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
#[doc = "Flash"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Flash {
ptr: *mut u8,
}
unsafe impl Send for Flash {}
unsafe impl Sync for Flash {}
impl Flash {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "access control register"]
#[inline(always)]
pub const fn acr(self) -> crate::common::Reg<regs::Acr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "key register"]
#[inline(always)]
pub const fn nskeyr(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
}
#[doc = "secure key register"]
#[inline(always)]
pub const fn seckeyr(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
#[doc = "option key register"]
#[inline(always)]
pub const fn optkeyr(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
}
#[doc = "Flash Bank 1 power-down key register"]
#[inline(always)]
pub const fn pdkey1r(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
}
#[doc = "Flash Bank 2 power-down key register"]
#[inline(always)]
pub const fn pdkey2r(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
}
#[doc = "status register"]
#[inline(always)]
pub const fn nssr(self) -> crate::common::Reg<regs::Nssr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
}
#[doc = "secure status register"]
#[inline(always)]
pub const fn secsr(self) -> crate::common::Reg<regs::Secsr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
}
#[doc = "FLASH non-secure control register"]
#[inline(always)]
pub const fn nscr(self) -> crate::common::Reg<regs::Nscr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
}
#[doc = "FLASH secure control register"]
#[inline(always)]
pub const fn seccr(self) -> crate::common::Reg<regs::Seccr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
}
#[doc = "ECC register"]
#[inline(always)]
pub const fn eccr(self) -> crate::common::Reg<regs::Eccr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
}
#[doc = "operation status register"]
#[inline(always)]
pub const fn opsr(self) -> crate::common::Reg<regs::Opsr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
}
#[doc = "control 2 register"]
#[inline(always)]
pub const fn nscr2(self) -> crate::common::Reg<regs::Nscr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
}
#[doc = "secure control 2 register"]
#[inline(always)]
pub const fn seccr2(self) -> crate::common::Reg<regs::Seccr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
}
#[doc = "option register"]
#[inline(always)]
pub const fn optr(self) -> crate::common::Reg<regs::Optr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
}
#[doc = "boot address 0 register"]
#[inline(always)]
pub const fn nsbootadd0r(self) -> crate::common::Reg<regs::Nsbootadd0r, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
}
#[doc = "boot address 1 register"]
#[inline(always)]
pub const fn nsbootadd1r(self) -> crate::common::Reg<regs::Nsbootadd1r, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
}
#[doc = "secure boot address 0 register"]
#[inline(always)]
pub const fn secbootadd0r(self) -> crate::common::Reg<regs::Secbootadd0r, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
}
#[doc = "FLASH secure watermark1 register 1"]
#[inline(always)]
pub const fn secwm1r1(self) -> crate::common::Reg<regs::Secwm1r1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
}
#[doc = "FLASH secure watermark1 register 2"]
#[inline(always)]
pub const fn secwm1r2(self) -> crate::common::Reg<regs::Secwm1r2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
}
#[doc = "Flash WRP bank 1 area A address register"]
#[inline(always)]
pub const fn wrp1ar(self) -> crate::common::Reg<regs::Wrp1ar, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
}
#[doc = "Flash WRP bank 1 area B address register"]
#[inline(always)]
pub const fn wrp1br(self) -> crate::common::Reg<regs::Wrp1br, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
}
#[doc = "Flash bank 2 secure watermark register 1"]
#[inline(always)]
pub const fn secwm2r1(self) -> crate::common::Reg<regs::Secwm2r1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
}
#[doc = "Flash bank 2 secure watermark register 2"]
#[inline(always)]
pub const fn secwm2r2(self) -> crate::common::Reg<regs::Secwm2r2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) }
}
#[doc = "Flash WRP bank 2 area A address register"]
#[inline(always)]
pub const fn wrp2ar(self) -> crate::common::Reg<regs::Wrp2ar, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
}
#[doc = "Flash WRP bank 2 area B address register"]
#[inline(always)]
pub const fn wrp2br(self) -> crate::common::Reg<regs::Wrp2br, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) }
}
#[doc = "OEM1 key register 1"]
#[inline(always)]
pub const fn oem1keyr1(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) }
}
#[doc = "OEM1 key register 2"]
#[inline(always)]
pub const fn oem1keyr2(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) }
}
#[doc = "OEM2 key register 1"]
#[inline(always)]
pub const fn oem2keyr1(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) }
}
#[doc = "OEM2 key register 2"]
#[inline(always)]
pub const fn oem2keyr2(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) }
}
#[doc = "Flash bank 1 secure block based register 1"]
#[inline(always)]
pub const fn secbb1r(self, n: usize) -> crate::common::Reg<regs::Bbr, crate::common::RW> {
assert!(n < 4usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize + n * 4usize) as _) }
}
#[doc = "Flash bank 2 secure block based register 1"]
#[inline(always)]
pub const fn secbb2r(self, n: usize) -> crate::common::Reg<regs::Bbr, crate::common::RW> {
assert!(n < 4usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize + n * 4usize) as _) }
}
#[doc = "secure HDP control register"]
#[inline(always)]
pub const fn sechdpcr(self) -> crate::common::Reg<regs::Sechdpcr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc0usize) as _) }
}
#[doc = "privilege configuration register"]
#[inline(always)]
pub const fn privcfgr(self) -> crate::common::Reg<regs::Privcfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) }
}
#[doc = "Flash bank 1 privilege block based register 1"]
#[inline(always)]
pub const fn privbb1r(self, n: usize) -> crate::common::Reg<regs::Bbr, crate::common::RW> {
assert!(n < 4usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd0usize + n * 4usize) as _) }
}
#[doc = "Flash bank 2 privilege block based register 1"]
#[inline(always)]
pub const fn privbb2r(self, n: usize) -> crate::common::Reg<regs::Bbr, crate::common::RW> {
assert!(n < 4usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf0usize + n * 4usize) as _) }
}
}
pub mod regs {
#[doc = "FLASH access control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Acr(pub u32);
impl Acr {
#[doc = "Latency These bits represent the ratio between the AHB hclk1 clock period and the memory access time. Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. ... Note: Before entering Stop 1 mode software must set wait state latency to at least 1."]
#[inline(always)]
pub const fn latency(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x0f;
val as u8
}
#[doc = "Latency These bits represent the ratio between the AHB hclk1 clock period and the memory access time. Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. ... Note: Before entering Stop 1 mode software must set wait state latency to at least 1."]
#[inline(always)]
pub fn set_latency(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
}
#[doc = "Prefetch enable This bit enables the prefetch buffer in the embedded memory. This bit can be protected against unprivileged access by NSPRIV."]
#[inline(always)]
pub const fn prften(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Prefetch enable This bit enables the prefetch buffer in the embedded memory. This bit can be protected against unprivileged access by NSPRIV."]
#[inline(always)]
pub fn set_prften(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "Low-power read mode This bit puts the memory in low-power read mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. This bit can’t be written when a program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a program or erase operation is busy (BSY = 1) is rejected."]
#[inline(always)]
pub const fn lpm(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Low-power read mode This bit puts the memory in low-power read mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. This bit can’t be written when a program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a program or erase operation is busy (BSY = 1) is rejected."]
#[inline(always)]
pub fn set_lpm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "Bank 1 power-down mode request This bit is write-protected with FLASH_PDKEY1R. This bit requests bank 1 to enter power-down mode. When bank 1 enters power-down mode, this bit is cleared by hardware and the PDKEY1R is locked."]
#[inline(always)]
pub const fn pdreq1(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "Bank 1 power-down mode request This bit is write-protected with FLASH_PDKEY1R. This bit requests bank 1 to enter power-down mode. When bank 1 enters power-down mode, this bit is cleared by hardware and the PDKEY1R is locked."]
#[inline(always)]
pub fn set_pdreq1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "Bank 2 power-down mode request This bit is write-protected with FLASH_PDKEY2R. This bit requests bank 2 to enter power-down mode. When bank 2 enters power-down mode, this bit is cleared by hardware and the PDKEY2R is locked."]
#[inline(always)]
pub const fn pdreq2(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "Bank 2 power-down mode request This bit is write-protected with FLASH_PDKEY2R. This bit requests bank 2 to enter power-down mode. When bank 2 enters power-down mode, this bit is cleared by hardware and the PDKEY2R is locked."]
#[inline(always)]
pub fn set_pdreq2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "memory power-down mode during Sleep mode This bit determines whether the memory is in power-down mode or Idle mode when the device is in Sleep mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. The must not be put in power-down while a program or an erase operation is ongoing."]
#[inline(always)]
pub const fn sleep_pd(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "memory power-down mode during Sleep mode This bit determines whether the memory is in power-down mode or Idle mode when the device is in Sleep mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. The must not be put in power-down while a program or an erase operation is ongoing."]
#[inline(always)]
pub fn set_sleep_pd(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
}
impl Default for Acr {
#[inline(always)]
fn default() -> Acr {
Acr(0)
}
}
impl core::fmt::Debug for Acr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Acr")
.field("latency", &self.latency())
.field("prften", &self.prften())
.field("lpm", &self.lpm())
.field("pdreq1", &self.pdreq1())
.field("pdreq2", &self.pdreq2())
.field("sleep_pd", &self.sleep_pd())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Acr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Acr {{ latency: {=u8:?}, prften: {=bool:?}, lpm: {=bool:?}, pdreq1: {=bool:?}, pdreq2: {=bool:?}, sleep_pd: {=bool:?} }}" , self . latency () , self . prften () , self . lpm () , self . pdreq1 () , self . pdreq2 () , self . sleep_pd ())
}
}
#[doc = "block based register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Bbr(pub u32);
impl Bbr {
#[inline(always)]
pub const fn block(&self, n: usize) -> bool {
assert!(n < 32usize);
let offs = 0usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_block(&mut self, n: usize, val: bool) {
assert!(n < 32usize);
let offs = 0usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Bbr {
#[inline(always)]
fn default() -> Bbr {
Bbr(0)
}
}
impl core::fmt::Debug for Bbr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Bbr")
.field("block[0]", &self.block(0usize))
.field("block[1]", &self.block(1usize))
.field("block[2]", &self.block(2usize))
.field("block[3]", &self.block(3usize))
.field("block[4]", &self.block(4usize))
.field("block[5]", &self.block(5usize))
.field("block[6]", &self.block(6usize))
.field("block[7]", &self.block(7usize))
.field("block[8]", &self.block(8usize))
.field("block[9]", &self.block(9usize))
.field("block[10]", &self.block(10usize))
.field("block[11]", &self.block(11usize))
.field("block[12]", &self.block(12usize))
.field("block[13]", &self.block(13usize))
.field("block[14]", &self.block(14usize))
.field("block[15]", &self.block(15usize))
.field("block[16]", &self.block(16usize))
.field("block[17]", &self.block(17usize))
.field("block[18]", &self.block(18usize))
.field("block[19]", &self.block(19usize))
.field("block[20]", &self.block(20usize))
.field("block[21]", &self.block(21usize))
.field("block[22]", &self.block(22usize))
.field("block[23]", &self.block(23usize))
.field("block[24]", &self.block(24usize))
.field("block[25]", &self.block(25usize))
.field("block[26]", &self.block(26usize))
.field("block[27]", &self.block(27usize))
.field("block[28]", &self.block(28usize))
.field("block[29]", &self.block(29usize))
.field("block[30]", &self.block(30usize))
.field("block[31]", &self.block(31usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Bbr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Bbr {{ block[0]: {=bool:?}, block[1]: {=bool:?}, block[2]: {=bool:?}, block[3]: {=bool:?}, block[4]: {=bool:?}, block[5]: {=bool:?}, block[6]: {=bool:?}, block[7]: {=bool:?}, block[8]: {=bool:?}, block[9]: {=bool:?}, block[10]: {=bool:?}, block[11]: {=bool:?}, block[12]: {=bool:?}, block[13]: {=bool:?}, block[14]: {=bool:?}, block[15]: {=bool:?}, block[16]: {=bool:?}, block[17]: {=bool:?}, block[18]: {=bool:?}, block[19]: {=bool:?}, block[20]: {=bool:?}, block[21]: {=bool:?}, block[22]: {=bool:?}, block[23]: {=bool:?}, block[24]: {=bool:?}, block[25]: {=bool:?}, block[26]: {=bool:?}, block[27]: {=bool:?}, block[28]: {=bool:?}, block[29]: {=bool:?}, block[30]: {=bool:?}, block[31]: {=bool:?} }}" , self . block (0usize) , self . block (1usize) , self . block (2usize) , self . block (3usize) , self . block (4usize) , self . block (5usize) , self . block (6usize) , self . block (7usize) , self . block (8usize) , self . block (9usize) , self . block (10usize) , self . block (11usize) , self . block (12usize) , self . block (13usize) , self . block (14usize) , self . block (15usize) , self . block (16usize) , self . block (17usize) , self . block (18usize) , self . block (19usize) , self . block (20usize) , self . block (21usize) , self . block (22usize) , self . block (23usize) , self . block (24usize) , self . block (25usize) , self . block (26usize) , self . block (27usize) , self . block (28usize) , self . block (29usize) , self . block (30usize) , self . block (31usize))
}
}
#[doc = "FLASH ECC register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Eccr(pub u32);
impl Eccr {
#[doc = "ECC fail address This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to base address, from offset 0x0�0000 to 0xF�FFF0. Note that bit 19 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub const fn addr_ecc(&self) -> u32 {
let val = (self.0 >> 0usize) & 0x000f_ffff;
val as u32
}
#[doc = "ECC fail address This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given relative to base address, from offset 0x0�0000 to 0xF�FFF0. Note that bit 19 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub fn set_addr_ecc(&mut self, val: u32) {
self.0 = (self.0 & !(0x000f_ffff << 0usize)) | (((val as u32) & 0x000f_ffff) << 0usize);
}
#[doc = "ECC fail bank"]
#[inline(always)]
pub const fn bk_ecc(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "ECC fail bank"]
#[inline(always)]
pub fn set_bk_ecc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "System memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system memory."]
#[inline(always)]
pub const fn sysf_ecc(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "System memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system memory."]
#[inline(always)]
pub fn set_sysf_ecc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the ECCR register is set."]
#[inline(always)]
pub const fn eccie(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the ECCR register is set."]
#[inline(always)]
pub fn set_eccie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1."]
#[inline(always)]
pub const fn eccc(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1."]
#[inline(always)]
pub fn set_eccc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1."]
#[inline(always)]
pub const fn eccd(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1."]
#[inline(always)]
pub fn set_eccd(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Eccr {
#[inline(always)]
fn default() -> Eccr {
Eccr(0)
}
}
impl core::fmt::Debug for Eccr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Eccr")
.field("addr_ecc", &self.addr_ecc())
.field("bk_ecc", &self.bk_ecc())
.field("sysf_ecc", &self.sysf_ecc())
.field("eccie", &self.eccie())
.field("eccc", &self.eccc())
.field("eccd", &self.eccd())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Eccr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Eccr {{ addr_ecc: {=u32:?}, bk_ecc: {=bool:?}, sysf_ecc: {=bool:?}, eccie: {=bool:?}, eccc: {=bool:?}, eccd: {=bool:?} }}" , self . addr_ecc () , self . bk_ecc () , self . sysf_ecc () , self . eccie () , self . eccc () , self . eccd ())
}
}
#[doc = "FLASH non-secure boot address 0 register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Nsbootadd0r(pub u32);
impl Nsbootadd0r {
#[doc = "Non-secure boot base address 0 This address is only used when TZEN = 0. The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address \\[31:7\\]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: NSBOOTADD0\\[24:0\\]
= 0x0100000: Boot from memory (0x0800 0000) NSBOOTADD0\\[24:0\\]
= 0x017F100: Boot from system memory bootloader (0x0BF8 8000) NSBOOTADD0\\[24:0\\]
= 0x0400200: Boot from SRAM2 on S-Bus (0x2001 0000)"]
#[inline(always)]
pub const fn nsbootadd0(&self) -> u32 {
let val = (self.0 >> 7usize) & 0x01ff_ffff;
val as u32
}
#[doc = "Non-secure boot base address 0 This address is only used when TZEN = 0. The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address \\[31:7\\]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: NSBOOTADD0\\[24:0\\]
= 0x0100000: Boot from memory (0x0800 0000) NSBOOTADD0\\[24:0\\]
= 0x017F100: Boot from system memory bootloader (0x0BF8 8000) NSBOOTADD0\\[24:0\\]
= 0x0400200: Boot from SRAM2 on S-Bus (0x2001 0000)"]
#[inline(always)]
pub fn set_nsbootadd0(&mut self, val: u32) {
self.0 = (self.0 & !(0x01ff_ffff << 7usize)) | (((val as u32) & 0x01ff_ffff) << 7usize);
}
}
impl Default for Nsbootadd0r {
#[inline(always)]
fn default() -> Nsbootadd0r {
Nsbootadd0r(0)
}
}
impl core::fmt::Debug for Nsbootadd0r {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Nsbootadd0r")
.field("nsbootadd0", &self.nsbootadd0())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Nsbootadd0r {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Nsbootadd0r {{ nsbootadd0: {=u32:?} }}", self.nsbootadd0())
}
}
#[doc = "FLASH non-secure boot address 1 register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Nsbootadd1r(pub u32);
impl Nsbootadd1r {
#[doc = "Non-secure boot address 1 This address is only used when TZEN = 0. The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address \\[31:7\\]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: NSBOOTADD1\\[24:0\\]
= 0x0100000: Boot from memory (0x0800 0000) NSBOOTADD1\\[24:0\\]
= 0x017F100: Boot from system memory bootloader (0x0BF8 8000) NSBOOTADD1\\[24:0\\]
= 0x0400200: Boot from SRAM2 (0x2001 0000)"]
#[inline(always)]
pub const fn nsbootadd1(&self) -> u32 {
let val = (self.0 >> 7usize) & 0x01ff_ffff;
val as u32
}
#[doc = "Non-secure boot address 1 This address is only used when TZEN = 0. The non-secure boot memory address can be programmed to any address in the valid address range (see Table 28: Boot space versus RDP protection) with a granularity of 128 bytes. These bits correspond to address \\[31:7\\]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: NSBOOTADD1\\[24:0\\]
= 0x0100000: Boot from memory (0x0800 0000) NSBOOTADD1\\[24:0\\]
= 0x017F100: Boot from system memory bootloader (0x0BF8 8000) NSBOOTADD1\\[24:0\\]
= 0x0400200: Boot from SRAM2 (0x2001 0000)"]
#[inline(always)]
pub fn set_nsbootadd1(&mut self, val: u32) {
self.0 = (self.0 & !(0x01ff_ffff << 7usize)) | (((val as u32) & 0x01ff_ffff) << 7usize);
}
}
impl Default for Nsbootadd1r {
#[inline(always)]
fn default() -> Nsbootadd1r {
Nsbootadd1r(0)
}
}
impl core::fmt::Debug for Nsbootadd1r {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Nsbootadd1r")
.field("nsbootadd1", &self.nsbootadd1())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Nsbootadd1r {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Nsbootadd1r {{ nsbootadd1: {=u32:?} }}", self.nsbootadd1())
}
}
#[doc = "FLASH non-secure control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Nscr(pub u32);
impl Nscr {
#[doc = "Non-secure programming"]
#[inline(always)]
pub const fn pg(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Non-secure programming"]
#[inline(always)]
pub fn set_pg(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Non-secure page erase"]
#[inline(always)]
pub const fn per(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Non-secure page erase"]
#[inline(always)]
pub fn set_per(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Non-secure bank 1 mass erase This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set."]
#[inline(always)]
pub const fn mer1(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Non-secure bank 1 mass erase This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set."]
#[inline(always)]
pub fn set_mer1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Non-secure page number selection These bits select the page to erase. ..."]
#[inline(always)]
pub const fn pnb(&self) -> u8 {
let val = (self.0 >> 3usize) & 0xff;
val as u8
}
#[doc = "Non-secure page number selection These bits select the page to erase. ..."]
#[inline(always)]
pub fn set_pnb(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 3usize)) | (((val as u32) & 0xff) << 3usize);
}
#[doc = "Non-secure bank selection for page erase"]
#[inline(always)]
pub const fn bker(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Non-secure bank selection for page erase"]
#[inline(always)]
pub fn set_bker(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "Non-secure burst write programming mode When set, this bit selects the burst write programming mode."]
#[inline(always)]
pub const fn bwr(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "Non-secure burst write programming mode When set, this bit selects the burst write programming mode."]
#[inline(always)]
pub fn set_bwr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "Non-secure bank 2 mass erase This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set."]
#[inline(always)]
pub const fn mer2(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "Non-secure bank 2 mass erase This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set."]
#[inline(always)]
pub fn set_mer2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "Non-secure start This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR."]
#[inline(always)]
pub const fn strt(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Non-secure start This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR."]
#[inline(always)]
pub fn set_strt(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Options modification start This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR."]
#[inline(always)]
pub const fn optstrt(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Options modification start This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR."]
#[inline(always)]
pub fn set_optstrt(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1."]
#[inline(always)]
pub const fn eopie(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1."]
#[inline(always)]
pub fn set_eopie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1."]
#[inline(always)]
pub const fn errie(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1."]
#[inline(always)]
pub fn set_errie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set."]
#[inline(always)]
pub const fn obl_launch(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set."]
#[inline(always)]
pub fn set_obl_launch(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Option lock This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset."]
#[inline(always)]
pub const fn optlock(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Option lock This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset."]
#[inline(always)]
pub fn set_optlock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "Non-secure lock This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset."]
#[inline(always)]
pub const fn lock(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Non-secure lock This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset."]
#[inline(always)]
pub fn set_lock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Nscr {
#[inline(always)]
fn default() -> Nscr {
Nscr(0)
}
}
impl core::fmt::Debug for Nscr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Nscr")
.field("pg", &self.pg())
.field("per", &self.per())
.field("mer1", &self.mer1())
.field("pnb", &self.pnb())
.field("bker", &self.bker())
.field("bwr", &self.bwr())
.field("mer2", &self.mer2())
.field("strt", &self.strt())
.field("optstrt", &self.optstrt())
.field("eopie", &self.eopie())
.field("errie", &self.errie())
.field("obl_launch", &self.obl_launch())
.field("optlock", &self.optlock())
.field("lock", &self.lock())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Nscr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Nscr {{ pg: {=bool:?}, per: {=bool:?}, mer1: {=bool:?}, pnb: {=u8:?}, bker: {=bool:?}, bwr: {=bool:?}, mer2: {=bool:?}, strt: {=bool:?}, optstrt: {=bool:?}, eopie: {=bool:?}, errie: {=bool:?}, obl_launch: {=bool:?}, optlock: {=bool:?}, lock: {=bool:?} }}" , self . pg () , self . per () , self . mer1 () , self . pnb () , self . bker () , self . bwr () , self . mer2 () , self . strt () , self . optstrt () , self . eopie () , self . errie () , self . obl_launch () , self . optlock () , self . lock ())
}
}
#[doc = "control 2 register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Nscr2(pub u32);
impl Nscr2 {
#[doc = "Program suspend request"]
#[inline(always)]
pub const fn ps(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Program suspend request"]
#[inline(always)]
pub fn set_ps(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Erase suspend request"]
#[inline(always)]
pub const fn es(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Erase suspend request"]
#[inline(always)]
pub fn set_es(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
}
impl Default for Nscr2 {
#[inline(always)]
fn default() -> Nscr2 {
Nscr2(0)
}
}
impl core::fmt::Debug for Nscr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Nscr2")
.field("ps", &self.ps())
.field("es", &self.es())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Nscr2 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Nscr2 {{ ps: {=bool:?}, es: {=bool:?} }}", self.ps(), self.es())
}
}
#[doc = "FLASH non-secure status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Nssr(pub u32);
impl Nssr {
#[doc = "Non-secure end of operation This bit is set by hardware when one or more memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in NSCR1). This bit is cleared by writing�1."]
#[inline(always)]
pub const fn eop(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Non-secure end of operation This bit is set by hardware when one or more memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in NSCR1). This bit is cleared by writing�1."]
#[inline(always)]
pub fn set_eop(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Non-secure operation error This bit is set by hardware when a memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1."]
#[inline(always)]
pub const fn operr(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Non-secure operation error This bit is set by hardware when a memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1."]
#[inline(always)]
pub fn set_operr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."]
#[inline(always)]
pub const fn progerr(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."]
#[inline(always)]
pub fn set_progerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "Non-secure write protection error This bit is set by hardware when a non-secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting."]
#[inline(always)]
pub const fn wrperr(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "Non-secure write protection error This bit is set by hardware when a non-secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting."]
#[inline(always)]
pub fn set_wrperr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "Non-secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1."]
#[inline(always)]
pub const fn pgaerr(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Non-secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1."]
#[inline(always)]
pub fn set_pgaerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Non-secure size error This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1."]
#[inline(always)]
pub const fn sizerr(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "Non-secure size error This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1."]
#[inline(always)]
pub fn set_sizerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "Non-secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting."]
#[inline(always)]
pub const fn pgserr(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "Non-secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting."]
#[inline(always)]
pub fn set_pgserr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "Option write error This bit is set by hardware when the options bytes are written with an invalid configuration or when modifying options in RDP level 2.. It is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting."]
#[inline(always)]
pub const fn optwerr(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "Option write error This bit is set by hardware when the options bytes are written with an invalid configuration or when modifying options in RDP level 2.. It is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting."]
#[inline(always)]
pub fn set_optwerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "Non-secure busy This indicates that a memory secure or non-secure operation is in progress. This bit is set at the beginning of a operation and reset when the operation finishes or when an error occurs."]
#[inline(always)]
pub const fn bsy(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Non-secure busy This indicates that a memory secure or non-secure operation is in progress. This bit is set at the beginning of a operation and reset when the operation finishes or when an error occurs."]
#[inline(always)]
pub fn set_bsy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Non-secure wait data to write This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."]
#[inline(always)]
pub const fn wdw(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Non-secure wait data to write This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."]
#[inline(always)]
pub fn set_wdw(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "OEM1 key RDP lock This bit indicates that the OEM1 key read during the OBL is not virgin. When set, the OEM1 key RDP lock mechanism is active."]
#[inline(always)]
pub const fn oem1lock(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "OEM1 key RDP lock This bit indicates that the OEM1 key read during the OBL is not virgin. When set, the OEM1 key RDP lock mechanism is active."]
#[inline(always)]
pub fn set_oem1lock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "OEM2 key RDP lock This bit indicates that the OEM2 key read during the OBL is not virgin. When set, the OEM2 key RDP lock mechanism is active."]
#[inline(always)]
pub const fn oem2lock(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "OEM2 key RDP lock This bit indicates that the OEM2 key read during the OBL is not virgin. When set, the OEM2 key RDP lock mechanism is active."]
#[inline(always)]
pub fn set_oem2lock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "Bank 1 in power-down mode This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bank 1 is in normal mode or being awaken."]
#[inline(always)]
pub const fn pd1(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "Bank 1 in power-down mode This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bank 1 is in normal mode or being awaken."]
#[inline(always)]
pub fn set_pd1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "Bank 2 in power-down mode This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bank 2 is in normal mode or being awaken."]
#[inline(always)]
pub const fn pd2(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "Bank 2 in power-down mode This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bank 2 is in normal mode or being awaken."]
#[inline(always)]
pub fn set_pd2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
}
impl Default for Nssr {
#[inline(always)]
fn default() -> Nssr {
Nssr(0)
}
}
impl core::fmt::Debug for Nssr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Nssr")
.field("eop", &self.eop())
.field("operr", &self.operr())
.field("progerr", &self.progerr())
.field("wrperr", &self.wrperr())
.field("pgaerr", &self.pgaerr())
.field("sizerr", &self.sizerr())
.field("pgserr", &self.pgserr())
.field("optwerr", &self.optwerr())
.field("bsy", &self.bsy())
.field("wdw", &self.wdw())
.field("oem1lock", &self.oem1lock())
.field("oem2lock", &self.oem2lock())
.field("pd1", &self.pd1())
.field("pd2", &self.pd2())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Nssr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Nssr {{ eop: {=bool:?}, operr: {=bool:?}, progerr: {=bool:?}, wrperr: {=bool:?}, pgaerr: {=bool:?}, sizerr: {=bool:?}, pgserr: {=bool:?}, optwerr: {=bool:?}, bsy: {=bool:?}, wdw: {=bool:?}, oem1lock: {=bool:?}, oem2lock: {=bool:?}, pd1: {=bool:?}, pd2: {=bool:?} }}" , self . eop () , self . operr () , self . progerr () , self . wrperr () , self . pgaerr () , self . sizerr () , self . pgserr () , self . optwerr () , self . bsy () , self . wdw () , self . oem1lock () , self . oem2lock () , self . pd1 () , self . pd2 ())
}
}
#[doc = "FLASH operation status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Opsr(pub u32);
impl Opsr {
#[doc = "Interrupted operation address This field indicates which address in the memory was accessed when reset occurred. The address is given relative to the base address, from offset 0x0�0000 to 0xF�FFF0. Note that bit 19 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub const fn addr_op(&self) -> u32 {
let val = (self.0 >> 0usize) & 0x000f_ffff;
val as u32
}
#[doc = "Interrupted operation address This field indicates which address in the memory was accessed when reset occurred. The address is given relative to the base address, from offset 0x0�0000 to 0xF�FFF0. Note that bit 19 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub fn set_addr_op(&mut self, val: u32) {
self.0 = (self.0 & !(0x000f_ffff << 0usize)) | (((val as u32) & 0x000f_ffff) << 0usize);
}
#[doc = "Interrupted operation bank This bit indicates which Flash memory bank was accessed when reset occurred"]
#[inline(always)]
pub const fn bk_op(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "Interrupted operation bank This bit indicates which Flash memory bank was accessed when reset occurred"]
#[inline(always)]
pub fn set_bk_op(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "Operation in system memory interrupted This bit indicates that the reset occurred during an operation in the system memory."]
#[inline(always)]
pub const fn sysf_op(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "Operation in system memory interrupted This bit indicates that the reset occurred during an operation in the system memory."]
#[inline(always)]
pub fn set_sysf_op(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "memory operation code This field indicates which memory operation has been interrupted by a system reset:"]
#[inline(always)]
pub const fn code_op(&self) -> super::vals::CodeOp {
let val = (self.0 >> 29usize) & 0x07;
super::vals::CodeOp::from_bits(val as u8)
}
#[doc = "memory operation code This field indicates which memory operation has been interrupted by a system reset:"]
#[inline(always)]
pub fn set_code_op(&mut self, val: super::vals::CodeOp) {
self.0 = (self.0 & !(0x07 << 29usize)) | (((val.to_bits() as u32) & 0x07) << 29usize);
}
}
impl Default for Opsr {
#[inline(always)]
fn default() -> Opsr {
Opsr(0)
}
}
impl core::fmt::Debug for Opsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Opsr")
.field("addr_op", &self.addr_op())
.field("bk_op", &self.bk_op())
.field("sysf_op", &self.sysf_op())
.field("code_op", &self.code_op())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Opsr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Opsr {{ addr_op: {=u32:?}, bk_op: {=bool:?}, sysf_op: {=bool:?}, code_op: {:?} }}",
self.addr_op(),
self.bk_op(),
self.sysf_op(),
self.code_op()
)
}
}
#[doc = "FLASH option register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Optr(pub u32);
impl Optr {
#[doc = "Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to Section�7.6.2: Readout protection (RDP) for more details."]
#[inline(always)]
pub const fn rdp(&self) -> super::vals::Rdp {
let val = (self.0 >> 0usize) & 0xff;
super::vals::Rdp::from_bits(val as u8)
}
#[doc = "Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to Section�7.6.2: Readout protection (RDP) for more details."]
#[inline(always)]
pub fn set_rdp(&mut self, val: super::vals::Rdp) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize);
}
#[doc = "BOR reset level These bits contain the V<sub>DD</sub> supply level threshold that activates/releases the reset."]
#[inline(always)]
pub const fn bor_lev(&self) -> super::vals::BorLev {
let val = (self.0 >> 8usize) & 0x07;
super::vals::BorLev::from_bits(val as u8)
}
#[doc = "BOR reset level These bits contain the V<sub>DD</sub> supply level threshold that activates/releases the reset."]
#[inline(always)]
pub fn set_bor_lev(&mut self, val: super::vals::BorLev) {
self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
}
#[doc = "Reset generation in Stop mode"]
#[inline(always)]
pub const fn n_rst_stop(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "Reset generation in Stop mode"]
#[inline(always)]
pub fn set_n_rst_stop(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "Reset generation in Standby mode"]
#[inline(always)]
pub const fn n_rst_stdby(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "Reset generation in Standby mode"]
#[inline(always)]
pub fn set_n_rst_stdby(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "Reset generation in Shutdown mode"]
#[inline(always)]
pub const fn n_rst_shdw(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "Reset generation in Shutdown mode"]
#[inline(always)]
pub fn set_n_rst_shdw(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "SRAM1 erase upon system reset"]
#[inline(always)]
pub const fn sram1_rst(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "SRAM1 erase upon system reset"]
#[inline(always)]
pub fn set_sram1_rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "Independent watchdog enable selection"]
#[inline(always)]
pub const fn iwdg_sw(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Independent watchdog enable selection"]
#[inline(always)]
pub fn set_iwdg_sw(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Independent watchdog counter freeze in Stop mode"]
#[inline(always)]
pub const fn iwdg_stop(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Independent watchdog counter freeze in Stop mode"]
#[inline(always)]
pub fn set_iwdg_stop(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "Independent watchdog counter freeze in Standby mode"]
#[inline(always)]
pub const fn iwdg_stdby(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "Independent watchdog counter freeze in Standby mode"]
#[inline(always)]
pub fn set_iwdg_stdby(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "Window watchdog selection"]
#[inline(always)]
pub const fn wwdg_sw(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "Window watchdog selection"]
#[inline(always)]
pub fn set_wwdg_sw(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "Swap banks"]
#[inline(always)]
pub const fn swap_bank(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "Swap banks"]
#[inline(always)]
pub fn set_swap_bank(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices"]
#[inline(always)]
pub const fn dualbank(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices"]
#[inline(always)]
pub fn set_dualbank(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "SRAM2 parity check enable"]
#[inline(always)]
pub const fn sram2_pe(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "SRAM2 parity check enable"]
#[inline(always)]
pub fn set_sram2_pe(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "SRAM2 erase when system reset"]
#[inline(always)]
pub const fn sram2_rst(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "SRAM2 erase when system reset"]
#[inline(always)]
pub fn set_sram2_rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "Software BOOT0"]
#[inline(always)]
pub const fn n_swboot0(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "Software BOOT0"]
#[inline(always)]
pub fn set_n_swboot0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "nBOOT0 option bit"]
#[inline(always)]
pub const fn n_boot0(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "nBOOT0 option bit"]
#[inline(always)]
pub fn set_n_boot0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "High-speed IO at low VDD voltage configuration bit This bit can be set only with VDD below 2.5V"]
#[inline(always)]
pub const fn io_vdd_hslv(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "High-speed IO at low VDD voltage configuration bit This bit can be set only with VDD below 2.5V"]
#[inline(always)]
pub fn set_io_vdd_hslv(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "High-speed IO at low VDDIO2 voltage configuration bit This bit can be set only with VDDIO2 below 2.5 V."]
#[inline(always)]
pub const fn io_vddio2_hslv(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "High-speed IO at low VDDIO2 voltage configuration bit This bit can be set only with VDDIO2 below 2.5 V."]
#[inline(always)]
pub fn set_io_vddio2_hslv(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "Global TrustZone security enable"]
#[inline(always)]
pub const fn tzen(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Global TrustZone security enable"]
#[inline(always)]
pub fn set_tzen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Optr {
#[inline(always)]
fn default() -> Optr {
Optr(0)
}
}
impl core::fmt::Debug for Optr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Optr")
.field("rdp", &self.rdp())
.field("bor_lev", &self.bor_lev())
.field("n_rst_stop", &self.n_rst_stop())
.field("n_rst_stdby", &self.n_rst_stdby())
.field("n_rst_shdw", &self.n_rst_shdw())
.field("sram1_rst", &self.sram1_rst())
.field("iwdg_sw", &self.iwdg_sw())
.field("iwdg_stop", &self.iwdg_stop())
.field("iwdg_stdby", &self.iwdg_stdby())
.field("wwdg_sw", &self.wwdg_sw())
.field("swap_bank", &self.swap_bank())
.field("dualbank", &self.dualbank())
.field("sram2_pe", &self.sram2_pe())
.field("sram2_rst", &self.sram2_rst())
.field("n_swboot0", &self.n_swboot0())
.field("n_boot0", &self.n_boot0())
.field("io_vdd_hslv", &self.io_vdd_hslv())
.field("io_vddio2_hslv", &self.io_vddio2_hslv())
.field("tzen", &self.tzen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Optr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Optr {{ rdp: {:?}, bor_lev: {:?}, n_rst_stop: {=bool:?}, n_rst_stdby: {=bool:?}, n_rst_shdw: {=bool:?}, sram1_rst: {=bool:?}, iwdg_sw: {=bool:?}, iwdg_stop: {=bool:?}, iwdg_stdby: {=bool:?}, wwdg_sw: {=bool:?}, swap_bank: {=bool:?}, dualbank: {=bool:?}, sram2_pe: {=bool:?}, sram2_rst: {=bool:?}, n_swboot0: {=bool:?}, n_boot0: {=bool:?}, io_vdd_hslv: {=bool:?}, io_vddio2_hslv: {=bool:?}, tzen: {=bool:?} }}" , self . rdp () , self . bor_lev () , self . n_rst_stop () , self . n_rst_stdby () , self . n_rst_shdw () , self . sram1_rst () , self . iwdg_sw () , self . iwdg_stop () , self . iwdg_stdby () , self . wwdg_sw () , self . swap_bank () , self . dualbank () , self . sram2_pe () , self . sram2_rst () , self . n_swboot0 () , self . n_boot0 () , self . io_vdd_hslv () , self . io_vddio2_hslv () , self . tzen ())
}
}
#[doc = "FLASH privilege configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Privcfgr(pub u32);
impl Privcfgr {
#[doc = "Privileged protection for secure registers This bit is secure write protected. It can only be written by a secure privileged access when TrustZone is enabled (TZEN�=�1)."]
#[inline(always)]
pub const fn spriv(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Privileged protection for secure registers This bit is secure write protected. It can only be written by a secure privileged access when TrustZone is enabled (TZEN�=�1)."]
#[inline(always)]
pub fn set_spriv(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Privileged protection for non-secure registers"]
#[inline(always)]
pub const fn nspriv(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Privileged protection for non-secure registers"]
#[inline(always)]
pub fn set_nspriv(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
}
impl Default for Privcfgr {
#[inline(always)]
fn default() -> Privcfgr {
Privcfgr(0)
}
}
impl core::fmt::Debug for Privcfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Privcfgr")
.field("spriv", &self.spriv())
.field("nspriv", &self.nspriv())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Privcfgr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Privcfgr {{ spriv: {=bool:?}, nspriv: {=bool:?} }}",
self.spriv(),
self.nspriv()
)
}
}
#[doc = "FLASH secure boot address 0 register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Secbootadd0r(pub u32);
impl Secbootadd0r {
#[doc = "Boot lock This lock is only used when TZEN = 0. When set, the boot is always forced to base address value programmed in SECBOOTADD0\\[24:0\\]
option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP regression level 1 to level 0."]
#[inline(always)]
pub const fn boot_lock(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Boot lock This lock is only used when TZEN = 0. When set, the boot is always forced to base address value programmed in SECBOOTADD0\\[24:0\\]
option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP regression level 1 to level 0."]
#[inline(always)]
pub fn set_boot_lock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Secure boot base address 0 This address is only used when TZEN = 1. The secure boot memory address can be programmed to any address in the valid address range (see Table�28: Boot space versus RDP protection) with a granularity of 128 bytes. This bits correspond to address \\[31:7\\]
The SECBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: SECBOOTADD0\\[24:0\\]
= 0x018 0000: Boot from secure user memory (0x0C00 0000) SECBOOTADD0\\[24:0\\]
= 0x01F F000: Boot from RSS system memory (0x0FF8 0000) SECBOOTADD0\\[24:0\\]
= 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)"]
#[inline(always)]
pub const fn secbootadd0(&self) -> u32 {
let val = (self.0 >> 7usize) & 0x01ff_ffff;
val as u32
}
#[doc = "Secure boot base address 0 This address is only used when TZEN = 1. The secure boot memory address can be programmed to any address in the valid address range (see Table�28: Boot space versus RDP protection) with a granularity of 128 bytes. This bits correspond to address \\[31:7\\]
The SECBOOTADD0 option bytes are selected following the BOOT0 pin or NSWBOOT0 state. Examples: SECBOOTADD0\\[24:0\\]
= 0x018 0000: Boot from secure user memory (0x0C00 0000) SECBOOTADD0\\[24:0\\]
= 0x01F F000: Boot from RSS system memory (0x0FF8 0000) SECBOOTADD0\\[24:0\\]
= 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)"]
#[inline(always)]
pub fn set_secbootadd0(&mut self, val: u32) {
self.0 = (self.0 & !(0x01ff_ffff << 7usize)) | (((val as u32) & 0x01ff_ffff) << 7usize);
}
}
impl Default for Secbootadd0r {
#[inline(always)]
fn default() -> Secbootadd0r {
Secbootadd0r(0)
}
}
impl core::fmt::Debug for Secbootadd0r {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Secbootadd0r")
.field("boot_lock", &self.boot_lock())
.field("secbootadd0", &self.secbootadd0())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Secbootadd0r {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Secbootadd0r {{ boot_lock: {=bool:?}, secbootadd0: {=u32:?} }}",
self.boot_lock(),
self.secbootadd0()
)
}
}
#[doc = "FLASH secure control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Seccr(pub u32);
impl Seccr {
#[doc = "Secure programming"]
#[inline(always)]
pub const fn pg(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Secure programming"]
#[inline(always)]
pub fn set_pg(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Secure page erase"]
#[inline(always)]
pub const fn per(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Secure page erase"]
#[inline(always)]
pub fn set_per(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set."]
#[inline(always)]
pub const fn mer1(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set."]
#[inline(always)]
pub fn set_mer1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Secure page number selection These bits select the page to erase: ..."]
#[inline(always)]
pub const fn pnb(&self) -> u8 {
let val = (self.0 >> 3usize) & 0xff;
val as u8
}
#[doc = "Secure page number selection These bits select the page to erase: ..."]
#[inline(always)]
pub fn set_pnb(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 3usize)) | (((val as u32) & 0xff) << 3usize);
}
#[doc = "Secure bank selection for page erase"]
#[inline(always)]
pub const fn bker(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Secure bank selection for page erase"]
#[inline(always)]
pub fn set_bker(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "Secure burst write programming mode When set, this bit selects the burst write programming mode."]
#[inline(always)]
pub const fn bwr(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "Secure burst write programming mode When set, this bit selects the burst write programming mode."]
#[inline(always)]
pub fn set_bwr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set."]
#[inline(always)]
pub const fn mer2(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set."]
#[inline(always)]
pub fn set_mer2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR."]
#[inline(always)]
pub const fn strt(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR."]
#[inline(always)]
pub fn set_strt(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1."]
#[inline(always)]
pub const fn eopie(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1."]
#[inline(always)]
pub fn set_eopie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Secure error interrupt enable"]
#[inline(always)]
pub const fn errie(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Secure error interrupt enable"]
#[inline(always)]
pub fn set_errie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "Secure PCROP read error interrupt enable"]
#[inline(always)]
pub const fn rderrie(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "Secure PCROP read error interrupt enable"]
#[inline(always)]
pub fn set_rderrie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "Flash memory security state invert This bit inverts the Flash memory security state."]
#[inline(always)]
pub const fn inv(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "Flash memory security state invert This bit inverts the Flash memory security state."]
#[inline(always)]
pub fn set_inv(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset."]
#[inline(always)]
pub const fn lock(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset."]
#[inline(always)]
pub fn set_lock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Seccr {
#[inline(always)]
fn default() -> Seccr {
Seccr(0)
}
}
impl core::fmt::Debug for Seccr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Seccr")
.field("pg", &self.pg())
.field("per", &self.per())
.field("mer1", &self.mer1())
.field("pnb", &self.pnb())
.field("bker", &self.bker())
.field("bwr", &self.bwr())
.field("mer2", &self.mer2())
.field("strt", &self.strt())
.field("eopie", &self.eopie())
.field("errie", &self.errie())
.field("rderrie", &self.rderrie())
.field("inv", &self.inv())
.field("lock", &self.lock())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Seccr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Seccr {{ pg: {=bool:?}, per: {=bool:?}, mer1: {=bool:?}, pnb: {=u8:?}, bker: {=bool:?}, bwr: {=bool:?}, mer2: {=bool:?}, strt: {=bool:?}, eopie: {=bool:?}, errie: {=bool:?}, rderrie: {=bool:?}, inv: {=bool:?}, lock: {=bool:?} }}" , self . pg () , self . per () , self . mer1 () , self . pnb () , self . bker () , self . bwr () , self . mer2 () , self . strt () , self . eopie () , self . errie () , self . rderrie () , self . inv () , self . lock ())
}
}
#[doc = "secure control 2 register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Seccr2(pub u32);
impl Seccr2 {
#[doc = "Program suspend request"]
#[inline(always)]
pub const fn ps(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Program suspend request"]
#[inline(always)]
pub fn set_ps(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Erase suspend request"]
#[inline(always)]
pub const fn es(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Erase suspend request"]
#[inline(always)]
pub fn set_es(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
}
impl Default for Seccr2 {
#[inline(always)]
fn default() -> Seccr2 {
Seccr2(0)
}
}
impl core::fmt::Debug for Seccr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Seccr2")
.field("ps", &self.ps())
.field("es", &self.es())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Seccr2 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Seccr2 {{ ps: {=bool:?}, es: {=bool:?} }}", self.ps(), self.es())
}
}
#[doc = "FLASH secure HDP control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Sechdpcr(pub u32);
impl Sechdpcr {
#[doc = "HDP1 area access disable When set, this bit is only cleared by a system reset."]
#[inline(always)]
pub const fn hdp1_accdis(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "HDP1 area access disable When set, this bit is only cleared by a system reset."]
#[inline(always)]
pub fn set_hdp1_accdis(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "HDP2 area access disable When set, this bit is only cleared by a system reset."]
#[inline(always)]
pub const fn hdp2_accdis(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "HDP2 area access disable When set, this bit is only cleared by a system reset."]
#[inline(always)]
pub fn set_hdp2_accdis(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
}
impl Default for Sechdpcr {
#[inline(always)]
fn default() -> Sechdpcr {
Sechdpcr(0)
}
}
impl core::fmt::Debug for Sechdpcr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sechdpcr")
.field("hdp1_accdis", &self.hdp1_accdis())
.field("hdp2_accdis", &self.hdp2_accdis())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Sechdpcr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Sechdpcr {{ hdp1_accdis: {=bool:?}, hdp2_accdis: {=bool:?} }}",
self.hdp1_accdis(),
self.hdp2_accdis()
)
}
}
#[doc = "FLASH secure status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Secsr(pub u32);
impl Secsr {
#[doc = "Secure end of operation This bit is set by hardware when one or more memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in SECCR1). This bit is cleared by writing�1."]
#[inline(always)]
pub const fn eop(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Secure end of operation This bit is set by hardware when one or more memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in SECCR1). This bit is cleared by writing�1."]
#[inline(always)]
pub fn set_eop(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Secure operation error This bit is set by hardware when a memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1."]
#[inline(always)]
pub const fn operr(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Secure operation error This bit is set by hardware when a memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1."]
#[inline(always)]
pub fn set_operr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Secure programming error This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."]
#[inline(always)]
pub const fn progerr(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Secure programming error This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1."]
#[inline(always)]
pub fn set_progerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "Secure write protection error This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting."]
#[inline(always)]
pub const fn wrperr(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "Secure write protection error This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP or HDP) of the memory. This bit is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting."]
#[inline(always)]
pub fn set_wrperr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "Secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1."]
#[inline(always)]
pub const fn pgaerr(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1."]
#[inline(always)]
pub fn set_pgaerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Secure size error This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1."]
#[inline(always)]
pub const fn sizerr(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "Secure size error This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1."]
#[inline(always)]
pub fn set_sizerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "Secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting."]
#[inline(always)]
pub const fn pgserr(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "Secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to Section�7.3.10: memory errors flags for full conditions of error flag setting."]
#[inline(always)]
pub fn set_pgserr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "Secure busy This bit indicates that a memory secure or non-secure operation is in progress. This is set on the beginning of a operation and reset when the operation finishes or when an error occurs."]
#[inline(always)]
pub const fn bsy(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Secure busy This bit indicates that a memory secure or non-secure operation is in progress. This is set on the beginning of a operation and reset when the operation finishes or when an error occurs."]
#[inline(always)]
pub fn set_bsy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Secure wait data to write This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."]
#[inline(always)]
pub const fn wdw(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Secure wait data to write This bit indicates that the memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the memory."]
#[inline(always)]
pub fn set_wdw(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
}
impl Default for Secsr {
#[inline(always)]
fn default() -> Secsr {
Secsr(0)
}
}
impl core::fmt::Debug for Secsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Secsr")
.field("eop", &self.eop())
.field("operr", &self.operr())
.field("progerr", &self.progerr())
.field("wrperr", &self.wrperr())
.field("pgaerr", &self.pgaerr())
.field("sizerr", &self.sizerr())
.field("pgserr", &self.pgserr())
.field("bsy", &self.bsy())
.field("wdw", &self.wdw())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Secsr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Secsr {{ eop: {=bool:?}, operr: {=bool:?}, progerr: {=bool:?}, wrperr: {=bool:?}, pgaerr: {=bool:?}, sizerr: {=bool:?}, pgserr: {=bool:?}, bsy: {=bool:?}, wdw: {=bool:?} }}" , self . eop () , self . operr () , self . progerr () , self . wrperr () , self . pgaerr () , self . sizerr () , self . pgserr () , self . bsy () , self . wdw ())
}
}
#[doc = "FLASH secure watermark1 register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Secwm1r1(pub u32);
impl Secwm1r1 {
#[doc = "Start page of first secure area This field contains the first page of the secure area in bank 1."]
#[inline(always)]
pub const fn secwm1_pstrt(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x7f;
val as u8
}
#[doc = "Start page of first secure area This field contains the first page of the secure area in bank 1."]
#[inline(always)]
pub fn set_secwm1_pstrt(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
}
#[doc = "End page of first secure area This field contains the last page of the secure area in bank 1."]
#[inline(always)]
pub const fn secwm1_pend(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x7f;
val as u8
}
#[doc = "End page of first secure area This field contains the last page of the secure area in bank 1."]
#[inline(always)]
pub fn set_secwm1_pend(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
}
}
impl Default for Secwm1r1 {
#[inline(always)]
fn default() -> Secwm1r1 {
Secwm1r1(0)
}
}
impl core::fmt::Debug for Secwm1r1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Secwm1r1")
.field("secwm1_pstrt", &self.secwm1_pstrt())
.field("secwm1_pend", &self.secwm1_pend())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Secwm1r1 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Secwm1r1 {{ secwm1_pstrt: {=u8:?}, secwm1_pend: {=u8:?} }}",
self.secwm1_pstrt(),
self.secwm1_pend()
)
}
}
#[doc = "FLASH secure watermark1 register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Secwm1r2(pub u32);
impl Secwm1r2 {
#[doc = "End page of first hide protection area This field contains the last page of the HDP area in bank 1."]
#[inline(always)]
pub const fn hdp1_pend(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x7f;
val as u8
}
#[doc = "End page of first hide protection area This field contains the last page of the HDP area in bank 1."]
#[inline(always)]
pub fn set_hdp1_pend(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
}
#[doc = "Hide protection first area enable"]
#[inline(always)]
pub const fn hdp1en(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Hide protection first area enable"]
#[inline(always)]
pub fn set_hdp1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Secwm1r2 {
#[inline(always)]
fn default() -> Secwm1r2 {
Secwm1r2(0)
}
}
impl core::fmt::Debug for Secwm1r2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Secwm1r2")
.field("hdp1_pend", &self.hdp1_pend())
.field("hdp1en", &self.hdp1en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Secwm1r2 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Secwm1r2 {{ hdp1_pend: {=u8:?}, hdp1en: {=bool:?} }}",
self.hdp1_pend(),
self.hdp1en()
)
}
}
#[doc = "FLASH secure watermark2 register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Secwm2r1(pub u32);
impl Secwm2r1 {
#[doc = "WRP area B start page This field contains the first page of the secure area in bank 2."]
#[inline(always)]
pub const fn secwm2_pstrt(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x7f;
val as u8
}
#[doc = "WRP area B start page This field contains the first page of the secure area in bank 2."]
#[inline(always)]
pub fn set_secwm2_pstrt(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
}
#[doc = "End page of secure area This field contains the last page of the secure area in bank 2."]
#[inline(always)]
pub const fn secwm2_pend(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x7f;
val as u8
}
#[doc = "End page of secure area This field contains the last page of the secure area in bank 2."]
#[inline(always)]
pub fn set_secwm2_pend(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
}
}
impl Default for Secwm2r1 {
#[inline(always)]
fn default() -> Secwm2r1 {
Secwm2r1(0)
}
}
impl core::fmt::Debug for Secwm2r1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Secwm2r1")
.field("secwm2_pstrt", &self.secwm2_pstrt())
.field("secwm2_pend", &self.secwm2_pend())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Secwm2r1 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Secwm2r1 {{ secwm2_pstrt: {=u8:?}, secwm2_pend: {=u8:?} }}",
self.secwm2_pstrt(),
self.secwm2_pend()
)
}
}
#[doc = "FLASH secure watermark2 register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Secwm2r2(pub u32);
impl Secwm2r2 {
#[doc = "Bank 2 end page of secure hide protection area This field contains the last page of the secure HDP area in bank 2."]
#[inline(always)]
pub const fn hdp2_pend(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x7f;
val as u8
}
#[doc = "Bank 2 end page of secure hide protection area This field contains the last page of the secure HDP area in bank 2."]
#[inline(always)]
pub fn set_hdp2_pend(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
}
#[doc = "Bank 2 secure Hide protection area enable"]
#[inline(always)]
pub const fn hdp2en(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Bank 2 secure Hide protection area enable"]
#[inline(always)]
pub fn set_hdp2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Secwm2r2 {
#[inline(always)]
fn default() -> Secwm2r2 {
Secwm2r2(0)
}
}
impl core::fmt::Debug for Secwm2r2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Secwm2r2")
.field("hdp2_pend", &self.hdp2_pend())
.field("hdp2en", &self.hdp2en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Secwm2r2 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Secwm2r2 {{ hdp2_pend: {=u8:?}, hdp2en: {=bool:?} }}",
self.hdp2_pend(),
self.hdp2en()
)
}
}
#[doc = "FLASH WRP1 area A address register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Wrp1ar(pub u32);
impl Wrp1ar {
#[doc = "WPR area A start page This field contains the first page of the WPR area A. Note that bit 6 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub const fn wrp1a_pstrt(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x7f;
val as u8
}
#[doc = "WPR area A start page This field contains the first page of the WPR area A. Note that bit 6 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub fn set_wrp1a_pstrt(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
}
#[doc = "WPR area A end page This field contains the last page of the WPR area A. Note that bit 22 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub const fn wrp1a_pend(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x7f;
val as u8
}
#[doc = "WPR area A end page This field contains the last page of the WPR area A. Note that bit 22 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub fn set_wrp1a_pend(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
}
#[doc = "WPR area A unlock"]
#[inline(always)]
pub const fn unlock(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "WPR area A unlock"]
#[inline(always)]
pub fn set_unlock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Wrp1ar {
#[inline(always)]
fn default() -> Wrp1ar {
Wrp1ar(0)
}
}
impl core::fmt::Debug for Wrp1ar {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wrp1ar")
.field("wrp1a_pstrt", &self.wrp1a_pstrt())
.field("wrp1a_pend", &self.wrp1a_pend())
.field("unlock", &self.unlock())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Wrp1ar {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Wrp1ar {{ wrp1a_pstrt: {=u8:?}, wrp1a_pend: {=u8:?}, unlock: {=bool:?} }}",
self.wrp1a_pstrt(),
self.wrp1a_pend(),
self.unlock()
)
}
}
#[doc = "FLASH WRP1 area B address register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Wrp1br(pub u32);
impl Wrp1br {
#[doc = "WRP area B start page This field contains the first page of the WRP area B. Note that bit 6 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub const fn wrp1b_pstrt(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x7f;
val as u8
}
#[doc = "WRP area B start page This field contains the first page of the WRP area B. Note that bit 6 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub fn set_wrp1b_pstrt(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
}
#[doc = "WRP area B end page This field contains the last page of the WRP area B. Note that bit 22 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub const fn wrp1b_pend(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x7f;
val as u8
}
#[doc = "WRP area B end page This field contains the last page of the WRP area B. Note that bit 22 is reserved on STM32WBAxEx devices."]
#[inline(always)]
pub fn set_wrp1b_pend(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
}
#[doc = "WPR area B unlock"]
#[inline(always)]
pub const fn unlock(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "WPR area B unlock"]
#[inline(always)]
pub fn set_unlock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Wrp1br {
#[inline(always)]
fn default() -> Wrp1br {
Wrp1br(0)
}
}
impl core::fmt::Debug for Wrp1br {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wrp1br")
.field("wrp1b_pstrt", &self.wrp1b_pstrt())
.field("wrp1b_pend", &self.wrp1b_pend())
.field("unlock", &self.unlock())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Wrp1br {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Wrp1br {{ wrp1b_pstrt: {=u8:?}, wrp1b_pend: {=u8:?}, unlock: {=bool:?} }}",
self.wrp1b_pstrt(),
self.wrp1b_pend(),
self.unlock()
)
}
}
#[doc = "FLASH WPR2 area A address register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Wrp2ar(pub u32);
impl Wrp2ar {
#[doc = "WRP bank 2 area A start page This field contains the first page of the WRP bank 2 area A."]
#[inline(always)]
pub const fn wrp2a_pstrt(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x7f;
val as u8
}
#[doc = "WRP bank 2 area A start page This field contains the first page of the WRP bank 2 area A."]
#[inline(always)]
pub fn set_wrp2a_pstrt(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
}
#[doc = "WRP bank 2 area A end page This field contains the last page of the WRP bank 2 area A."]
#[inline(always)]
pub const fn wrp2a_pend(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x7f;
val as u8
}
#[doc = "WRP bank 2 area A end page This field contains the last page of the WRP bank 2 area A."]
#[inline(always)]
pub fn set_wrp2a_pend(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
}
#[doc = "WPR bank 2 area A unlock"]
#[inline(always)]
pub const fn unlock(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "WPR bank 2 area A unlock"]
#[inline(always)]
pub fn set_unlock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Wrp2ar {
#[inline(always)]
fn default() -> Wrp2ar {
Wrp2ar(0)
}
}
impl core::fmt::Debug for Wrp2ar {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wrp2ar")
.field("wrp2a_pstrt", &self.wrp2a_pstrt())
.field("wrp2a_pend", &self.wrp2a_pend())
.field("unlock", &self.unlock())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Wrp2ar {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Wrp2ar {{ wrp2a_pstrt: {=u8:?}, wrp2a_pend: {=u8:?}, unlock: {=bool:?} }}",
self.wrp2a_pstrt(),
self.wrp2a_pend(),
self.unlock()
)
}
}
#[doc = "FLASH WPR2 area B address register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Wrp2br(pub u32);
impl Wrp2br {
#[doc = "WRP bank 2 area B start page This field contains the first page of the WRP bank 2 area B."]
#[inline(always)]
pub const fn wrp2b_pstrt(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x7f;
val as u8
}
#[doc = "WRP bank 2 area B start page This field contains the first page of the WRP bank 2 area B."]
#[inline(always)]
pub fn set_wrp2b_pstrt(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
}
#[doc = "WRP bank 2 area B end page This field contains the last page of the WRP bank 2 area B."]
#[inline(always)]
pub const fn wrp2b_pend(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x7f;
val as u8
}
#[doc = "WRP bank 2 area B end page This field contains the last page of the WRP bank 2 area B."]
#[inline(always)]
pub fn set_wrp2b_pend(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
}
#[doc = "WPR bank 2 area B unlock"]
#[inline(always)]
pub const fn unlock(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "WPR bank 2 area B unlock"]
#[inline(always)]
pub fn set_unlock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Wrp2br {
#[inline(always)]
fn default() -> Wrp2br {
Wrp2br(0)
}
}
impl core::fmt::Debug for Wrp2br {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wrp2br")
.field("wrp2b_pstrt", &self.wrp2b_pstrt())
.field("wrp2b_pend", &self.wrp2b_pend())
.field("unlock", &self.unlock())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Wrp2br {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Wrp2br {{ wrp2b_pstrt: {=u8:?}, wrp2b_pend: {=u8:?}, unlock: {=bool:?} }}",
self.wrp2b_pstrt(),
self.wrp2b_pend(),
self.unlock()
)
}
}
}
pub mod vals {
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum BorLev {
#[doc = "BOR level 0 (reset level threshold around 1.7V)"]
LEVEL0 = 0x0,
#[doc = "BOR level 1 (reset level threshold around 2.0V)"]
LEVEL1 = 0x01,
#[doc = "BOR level 2 (reset level threshold around 2.2V)"]
LEVEL2 = 0x02,
#[doc = "BOR level 3 (reset level threshold around 2.5V)"]
LEVEL3 = 0x03,
#[doc = "BOR level 4 (reset level threshold around 2.8V)"]
LEVEL4 = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl BorLev {
#[inline(always)]
pub const fn from_bits(val: u8) -> BorLev {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for BorLev {
#[inline(always)]
fn from(val: u8) -> BorLev {
BorLev::from_bits(val)
}
}
impl From<BorLev> for u8 {
#[inline(always)]
fn from(val: BorLev) -> u8 {
BorLev::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum CodeOp {
#[doc = "No Flash operation interrupted by previous reset"]
NO_FLASH_INT = 0x0,
#[doc = "Single write operation interrupted"]
SINGLE_WR_INT = 0x01,
#[doc = "Burst write operation interrupted"]
BURST_WR_INT = 0x02,
#[doc = "Page erase operation interrupted"]
PG_ERASE_INT = 0x03,
#[doc = "Bank erase operation interrupted"]
BANK_ERASE_INT = 0x04,
#[doc = "Mass erase operation interrupted"]
MASS_ERASE_INT = 0x05,
#[doc = "Option change operation interrupted"]
OPT_CHANGE_INT = 0x06,
_RESERVED_7 = 0x07,
}
impl CodeOp {
#[inline(always)]
pub const fn from_bits(val: u8) -> CodeOp {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for CodeOp {
#[inline(always)]
fn from(val: u8) -> CodeOp {
CodeOp::from_bits(val)
}
}
impl From<CodeOp> for u8 {
#[inline(always)]
fn from(val: CodeOp) -> u8 {
CodeOp::to_bits(val)
}
}
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
pub struct Rdp(u8);
impl Rdp {
#[doc = "Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1)"]
pub const B_0X55: Self = Self(0x55);
#[doc = "Level 0 (readout protection not active)"]
pub const B_0X_AA: Self = Self(0xaa);
#[doc = "Level 2 (chip readout protection active)"]
pub const B_0X_CC: Self = Self(0xcc);
}
impl Rdp {
pub const fn from_bits(val: u8) -> Rdp {
Self(val & 0xff)
}
pub const fn to_bits(self) -> u8 {
self.0
}
}
impl core::fmt::Debug for Rdp {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
match self.0 {
0x55 => f.write_str("B_0X55"),
0xaa => f.write_str("B_0X_AA"),
0xcc => f.write_str("B_0X_CC"),
other => core::write!(f, "0x{:02X}", other),
}
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Rdp {
fn format(&self, f: defmt::Formatter) {
match self.0 {
0x55 => defmt::write!(f, "B_0X55"),
0xaa => defmt::write!(f, "B_0X_AA"),
0xcc => defmt::write!(f, "B_0X_CC"),
other => defmt::write!(f, "0x{:02X}", other),
}
}
}
impl From<u8> for Rdp {
#[inline(always)]
fn from(val: u8) -> Rdp {
Rdp::from_bits(val)
}
}
impl From<Rdp> for u8 {
#[inline(always)]
fn from(val: Rdp) -> u8 {
Rdp::to_bits(val)
}
}
}