#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
#[doc = "Reset and clock control"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Rcc {
ptr: *mut u8,
}
unsafe impl Send for Rcc {}
unsafe impl Sync for Rcc {}
impl Rcc {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "Clock control register"]
#[inline(always)]
pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "Internal clock sources calibration register"]
#[inline(always)]
pub const fn icscr(self) -> crate::common::Reg<regs::Icscr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "Clock configuration register"]
#[inline(always)]
pub const fn cfgr(self) -> crate::common::Reg<regs::Cfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
}
#[doc = "PLL configuration register"]
#[inline(always)]
pub const fn pllcfgr(self) -> crate::common::Reg<regs::Pllcfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
#[doc = "Clock interrupt enable register"]
#[inline(always)]
pub const fn cier(self) -> crate::common::Reg<regs::Cier, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
}
#[doc = "Clock interrupt flag register"]
#[inline(always)]
pub const fn cifr(self) -> crate::common::Reg<regs::Cifr, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
}
#[doc = "Clock interrupt clear register"]
#[inline(always)]
pub const fn cicr(self) -> crate::common::Reg<regs::Cicr, crate::common::W> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
}
#[doc = "GPIO reset register"]
#[inline(always)]
pub const fn gpiorstr(self) -> crate::common::Reg<regs::Gpiorstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
}
#[doc = "AHB peripheral reset register"]
#[inline(always)]
pub const fn ahbrstr(self) -> crate::common::Reg<regs::Ahbrstr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
}
#[doc = "APB peripheral reset register 1"]
#[inline(always)]
pub const fn apbrstr1(self) -> crate::common::Reg<regs::Apbrstr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
}
#[doc = "APB peripheral reset register 2"]
#[inline(always)]
pub const fn apbrstr2(self) -> crate::common::Reg<regs::Apbrstr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
}
#[doc = "GPIO clock enable register"]
#[inline(always)]
pub const fn gpioenr(self) -> crate::common::Reg<regs::Gpioenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
}
#[doc = "AHB peripheral clock enable register"]
#[inline(always)]
pub const fn ahbenr(self) -> crate::common::Reg<regs::Ahbenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
}
#[doc = "APB peripheral clock enable register 1"]
#[inline(always)]
pub const fn apbenr1(self) -> crate::common::Reg<regs::Apbenr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
}
#[doc = "APB peripheral clock enable register 2"]
#[inline(always)]
pub const fn apbenr2(self) -> crate::common::Reg<regs::Apbenr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
}
#[doc = "GPIO in Sleep mode clock enable register"]
#[inline(always)]
pub const fn gpiosmenr(self) -> crate::common::Reg<regs::Gpiosmenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
}
#[doc = "AHB peripheral clock enable in Sleep mode register"]
#[inline(always)]
pub const fn ahbsmenr(self) -> crate::common::Reg<regs::Ahbsmenr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
}
#[doc = "APB peripheral clock enable in Sleep mode register 1"]
#[inline(always)]
pub const fn apbsmenr1(self) -> crate::common::Reg<regs::Apbsmenr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
}
#[doc = "APB peripheral clock enable in Sleep mode register 2"]
#[inline(always)]
pub const fn apbsmenr2(self) -> crate::common::Reg<regs::Apbsmenr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
}
#[doc = "Peripherals independent clock configuration register"]
#[inline(always)]
pub const fn ccipr(self) -> crate::common::Reg<regs::Ccipr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
}
#[doc = "Peripherals independent clock configuration register 2"]
#[inline(always)]
pub const fn ccipr2(self) -> crate::common::Reg<regs::Ccipr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
}
#[doc = "RTC domain control register"]
#[inline(always)]
pub const fn bdcr(self) -> crate::common::Reg<regs::Bdcr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
}
#[doc = "Control/status register"]
#[inline(always)]
pub const fn csr(self) -> crate::common::Reg<regs::Csr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
}
}
pub mod regs {
#[doc = "AHB peripheral clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahbenr(pub u32);
impl Ahbenr {
#[doc = "DMA1 clock enable"]
#[inline(always)]
pub const fn dma1en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "DMA1 clock enable"]
#[inline(always)]
pub fn set_dma1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "DMA2 clock enable"]
#[inline(always)]
pub const fn dma2en(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "DMA2 clock enable"]
#[inline(always)]
pub fn set_dma2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Flash memory interface clock enable"]
#[inline(always)]
pub const fn flashen(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Flash memory interface clock enable"]
#[inline(always)]
pub fn set_flashen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "CRC clock enable"]
#[inline(always)]
pub const fn crcen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC clock enable"]
#[inline(always)]
pub fn set_crcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "AES hardware accelerator"]
#[inline(always)]
pub const fn aesen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "AES hardware accelerator"]
#[inline(always)]
pub fn set_aesen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Random number generator clock enable"]
#[inline(always)]
pub const fn rngen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "Random number generator clock enable"]
#[inline(always)]
pub fn set_rngen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for Ahbenr {
#[inline(always)]
fn default() -> Ahbenr {
Ahbenr(0)
}
}
impl core::fmt::Debug for Ahbenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahbenr")
.field("dma1en", &self.dma1en())
.field("dma2en", &self.dma2en())
.field("flashen", &self.flashen())
.field("crcen", &self.crcen())
.field("aesen", &self.aesen())
.field("rngen", &self.rngen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahbenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahbenr {{ dma1en: {=bool:?}, dma2en: {=bool:?}, flashen: {=bool:?}, crcen: {=bool:?}, aesen: {=bool:?}, rngen: {=bool:?} }}" , self . dma1en () , self . dma2en () , self . flashen () , self . crcen () , self . aesen () , self . rngen ())
}
}
#[doc = "AHB peripheral reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahbrstr(pub u32);
impl Ahbrstr {
#[doc = "DMA1 reset"]
#[inline(always)]
pub const fn dma1rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "DMA1 reset"]
#[inline(always)]
pub fn set_dma1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "DMA1 reset"]
#[inline(always)]
pub const fn dma2rst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "DMA1 reset"]
#[inline(always)]
pub fn set_dma2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "FLASH reset"]
#[inline(always)]
pub const fn flashrst(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "FLASH reset"]
#[inline(always)]
pub fn set_flashrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "CRC reset"]
#[inline(always)]
pub const fn crcrst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC reset"]
#[inline(always)]
pub fn set_crcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "AES hardware accelerator reset"]
#[inline(always)]
pub const fn aesrst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "AES hardware accelerator reset"]
#[inline(always)]
pub fn set_aesrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Random number generator reset"]
#[inline(always)]
pub const fn rngrst(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "Random number generator reset"]
#[inline(always)]
pub fn set_rngrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for Ahbrstr {
#[inline(always)]
fn default() -> Ahbrstr {
Ahbrstr(0)
}
}
impl core::fmt::Debug for Ahbrstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahbrstr")
.field("dma1rst", &self.dma1rst())
.field("dma2rst", &self.dma2rst())
.field("flashrst", &self.flashrst())
.field("crcrst", &self.crcrst())
.field("aesrst", &self.aesrst())
.field("rngrst", &self.rngrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahbrstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahbrstr {{ dma1rst: {=bool:?}, dma2rst: {=bool:?}, flashrst: {=bool:?}, crcrst: {=bool:?}, aesrst: {=bool:?}, rngrst: {=bool:?} }}" , self . dma1rst () , self . dma2rst () , self . flashrst () , self . crcrst () , self . aesrst () , self . rngrst ())
}
}
#[doc = "AHB peripheral clock enable in Sleep mode register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahbsmenr(pub u32);
impl Ahbsmenr {
#[doc = "DMA1 clock enable during Sleep mode"]
#[inline(always)]
pub const fn dma1smen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "DMA1 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_dma1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "DMA2 clock enable during Sleep mode"]
#[inline(always)]
pub const fn dma2smen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "DMA2 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_dma2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Flash memory interface clock enable during Sleep mode"]
#[inline(always)]
pub const fn flashsmen(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Flash memory interface clock enable during Sleep mode"]
#[inline(always)]
pub fn set_flashsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "SRAM clock enable during Sleep mode"]
#[inline(always)]
pub const fn sramsmen(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "SRAM clock enable during Sleep mode"]
#[inline(always)]
pub fn set_sramsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "CRC clock enable during Sleep mode"]
#[inline(always)]
pub const fn crcsmen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "CRC clock enable during Sleep mode"]
#[inline(always)]
pub fn set_crcsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "AES hardware accelerator clock enable during Sleep mode"]
#[inline(always)]
pub const fn aessmen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "AES hardware accelerator clock enable during Sleep mode"]
#[inline(always)]
pub fn set_aessmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Random number generator clock enable during Sleep mode"]
#[inline(always)]
pub const fn rngsmen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "Random number generator clock enable during Sleep mode"]
#[inline(always)]
pub fn set_rngsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for Ahbsmenr {
#[inline(always)]
fn default() -> Ahbsmenr {
Ahbsmenr(0)
}
}
impl core::fmt::Debug for Ahbsmenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahbsmenr")
.field("dma1smen", &self.dma1smen())
.field("dma2smen", &self.dma2smen())
.field("flashsmen", &self.flashsmen())
.field("sramsmen", &self.sramsmen())
.field("crcsmen", &self.crcsmen())
.field("aessmen", &self.aessmen())
.field("rngsmen", &self.rngsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahbsmenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahbsmenr {{ dma1smen: {=bool:?}, dma2smen: {=bool:?}, flashsmen: {=bool:?}, sramsmen: {=bool:?}, crcsmen: {=bool:?}, aessmen: {=bool:?}, rngsmen: {=bool:?} }}" , self . dma1smen () , self . dma2smen () , self . flashsmen () , self . sramsmen () , self . crcsmen () , self . aessmen () , self . rngsmen ())
}
}
#[doc = "APB peripheral clock enable register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbenr1(pub u32);
impl Apbenr1 {
#[doc = "TIM2 timer clock enable"]
#[inline(always)]
pub const fn tim2en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 timer clock enable"]
#[inline(always)]
pub fn set_tim2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM3 timer clock enable"]
#[inline(always)]
pub const fn tim3en(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "TIM3 timer clock enable"]
#[inline(always)]
pub fn set_tim3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "TIM4 timer clock enable"]
#[inline(always)]
pub const fn tim4en(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "TIM4 timer clock enable"]
#[inline(always)]
pub fn set_tim4en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "TIM6 timer clock enable"]
#[inline(always)]
pub const fn tim6en(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "TIM6 timer clock enable"]
#[inline(always)]
pub fn set_tim6en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "TIM7 timer clock enable"]
#[inline(always)]
pub const fn tim7en(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "TIM7 timer clock enable"]
#[inline(always)]
pub fn set_tim7en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "LPUART2 clock enable"]
#[inline(always)]
pub const fn lpuart2en(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "LPUART2 clock enable"]
#[inline(always)]
pub fn set_lpuart2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "USART5EN"]
#[inline(always)]
pub const fn usart5en(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "USART5EN"]
#[inline(always)]
pub fn set_usart5en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "USART6EN"]
#[inline(always)]
pub const fn usart6en(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "USART6EN"]
#[inline(always)]
pub fn set_usart6en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "RTC APB clock enable"]
#[inline(always)]
pub const fn rtcapben(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "RTC APB clock enable"]
#[inline(always)]
pub fn set_rtcapben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "WWDG clock enable"]
#[inline(always)]
pub const fn wwdgen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "WWDG clock enable"]
#[inline(always)]
pub fn set_wwdgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "USBEN"]
#[inline(always)]
pub const fn fdcanen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "USBEN"]
#[inline(always)]
pub fn set_fdcanen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USBEN"]
#[inline(always)]
pub const fn usben(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "USBEN"]
#[inline(always)]
pub fn set_usben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "SPI2 clock enable"]
#[inline(always)]
pub const fn spi2en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 clock enable"]
#[inline(always)]
pub fn set_spi2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "SPI3 clock enable"]
#[inline(always)]
pub const fn spi3en(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "SPI3 clock enable"]
#[inline(always)]
pub fn set_spi3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "CRSEN"]
#[inline(always)]
pub const fn crsen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "CRSEN"]
#[inline(always)]
pub fn set_crsen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "USART2 clock enable"]
#[inline(always)]
pub const fn usart2en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 clock enable"]
#[inline(always)]
pub fn set_usart2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART3 clock enable"]
#[inline(always)]
pub const fn usart3en(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART3 clock enable"]
#[inline(always)]
pub fn set_usart3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "USART4 clock enable"]
#[inline(always)]
pub const fn usart4en(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "USART4 clock enable"]
#[inline(always)]
pub fn set_usart4en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "LPUART1 clock enable"]
#[inline(always)]
pub const fn lpuart1en(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "LPUART1 clock enable"]
#[inline(always)]
pub fn set_lpuart1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "I2C1 clock enable"]
#[inline(always)]
pub const fn i2c1en(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 clock enable"]
#[inline(always)]
pub fn set_i2c1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 clock enable"]
#[inline(always)]
pub const fn i2c2en(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 clock enable"]
#[inline(always)]
pub fn set_i2c2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "I2C3 clock enable"]
#[inline(always)]
pub const fn i2c3en(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "I2C3 clock enable"]
#[inline(always)]
pub fn set_i2c3en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "HDMI CEC clock enable"]
#[inline(always)]
pub const fn cecen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "HDMI CEC clock enable"]
#[inline(always)]
pub fn set_cecen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "UCPD1 clock enable"]
#[inline(always)]
pub const fn ucpd1en(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "UCPD1 clock enable"]
#[inline(always)]
pub fn set_ucpd1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "UCPD2 clock enable"]
#[inline(always)]
pub const fn ucpd2en(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "UCPD2 clock enable"]
#[inline(always)]
pub fn set_ucpd2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "Debug support clock enable"]
#[inline(always)]
pub const fn dbgen(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "Debug support clock enable"]
#[inline(always)]
pub fn set_dbgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Power interface clock enable"]
#[inline(always)]
pub const fn pwren(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Power interface clock enable"]
#[inline(always)]
pub fn set_pwren(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "DAC1 interface clock enable"]
#[inline(always)]
pub const fn dac1en(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "DAC1 interface clock enable"]
#[inline(always)]
pub fn set_dac1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "LPTIM2 clock enable"]
#[inline(always)]
pub const fn lptim2en(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "LPTIM2 clock enable"]
#[inline(always)]
pub fn set_lptim2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "LPTIM1 clock enable"]
#[inline(always)]
pub const fn lptim1en(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "LPTIM1 clock enable"]
#[inline(always)]
pub fn set_lptim1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apbenr1 {
#[inline(always)]
fn default() -> Apbenr1 {
Apbenr1(0)
}
}
impl core::fmt::Debug for Apbenr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbenr1")
.field("tim2en", &self.tim2en())
.field("tim3en", &self.tim3en())
.field("tim4en", &self.tim4en())
.field("tim6en", &self.tim6en())
.field("tim7en", &self.tim7en())
.field("lpuart2en", &self.lpuart2en())
.field("usart5en", &self.usart5en())
.field("usart6en", &self.usart6en())
.field("rtcapben", &self.rtcapben())
.field("wwdgen", &self.wwdgen())
.field("fdcanen", &self.fdcanen())
.field("usben", &self.usben())
.field("spi2en", &self.spi2en())
.field("spi3en", &self.spi3en())
.field("crsen", &self.crsen())
.field("usart2en", &self.usart2en())
.field("usart3en", &self.usart3en())
.field("usart4en", &self.usart4en())
.field("lpuart1en", &self.lpuart1en())
.field("i2c1en", &self.i2c1en())
.field("i2c2en", &self.i2c2en())
.field("i2c3en", &self.i2c3en())
.field("cecen", &self.cecen())
.field("ucpd1en", &self.ucpd1en())
.field("ucpd2en", &self.ucpd2en())
.field("dbgen", &self.dbgen())
.field("pwren", &self.pwren())
.field("dac1en", &self.dac1en())
.field("lptim2en", &self.lptim2en())
.field("lptim1en", &self.lptim1en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbenr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbenr1 {{ tim2en: {=bool:?}, tim3en: {=bool:?}, tim4en: {=bool:?}, tim6en: {=bool:?}, tim7en: {=bool:?}, lpuart2en: {=bool:?}, usart5en: {=bool:?}, usart6en: {=bool:?}, rtcapben: {=bool:?}, wwdgen: {=bool:?}, fdcanen: {=bool:?}, usben: {=bool:?}, spi2en: {=bool:?}, spi3en: {=bool:?}, crsen: {=bool:?}, usart2en: {=bool:?}, usart3en: {=bool:?}, usart4en: {=bool:?}, lpuart1en: {=bool:?}, i2c1en: {=bool:?}, i2c2en: {=bool:?}, i2c3en: {=bool:?}, cecen: {=bool:?}, ucpd1en: {=bool:?}, ucpd2en: {=bool:?}, dbgen: {=bool:?}, pwren: {=bool:?}, dac1en: {=bool:?}, lptim2en: {=bool:?}, lptim1en: {=bool:?} }}" , self . tim2en () , self . tim3en () , self . tim4en () , self . tim6en () , self . tim7en () , self . lpuart2en () , self . usart5en () , self . usart6en () , self . rtcapben () , self . wwdgen () , self . fdcanen () , self . usben () , self . spi2en () , self . spi3en () , self . crsen () , self . usart2en () , self . usart3en () , self . usart4en () , self . lpuart1en () , self . i2c1en () , self . i2c2en () , self . i2c3en () , self . cecen () , self . ucpd1en () , self . ucpd2en () , self . dbgen () , self . pwren () , self . dac1en () , self . lptim2en () , self . lptim1en ())
}
}
#[doc = "APB peripheral clock enable register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbenr2(pub u32);
impl Apbenr2 {
#[doc = "SYSCFG, COMP and VREFBUF clock enable"]
#[inline(always)]
pub const fn syscfgen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "SYSCFG, COMP and VREFBUF clock enable"]
#[inline(always)]
pub fn set_syscfgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM1 timer clock enable"]
#[inline(always)]
pub const fn tim1en(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 timer clock enable"]
#[inline(always)]
pub fn set_tim1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 clock enable"]
#[inline(always)]
pub const fn spi1en(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 clock enable"]
#[inline(always)]
pub fn set_spi1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1 clock enable"]
#[inline(always)]
pub const fn usart1en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 clock enable"]
#[inline(always)]
pub fn set_usart1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM14 timer clock enable"]
#[inline(always)]
pub const fn tim14en(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "TIM14 timer clock enable"]
#[inline(always)]
pub fn set_tim14en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "TIM15 timer clock enable"]
#[inline(always)]
pub const fn tim15en(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "TIM15 timer clock enable"]
#[inline(always)]
pub fn set_tim15en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "TIM16 timer clock enable"]
#[inline(always)]
pub const fn tim16en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer clock enable"]
#[inline(always)]
pub fn set_tim16en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM16 timer clock enable"]
#[inline(always)]
pub const fn tim17en(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer clock enable"]
#[inline(always)]
pub fn set_tim17en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "ADC clock enable"]
#[inline(always)]
pub const fn adcen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "ADC clock enable"]
#[inline(always)]
pub fn set_adcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Apbenr2 {
#[inline(always)]
fn default() -> Apbenr2 {
Apbenr2(0)
}
}
impl core::fmt::Debug for Apbenr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbenr2")
.field("syscfgen", &self.syscfgen())
.field("tim1en", &self.tim1en())
.field("spi1en", &self.spi1en())
.field("usart1en", &self.usart1en())
.field("tim14en", &self.tim14en())
.field("tim15en", &self.tim15en())
.field("tim16en", &self.tim16en())
.field("tim17en", &self.tim17en())
.field("adcen", &self.adcen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbenr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbenr2 {{ syscfgen: {=bool:?}, tim1en: {=bool:?}, spi1en: {=bool:?}, usart1en: {=bool:?}, tim14en: {=bool:?}, tim15en: {=bool:?}, tim16en: {=bool:?}, tim17en: {=bool:?}, adcen: {=bool:?} }}" , self . syscfgen () , self . tim1en () , self . spi1en () , self . usart1en () , self . tim14en () , self . tim15en () , self . tim16en () , self . tim17en () , self . adcen ())
}
}
#[doc = "APB peripheral reset register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbrstr1(pub u32);
impl Apbrstr1 {
#[doc = "TIM2 timer reset"]
#[inline(always)]
pub const fn tim2rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 timer reset"]
#[inline(always)]
pub fn set_tim2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM3 timer reset"]
#[inline(always)]
pub const fn tim3rst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "TIM3 timer reset"]
#[inline(always)]
pub fn set_tim3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "TIM4 timer reset"]
#[inline(always)]
pub const fn tim4rst(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "TIM4 timer reset"]
#[inline(always)]
pub fn set_tim4rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "TIM6 timer reset"]
#[inline(always)]
pub const fn tim6rst(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "TIM6 timer reset"]
#[inline(always)]
pub fn set_tim6rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "TIM7 timer reset"]
#[inline(always)]
pub const fn tim7rst(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "TIM7 timer reset"]
#[inline(always)]
pub fn set_tim7rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "LPUART2RST"]
#[inline(always)]
pub const fn lpuart2rst(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "LPUART2RST"]
#[inline(always)]
pub fn set_lpuart2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "USART5RST"]
#[inline(always)]
pub const fn usart5rst(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "USART5RST"]
#[inline(always)]
pub fn set_usart5rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "USART6RST"]
#[inline(always)]
pub const fn usart6rst(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "USART6RST"]
#[inline(always)]
pub fn set_usart6rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "FDCANRST"]
#[inline(always)]
pub const fn fdcanrst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "FDCANRST"]
#[inline(always)]
pub fn set_fdcanrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USBRST"]
#[inline(always)]
pub const fn usbrst(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "USBRST"]
#[inline(always)]
pub fn set_usbrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "SPI2 reset"]
#[inline(always)]
pub const fn spi2rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 reset"]
#[inline(always)]
pub fn set_spi2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "SPI3 reset"]
#[inline(always)]
pub const fn spi3rst(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "SPI3 reset"]
#[inline(always)]
pub fn set_spi3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "CRSRST"]
#[inline(always)]
pub const fn crsrst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "CRSRST"]
#[inline(always)]
pub fn set_crsrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "USART2 reset"]
#[inline(always)]
pub const fn usart2rst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 reset"]
#[inline(always)]
pub fn set_usart2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART3 reset"]
#[inline(always)]
pub const fn usart3rst(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART3 reset"]
#[inline(always)]
pub fn set_usart3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "USART4 reset"]
#[inline(always)]
pub const fn usart4rst(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "USART4 reset"]
#[inline(always)]
pub fn set_usart4rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "LPUART1 reset"]
#[inline(always)]
pub const fn lpuart1rst(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "LPUART1 reset"]
#[inline(always)]
pub fn set_lpuart1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "I2C1 reset"]
#[inline(always)]
pub const fn i2c1rst(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 reset"]
#[inline(always)]
pub fn set_i2c1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 reset"]
#[inline(always)]
pub const fn i2c2rst(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 reset"]
#[inline(always)]
pub fn set_i2c2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "I2C3RST reset"]
#[inline(always)]
pub const fn i2c3rst(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "I2C3RST reset"]
#[inline(always)]
pub fn set_i2c3rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "HDMI CEC reset"]
#[inline(always)]
pub const fn cecrst(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "HDMI CEC reset"]
#[inline(always)]
pub fn set_cecrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "UCPD1 reset"]
#[inline(always)]
pub const fn ucpd1rst(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "UCPD1 reset"]
#[inline(always)]
pub fn set_ucpd1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "UCPD2 reset"]
#[inline(always)]
pub const fn ucpd2rst(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "UCPD2 reset"]
#[inline(always)]
pub fn set_ucpd2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "Debug support reset"]
#[inline(always)]
pub const fn dbgrst(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "Debug support reset"]
#[inline(always)]
pub fn set_dbgrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Power interface reset"]
#[inline(always)]
pub const fn pwrrst(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Power interface reset"]
#[inline(always)]
pub fn set_pwrrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "DAC1 interface reset"]
#[inline(always)]
pub const fn dac1rst(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "DAC1 interface reset"]
#[inline(always)]
pub fn set_dac1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Low Power Timer 2 reset"]
#[inline(always)]
pub const fn lptim2rst(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Low Power Timer 2 reset"]
#[inline(always)]
pub fn set_lptim2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "Low Power Timer 1 reset"]
#[inline(always)]
pub const fn lptim1rst(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Low Power Timer 1 reset"]
#[inline(always)]
pub fn set_lptim1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apbrstr1 {
#[inline(always)]
fn default() -> Apbrstr1 {
Apbrstr1(0)
}
}
impl core::fmt::Debug for Apbrstr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbrstr1")
.field("tim2rst", &self.tim2rst())
.field("tim3rst", &self.tim3rst())
.field("tim4rst", &self.tim4rst())
.field("tim6rst", &self.tim6rst())
.field("tim7rst", &self.tim7rst())
.field("lpuart2rst", &self.lpuart2rst())
.field("usart5rst", &self.usart5rst())
.field("usart6rst", &self.usart6rst())
.field("fdcanrst", &self.fdcanrst())
.field("usbrst", &self.usbrst())
.field("spi2rst", &self.spi2rst())
.field("spi3rst", &self.spi3rst())
.field("crsrst", &self.crsrst())
.field("usart2rst", &self.usart2rst())
.field("usart3rst", &self.usart3rst())
.field("usart4rst", &self.usart4rst())
.field("lpuart1rst", &self.lpuart1rst())
.field("i2c1rst", &self.i2c1rst())
.field("i2c2rst", &self.i2c2rst())
.field("i2c3rst", &self.i2c3rst())
.field("cecrst", &self.cecrst())
.field("ucpd1rst", &self.ucpd1rst())
.field("ucpd2rst", &self.ucpd2rst())
.field("dbgrst", &self.dbgrst())
.field("pwrrst", &self.pwrrst())
.field("dac1rst", &self.dac1rst())
.field("lptim2rst", &self.lptim2rst())
.field("lptim1rst", &self.lptim1rst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbrstr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbrstr1 {{ tim2rst: {=bool:?}, tim3rst: {=bool:?}, tim4rst: {=bool:?}, tim6rst: {=bool:?}, tim7rst: {=bool:?}, lpuart2rst: {=bool:?}, usart5rst: {=bool:?}, usart6rst: {=bool:?}, fdcanrst: {=bool:?}, usbrst: {=bool:?}, spi2rst: {=bool:?}, spi3rst: {=bool:?}, crsrst: {=bool:?}, usart2rst: {=bool:?}, usart3rst: {=bool:?}, usart4rst: {=bool:?}, lpuart1rst: {=bool:?}, i2c1rst: {=bool:?}, i2c2rst: {=bool:?}, i2c3rst: {=bool:?}, cecrst: {=bool:?}, ucpd1rst: {=bool:?}, ucpd2rst: {=bool:?}, dbgrst: {=bool:?}, pwrrst: {=bool:?}, dac1rst: {=bool:?}, lptim2rst: {=bool:?}, lptim1rst: {=bool:?} }}" , self . tim2rst () , self . tim3rst () , self . tim4rst () , self . tim6rst () , self . tim7rst () , self . lpuart2rst () , self . usart5rst () , self . usart6rst () , self . fdcanrst () , self . usbrst () , self . spi2rst () , self . spi3rst () , self . crsrst () , self . usart2rst () , self . usart3rst () , self . usart4rst () , self . lpuart1rst () , self . i2c1rst () , self . i2c2rst () , self . i2c3rst () , self . cecrst () , self . ucpd1rst () , self . ucpd2rst () , self . dbgrst () , self . pwrrst () , self . dac1rst () , self . lptim2rst () , self . lptim1rst ())
}
}
#[doc = "APB peripheral reset register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbrstr2(pub u32);
impl Apbrstr2 {
#[doc = "SYSCFG, COMP and VREFBUF reset"]
#[inline(always)]
pub const fn syscfgrst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "SYSCFG, COMP and VREFBUF reset"]
#[inline(always)]
pub fn set_syscfgrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM1 timer reset"]
#[inline(always)]
pub const fn tim1rst(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 timer reset"]
#[inline(always)]
pub fn set_tim1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 reset"]
#[inline(always)]
pub const fn spi1rst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 reset"]
#[inline(always)]
pub fn set_spi1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1 reset"]
#[inline(always)]
pub const fn usart1rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 reset"]
#[inline(always)]
pub fn set_usart1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM14 timer reset"]
#[inline(always)]
pub const fn tim14rst(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "TIM14 timer reset"]
#[inline(always)]
pub fn set_tim14rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "TIM15 timer reset"]
#[inline(always)]
pub const fn tim15rst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "TIM15 timer reset"]
#[inline(always)]
pub fn set_tim15rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "TIM16 timer reset"]
#[inline(always)]
pub const fn tim16rst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer reset"]
#[inline(always)]
pub fn set_tim16rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM17 timer reset"]
#[inline(always)]
pub const fn tim17rst(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM17 timer reset"]
#[inline(always)]
pub fn set_tim17rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "ADC reset"]
#[inline(always)]
pub const fn adcrst(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "ADC reset"]
#[inline(always)]
pub fn set_adcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Apbrstr2 {
#[inline(always)]
fn default() -> Apbrstr2 {
Apbrstr2(0)
}
}
impl core::fmt::Debug for Apbrstr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbrstr2")
.field("syscfgrst", &self.syscfgrst())
.field("tim1rst", &self.tim1rst())
.field("spi1rst", &self.spi1rst())
.field("usart1rst", &self.usart1rst())
.field("tim14rst", &self.tim14rst())
.field("tim15rst", &self.tim15rst())
.field("tim16rst", &self.tim16rst())
.field("tim17rst", &self.tim17rst())
.field("adcrst", &self.adcrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbrstr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbrstr2 {{ syscfgrst: {=bool:?}, tim1rst: {=bool:?}, spi1rst: {=bool:?}, usart1rst: {=bool:?}, tim14rst: {=bool:?}, tim15rst: {=bool:?}, tim16rst: {=bool:?}, tim17rst: {=bool:?}, adcrst: {=bool:?} }}" , self . syscfgrst () , self . tim1rst () , self . spi1rst () , self . usart1rst () , self . tim14rst () , self . tim15rst () , self . tim16rst () , self . tim17rst () , self . adcrst ())
}
}
#[doc = "APB peripheral clock enable in Sleep mode register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbsmenr1(pub u32);
impl Apbsmenr1 {
#[doc = "TIM2 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim2smen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIM2 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM3 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim3smen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "TIM3 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim3smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "TIM4 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim4smen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "TIM4 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim4smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "TIM6 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim6smen(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "TIM6 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim6smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "TIM7 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim7smen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "TIM7 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim7smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "LPUART2 clock enable"]
#[inline(always)]
pub const fn lpuart2smen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "LPUART2 clock enable"]
#[inline(always)]
pub fn set_lpuart2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "USART5 clock enable"]
#[inline(always)]
pub const fn usart5smen(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "USART5 clock enable"]
#[inline(always)]
pub fn set_usart5smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "USART6 clock enable"]
#[inline(always)]
pub const fn usart6smen(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "USART6 clock enable"]
#[inline(always)]
pub fn set_usart6smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "RTC APB clock enable during Sleep mode"]
#[inline(always)]
pub const fn rtcapbsmen(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "RTC APB clock enable during Sleep mode"]
#[inline(always)]
pub fn set_rtcapbsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "WWDG clock enable during Sleep mode"]
#[inline(always)]
pub const fn wwdgsmen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "WWDG clock enable during Sleep mode"]
#[inline(always)]
pub fn set_wwdgsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "FDCAN clock enable during Sleep mode"]
#[inline(always)]
pub const fn fdcansmen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "FDCAN clock enable during Sleep mode"]
#[inline(always)]
pub fn set_fdcansmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USB clock enable during Sleep mode"]
#[inline(always)]
pub const fn usbsmen(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[doc = "USB clock enable during Sleep mode"]
#[inline(always)]
pub fn set_usbsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
#[doc = "SPI2 clock enable during Sleep mode"]
#[inline(always)]
pub const fn spi2smen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "SPI2 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_spi2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "SPI3 clock enable during Sleep mode"]
#[inline(always)]
pub const fn spi3smen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "SPI3 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_spi3smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "CRSS clock enable during Sleep mode"]
#[inline(always)]
pub const fn crsssmen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "CRSS clock enable during Sleep mode"]
#[inline(always)]
pub fn set_crsssmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "USART2 clock enable during Sleep mode"]
#[inline(always)]
pub const fn usart2smen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "USART2 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_usart2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USART3 clock enable during Sleep mode"]
#[inline(always)]
pub const fn usart3smen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USART3 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_usart3smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "USART4 clock enable during Sleep mode"]
#[inline(always)]
pub const fn usart4smen(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "USART4 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_usart4smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "LPUART1 clock enable during Sleep mode"]
#[inline(always)]
pub const fn lpuart1smen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "LPUART1 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_lpuart1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "I2C1 clock enable during Sleep mode"]
#[inline(always)]
pub const fn i2c1smen(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C1 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_i2c1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "I2C2 clock enable during Sleep mode"]
#[inline(always)]
pub const fn i2c2smen(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "I2C2 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_i2c2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "I2C3 clock enable during Sleep mode"]
#[inline(always)]
pub const fn i2c3smen(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "I2C3 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_i2c3smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "HDMI CEC clock enable during Sleep mode"]
#[inline(always)]
pub const fn cecsmen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "HDMI CEC clock enable during Sleep mode"]
#[inline(always)]
pub fn set_cecsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "UCPD1 clock enable during Sleep mode"]
#[inline(always)]
pub const fn ucpd1smen(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "UCPD1 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_ucpd1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "UCPD2 clock enable during Sleep mode"]
#[inline(always)]
pub const fn ucpd2smen(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "UCPD2 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_ucpd2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "Debug support clock enable during Sleep mode"]
#[inline(always)]
pub const fn dbgsmen(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "Debug support clock enable during Sleep mode"]
#[inline(always)]
pub fn set_dbgsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Power interface clock enable during Sleep mode"]
#[inline(always)]
pub const fn pwrsmen(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Power interface clock enable during Sleep mode"]
#[inline(always)]
pub fn set_pwrsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "DAC1 interface clock enable during Sleep mode"]
#[inline(always)]
pub const fn dac1smen(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "DAC1 interface clock enable during Sleep mode"]
#[inline(always)]
pub fn set_dac1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Low Power Timer 2 clock enable during Sleep mode"]
#[inline(always)]
pub const fn lptim2smen(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Low Power Timer 2 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_lptim2smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "Low Power Timer 1 clock enable during Sleep mode"]
#[inline(always)]
pub const fn lptim1smen(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Low Power Timer 1 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_lptim1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apbsmenr1 {
#[inline(always)]
fn default() -> Apbsmenr1 {
Apbsmenr1(0)
}
}
impl core::fmt::Debug for Apbsmenr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbsmenr1")
.field("tim2smen", &self.tim2smen())
.field("tim3smen", &self.tim3smen())
.field("tim4smen", &self.tim4smen())
.field("tim6smen", &self.tim6smen())
.field("tim7smen", &self.tim7smen())
.field("lpuart2smen", &self.lpuart2smen())
.field("usart5smen", &self.usart5smen())
.field("usart6smen", &self.usart6smen())
.field("rtcapbsmen", &self.rtcapbsmen())
.field("wwdgsmen", &self.wwdgsmen())
.field("fdcansmen", &self.fdcansmen())
.field("usbsmen", &self.usbsmen())
.field("spi2smen", &self.spi2smen())
.field("spi3smen", &self.spi3smen())
.field("crsssmen", &self.crsssmen())
.field("usart2smen", &self.usart2smen())
.field("usart3smen", &self.usart3smen())
.field("usart4smen", &self.usart4smen())
.field("lpuart1smen", &self.lpuart1smen())
.field("i2c1smen", &self.i2c1smen())
.field("i2c2smen", &self.i2c2smen())
.field("i2c3smen", &self.i2c3smen())
.field("cecsmen", &self.cecsmen())
.field("ucpd1smen", &self.ucpd1smen())
.field("ucpd2smen", &self.ucpd2smen())
.field("dbgsmen", &self.dbgsmen())
.field("pwrsmen", &self.pwrsmen())
.field("dac1smen", &self.dac1smen())
.field("lptim2smen", &self.lptim2smen())
.field("lptim1smen", &self.lptim1smen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbsmenr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbsmenr1 {{ tim2smen: {=bool:?}, tim3smen: {=bool:?}, tim4smen: {=bool:?}, tim6smen: {=bool:?}, tim7smen: {=bool:?}, lpuart2smen: {=bool:?}, usart5smen: {=bool:?}, usart6smen: {=bool:?}, rtcapbsmen: {=bool:?}, wwdgsmen: {=bool:?}, fdcansmen: {=bool:?}, usbsmen: {=bool:?}, spi2smen: {=bool:?}, spi3smen: {=bool:?}, crsssmen: {=bool:?}, usart2smen: {=bool:?}, usart3smen: {=bool:?}, usart4smen: {=bool:?}, lpuart1smen: {=bool:?}, i2c1smen: {=bool:?}, i2c2smen: {=bool:?}, i2c3smen: {=bool:?}, cecsmen: {=bool:?}, ucpd1smen: {=bool:?}, ucpd2smen: {=bool:?}, dbgsmen: {=bool:?}, pwrsmen: {=bool:?}, dac1smen: {=bool:?}, lptim2smen: {=bool:?}, lptim1smen: {=bool:?} }}" , self . tim2smen () , self . tim3smen () , self . tim4smen () , self . tim6smen () , self . tim7smen () , self . lpuart2smen () , self . usart5smen () , self . usart6smen () , self . rtcapbsmen () , self . wwdgsmen () , self . fdcansmen () , self . usbsmen () , self . spi2smen () , self . spi3smen () , self . crsssmen () , self . usart2smen () , self . usart3smen () , self . usart4smen () , self . lpuart1smen () , self . i2c1smen () , self . i2c2smen () , self . i2c3smen () , self . cecsmen () , self . ucpd1smen () , self . ucpd2smen () , self . dbgsmen () , self . pwrsmen () , self . dac1smen () , self . lptim2smen () , self . lptim1smen ())
}
}
#[doc = "APB peripheral clock enable in Sleep mode register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apbsmenr2(pub u32);
impl Apbsmenr2 {
#[doc = "SYSCFG, COMP and VREFBUF clock enable during Sleep mode"]
#[inline(always)]
pub const fn syscfgsmen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "SYSCFG, COMP and VREFBUF clock enable during Sleep mode"]
#[inline(always)]
pub fn set_syscfgsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM1 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim1smen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "TIM1 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "SPI1 clock enable during Sleep mode"]
#[inline(always)]
pub const fn spi1smen(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI1 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_spi1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "USART1 clock enable during Sleep mode"]
#[inline(always)]
pub const fn usart1smen(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "USART1 clock enable during Sleep mode"]
#[inline(always)]
pub fn set_usart1smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "TIM14 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim14smen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "TIM14 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim14smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "TIM15 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim15smen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "TIM15 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim15smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "TIM16 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim16smen(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim16smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "TIM16 timer clock enable during Sleep mode"]
#[inline(always)]
pub const fn tim17smen(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "TIM16 timer clock enable during Sleep mode"]
#[inline(always)]
pub fn set_tim17smen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "ADC clock enable during Sleep mode"]
#[inline(always)]
pub const fn adcsmen(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "ADC clock enable during Sleep mode"]
#[inline(always)]
pub fn set_adcsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Apbsmenr2 {
#[inline(always)]
fn default() -> Apbsmenr2 {
Apbsmenr2(0)
}
}
impl core::fmt::Debug for Apbsmenr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apbsmenr2")
.field("syscfgsmen", &self.syscfgsmen())
.field("tim1smen", &self.tim1smen())
.field("spi1smen", &self.spi1smen())
.field("usart1smen", &self.usart1smen())
.field("tim14smen", &self.tim14smen())
.field("tim15smen", &self.tim15smen())
.field("tim16smen", &self.tim16smen())
.field("tim17smen", &self.tim17smen())
.field("adcsmen", &self.adcsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apbsmenr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apbsmenr2 {{ syscfgsmen: {=bool:?}, tim1smen: {=bool:?}, spi1smen: {=bool:?}, usart1smen: {=bool:?}, tim14smen: {=bool:?}, tim15smen: {=bool:?}, tim16smen: {=bool:?}, tim17smen: {=bool:?}, adcsmen: {=bool:?} }}" , self . syscfgsmen () , self . tim1smen () , self . spi1smen () , self . usart1smen () , self . tim14smen () , self . tim15smen () , self . tim16smen () , self . tim17smen () , self . adcsmen ())
}
}
#[doc = "RTC domain control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Bdcr(pub u32);
impl Bdcr {
#[doc = "LSE oscillator enable"]
#[inline(always)]
pub const fn lseon(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator enable"]
#[inline(always)]
pub fn set_lseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE oscillator ready"]
#[inline(always)]
pub const fn lserdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator ready"]
#[inline(always)]
pub fn set_lserdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "LSE oscillator bypass"]
#[inline(always)]
pub const fn lsebyp(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator bypass"]
#[inline(always)]
pub fn set_lsebyp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "LSE oscillator drive capability"]
#[inline(always)]
pub const fn lsedrv(&self) -> super::vals::Lsedrv {
let val = (self.0 >> 3usize) & 0x03;
super::vals::Lsedrv::from_bits(val as u8)
}
#[doc = "LSE oscillator drive capability"]
#[inline(always)]
pub fn set_lsedrv(&mut self, val: super::vals::Lsedrv) {
self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
}
#[doc = "CSS on LSE enable"]
#[inline(always)]
pub const fn lsecsson(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "CSS on LSE enable"]
#[inline(always)]
pub fn set_lsecsson(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "CSS on LSE failure Detection"]
#[inline(always)]
pub const fn lsecssd(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "CSS on LSE failure Detection"]
#[inline(always)]
pub fn set_lsecssd(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "RTC clock source selection"]
#[inline(always)]
pub const fn rtcsel(&self) -> super::vals::Rtcsel {
let val = (self.0 >> 8usize) & 0x03;
super::vals::Rtcsel::from_bits(val as u8)
}
#[doc = "RTC clock source selection"]
#[inline(always)]
pub fn set_rtcsel(&mut self, val: super::vals::Rtcsel) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
}
#[doc = "RTC clock enable"]
#[inline(always)]
pub const fn rtcen(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "RTC clock enable"]
#[inline(always)]
pub fn set_rtcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "RTC domain software reset"]
#[inline(always)]
pub const fn bdrst(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "RTC domain software reset"]
#[inline(always)]
pub fn set_bdrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Low-speed clock output (LSCO) enable"]
#[inline(always)]
pub const fn lscoen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Low-speed clock output (LSCO) enable"]
#[inline(always)]
pub fn set_lscoen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Low-speed clock output selection"]
#[inline(always)]
pub const fn lscosel(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Low-speed clock output selection"]
#[inline(always)]
pub fn set_lscosel(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for Bdcr {
#[inline(always)]
fn default() -> Bdcr {
Bdcr(0)
}
}
impl core::fmt::Debug for Bdcr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Bdcr")
.field("lseon", &self.lseon())
.field("lserdy", &self.lserdy())
.field("lsebyp", &self.lsebyp())
.field("lsedrv", &self.lsedrv())
.field("lsecsson", &self.lsecsson())
.field("lsecssd", &self.lsecssd())
.field("rtcsel", &self.rtcsel())
.field("rtcen", &self.rtcen())
.field("bdrst", &self.bdrst())
.field("lscoen", &self.lscoen())
.field("lscosel", &self.lscosel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Bdcr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Bdcr {{ lseon: {=bool:?}, lserdy: {=bool:?}, lsebyp: {=bool:?}, lsedrv: {:?}, lsecsson: {=bool:?}, lsecssd: {=bool:?}, rtcsel: {:?}, rtcen: {=bool:?}, bdrst: {=bool:?}, lscoen: {=bool:?}, lscosel: {=bool:?} }}" , self . lseon () , self . lserdy () , self . lsebyp () , self . lsedrv () , self . lsecsson () , self . lsecssd () , self . rtcsel () , self . rtcen () , self . bdrst () , self . lscoen () , self . lscosel ())
}
}
#[doc = "Peripherals independent clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ccipr(pub u32);
impl Ccipr {
#[doc = "USART1 clock source selection"]
#[inline(always)]
pub const fn usart1sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 0usize) & 0x03;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "USART1 clock source selection"]
#[inline(always)]
pub fn set_usart1sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "USART2 clock source selection"]
#[inline(always)]
pub const fn usart2sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 2usize) & 0x03;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "USART2 clock source selection"]
#[inline(always)]
pub fn set_usart2sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
}
#[doc = "USART3 clock source selection"]
#[inline(always)]
pub const fn usart3sel(&self) -> super::vals::Usartsel {
let val = (self.0 >> 4usize) & 0x03;
super::vals::Usartsel::from_bits(val as u8)
}
#[doc = "USART3 clock source selection"]
#[inline(always)]
pub fn set_usart3sel(&mut self, val: super::vals::Usartsel) {
self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
}
#[doc = "HDMI CEC clock source selection"]
#[inline(always)]
pub const fn cecsel(&self) -> super::vals::Cecsel {
let val = (self.0 >> 6usize) & 0x01;
super::vals::Cecsel::from_bits(val as u8)
}
#[doc = "HDMI CEC clock source selection"]
#[inline(always)]
pub fn set_cecsel(&mut self, val: super::vals::Cecsel) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
}
#[doc = "LPUART2 clock source selection"]
#[inline(always)]
pub const fn lpuart2sel(&self) -> super::vals::Lpuart2sel {
let val = (self.0 >> 8usize) & 0x03;
super::vals::Lpuart2sel::from_bits(val as u8)
}
#[doc = "LPUART2 clock source selection"]
#[inline(always)]
pub fn set_lpuart2sel(&mut self, val: super::vals::Lpuart2sel) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
}
#[doc = "LPUART1 clock source selection"]
#[inline(always)]
pub const fn lpuart1sel(&self) -> super::vals::Lpuart1sel {
let val = (self.0 >> 10usize) & 0x03;
super::vals::Lpuart1sel::from_bits(val as u8)
}
#[doc = "LPUART1 clock source selection"]
#[inline(always)]
pub fn set_lpuart1sel(&mut self, val: super::vals::Lpuart1sel) {
self.0 = (self.0 & !(0x03 << 10usize)) | (((val.to_bits() as u32) & 0x03) << 10usize);
}
#[doc = "I2C1 clock source selection"]
#[inline(always)]
pub const fn i2c1sel(&self) -> super::vals::I2c1sel {
let val = (self.0 >> 12usize) & 0x03;
super::vals::I2c1sel::from_bits(val as u8)
}
#[doc = "I2C1 clock source selection"]
#[inline(always)]
pub fn set_i2c1sel(&mut self, val: super::vals::I2c1sel) {
self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
}
#[doc = "I2C2 or I2S1 clock source selection"]
#[inline(always)]
pub const fn i2c2i2s1sel(&self) -> super::vals::I2c2i2s1sel {
let val = (self.0 >> 14usize) & 0x03;
super::vals::I2c2i2s1sel::from_bits(val as u8)
}
#[doc = "I2C2 or I2S1 clock source selection"]
#[inline(always)]
pub fn set_i2c2i2s1sel(&mut self, val: super::vals::I2c2i2s1sel) {
self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize);
}
#[doc = "LPTIM1 clock source selection"]
#[inline(always)]
pub const fn lptim1sel(&self) -> super::vals::Lptim1sel {
let val = (self.0 >> 18usize) & 0x03;
super::vals::Lptim1sel::from_bits(val as u8)
}
#[doc = "LPTIM1 clock source selection"]
#[inline(always)]
pub fn set_lptim1sel(&mut self, val: super::vals::Lptim1sel) {
self.0 = (self.0 & !(0x03 << 18usize)) | (((val.to_bits() as u32) & 0x03) << 18usize);
}
#[doc = "LPTIM2 clock source selection"]
#[inline(always)]
pub const fn lptim2sel(&self) -> super::vals::Lptim2sel {
let val = (self.0 >> 20usize) & 0x03;
super::vals::Lptim2sel::from_bits(val as u8)
}
#[doc = "LPTIM2 clock source selection"]
#[inline(always)]
pub fn set_lptim2sel(&mut self, val: super::vals::Lptim2sel) {
self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize);
}
#[doc = "TIM1 clock source selection"]
#[inline(always)]
pub const fn tim1sel(&self) -> super::vals::Tim1sel {
let val = (self.0 >> 22usize) & 0x01;
super::vals::Tim1sel::from_bits(val as u8)
}
#[doc = "TIM1 clock source selection"]
#[inline(always)]
pub fn set_tim1sel(&mut self, val: super::vals::Tim1sel) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val.to_bits() as u32) & 0x01) << 22usize);
}
#[doc = "TIM15 clock source selection"]
#[inline(always)]
pub const fn tim15sel(&self) -> super::vals::Tim15sel {
let val = (self.0 >> 24usize) & 0x01;
super::vals::Tim15sel::from_bits(val as u8)
}
#[doc = "TIM15 clock source selection"]
#[inline(always)]
pub fn set_tim15sel(&mut self, val: super::vals::Tim15sel) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize);
}
#[doc = "RNG clock source selection"]
#[inline(always)]
pub const fn rngsel(&self) -> super::vals::Rngsel {
let val = (self.0 >> 26usize) & 0x03;
super::vals::Rngsel::from_bits(val as u8)
}
#[doc = "RNG clock source selection"]
#[inline(always)]
pub fn set_rngsel(&mut self, val: super::vals::Rngsel) {
self.0 = (self.0 & !(0x03 << 26usize)) | (((val.to_bits() as u32) & 0x03) << 26usize);
}
#[doc = "Division factor of RNG clock divider"]
#[inline(always)]
pub const fn rngdiv(&self) -> super::vals::Rngdiv {
let val = (self.0 >> 28usize) & 0x03;
super::vals::Rngdiv::from_bits(val as u8)
}
#[doc = "Division factor of RNG clock divider"]
#[inline(always)]
pub fn set_rngdiv(&mut self, val: super::vals::Rngdiv) {
self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize);
}
#[doc = "ADCs clock source selection"]
#[inline(always)]
pub const fn adcsel(&self) -> super::vals::Adcsel {
let val = (self.0 >> 30usize) & 0x03;
super::vals::Adcsel::from_bits(val as u8)
}
#[doc = "ADCs clock source selection"]
#[inline(always)]
pub fn set_adcsel(&mut self, val: super::vals::Adcsel) {
self.0 = (self.0 & !(0x03 << 30usize)) | (((val.to_bits() as u32) & 0x03) << 30usize);
}
}
impl Default for Ccipr {
#[inline(always)]
fn default() -> Ccipr {
Ccipr(0)
}
}
impl core::fmt::Debug for Ccipr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ccipr")
.field("usart1sel", &self.usart1sel())
.field("usart2sel", &self.usart2sel())
.field("usart3sel", &self.usart3sel())
.field("cecsel", &self.cecsel())
.field("lpuart2sel", &self.lpuart2sel())
.field("lpuart1sel", &self.lpuart1sel())
.field("i2c1sel", &self.i2c1sel())
.field("i2c2i2s1sel", &self.i2c2i2s1sel())
.field("lptim1sel", &self.lptim1sel())
.field("lptim2sel", &self.lptim2sel())
.field("tim1sel", &self.tim1sel())
.field("tim15sel", &self.tim15sel())
.field("rngsel", &self.rngsel())
.field("rngdiv", &self.rngdiv())
.field("adcsel", &self.adcsel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ccipr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ccipr {{ usart1sel: {:?}, usart2sel: {:?}, usart3sel: {:?}, cecsel: {:?}, lpuart2sel: {:?}, lpuart1sel: {:?}, i2c1sel: {:?}, i2c2i2s1sel: {:?}, lptim1sel: {:?}, lptim2sel: {:?}, tim1sel: {:?}, tim15sel: {:?}, rngsel: {:?}, rngdiv: {:?}, adcsel: {:?} }}" , self . usart1sel () , self . usart2sel () , self . usart3sel () , self . cecsel () , self . lpuart2sel () , self . lpuart1sel () , self . i2c1sel () , self . i2c2i2s1sel () , self . lptim1sel () , self . lptim2sel () , self . tim1sel () , self . tim15sel () , self . rngsel () , self . rngdiv () , self . adcsel ())
}
}
#[doc = "Peripherals independent clock configuration register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ccipr2(pub u32);
impl Ccipr2 {
#[doc = "I2S1SEL"]
#[inline(always)]
pub const fn i2s1sel(&self) -> super::vals::I2s1sel {
let val = (self.0 >> 0usize) & 0x03;
super::vals::I2s1sel::from_bits(val as u8)
}
#[doc = "I2S1SEL"]
#[inline(always)]
pub fn set_i2s1sel(&mut self, val: super::vals::I2s1sel) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "I2S2SEL"]
#[inline(always)]
pub const fn i2s2sel(&self) -> super::vals::I2s2sel {
let val = (self.0 >> 2usize) & 0x03;
super::vals::I2s2sel::from_bits(val as u8)
}
#[doc = "I2S2SEL"]
#[inline(always)]
pub fn set_i2s2sel(&mut self, val: super::vals::I2s2sel) {
self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
}
#[doc = "FDCANSEL"]
#[inline(always)]
pub const fn fdcansel(&self) -> super::vals::Fdcansel {
let val = (self.0 >> 8usize) & 0x03;
super::vals::Fdcansel::from_bits(val as u8)
}
#[doc = "FDCANSEL"]
#[inline(always)]
pub fn set_fdcansel(&mut self, val: super::vals::Fdcansel) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
}
#[doc = "USBSEL"]
#[inline(always)]
pub const fn usbsel(&self) -> super::vals::Usbsel {
let val = (self.0 >> 12usize) & 0x03;
super::vals::Usbsel::from_bits(val as u8)
}
#[doc = "USBSEL"]
#[inline(always)]
pub fn set_usbsel(&mut self, val: super::vals::Usbsel) {
self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
}
}
impl Default for Ccipr2 {
#[inline(always)]
fn default() -> Ccipr2 {
Ccipr2(0)
}
}
impl core::fmt::Debug for Ccipr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ccipr2")
.field("i2s1sel", &self.i2s1sel())
.field("i2s2sel", &self.i2s2sel())
.field("fdcansel", &self.fdcansel())
.field("usbsel", &self.usbsel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ccipr2 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ccipr2 {{ i2s1sel: {:?}, i2s2sel: {:?}, fdcansel: {:?}, usbsel: {:?} }}",
self.i2s1sel(),
self.i2s2sel(),
self.fdcansel(),
self.usbsel()
)
}
}
#[doc = "Clock configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfgr(pub u32);
impl Cfgr {
#[doc = "System clock switch"]
#[inline(always)]
pub const fn sw(&self) -> super::vals::Sw {
let val = (self.0 >> 0usize) & 0x07;
super::vals::Sw::from_bits(val as u8)
}
#[doc = "System clock switch"]
#[inline(always)]
pub fn set_sw(&mut self, val: super::vals::Sw) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
}
#[doc = "System clock switch status"]
#[inline(always)]
pub const fn sws(&self) -> super::vals::Sw {
let val = (self.0 >> 3usize) & 0x07;
super::vals::Sw::from_bits(val as u8)
}
#[doc = "System clock switch status"]
#[inline(always)]
pub fn set_sws(&mut self, val: super::vals::Sw) {
self.0 = (self.0 & !(0x07 << 3usize)) | (((val.to_bits() as u32) & 0x07) << 3usize);
}
#[doc = "AHB prescaler"]
#[inline(always)]
pub const fn hpre(&self) -> super::vals::Hpre {
let val = (self.0 >> 8usize) & 0x0f;
super::vals::Hpre::from_bits(val as u8)
}
#[doc = "AHB prescaler"]
#[inline(always)]
pub fn set_hpre(&mut self, val: super::vals::Hpre) {
self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize);
}
#[doc = "APB prescaler"]
#[inline(always)]
pub const fn ppre(&self) -> super::vals::Ppre {
let val = (self.0 >> 12usize) & 0x07;
super::vals::Ppre::from_bits(val as u8)
}
#[doc = "APB prescaler"]
#[inline(always)]
pub fn set_ppre(&mut self, val: super::vals::Ppre) {
self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize);
}
#[doc = "MCO2SEL"]
#[inline(always)]
pub const fn mco2sel(&self) -> super::vals::Mcosel {
let val = (self.0 >> 16usize) & 0x0f;
super::vals::Mcosel::from_bits(val as u8)
}
#[doc = "MCO2SEL"]
#[inline(always)]
pub fn set_mco2sel(&mut self, val: super::vals::Mcosel) {
self.0 = (self.0 & !(0x0f << 16usize)) | (((val.to_bits() as u32) & 0x0f) << 16usize);
}
#[doc = "MCO2PRE"]
#[inline(always)]
pub const fn mco2pre(&self) -> super::vals::Mcopre {
let val = (self.0 >> 20usize) & 0x0f;
super::vals::Mcopre::from_bits(val as u8)
}
#[doc = "MCO2PRE"]
#[inline(always)]
pub fn set_mco2pre(&mut self, val: super::vals::Mcopre) {
self.0 = (self.0 & !(0x0f << 20usize)) | (((val.to_bits() as u32) & 0x0f) << 20usize);
}
#[doc = "Microcontroller clock output"]
#[inline(always)]
pub const fn mco1sel(&self) -> super::vals::Mcosel {
let val = (self.0 >> 24usize) & 0x0f;
super::vals::Mcosel::from_bits(val as u8)
}
#[doc = "Microcontroller clock output"]
#[inline(always)]
pub fn set_mco1sel(&mut self, val: super::vals::Mcosel) {
self.0 = (self.0 & !(0x0f << 24usize)) | (((val.to_bits() as u32) & 0x0f) << 24usize);
}
#[doc = "Microcontroller clock output prescaler"]
#[inline(always)]
pub const fn mco1pre(&self) -> super::vals::Mcopre {
let val = (self.0 >> 28usize) & 0x0f;
super::vals::Mcopre::from_bits(val as u8)
}
#[doc = "Microcontroller clock output prescaler"]
#[inline(always)]
pub fn set_mco1pre(&mut self, val: super::vals::Mcopre) {
self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
}
}
impl Default for Cfgr {
#[inline(always)]
fn default() -> Cfgr {
Cfgr(0)
}
}
impl core::fmt::Debug for Cfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cfgr")
.field("sw", &self.sw())
.field("sws", &self.sws())
.field("hpre", &self.hpre())
.field("ppre", &self.ppre())
.field("mco2sel", &self.mco2sel())
.field("mco2pre", &self.mco2pre())
.field("mco1sel", &self.mco1sel())
.field("mco1pre", &self.mco1pre())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cfgr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cfgr {{ sw: {:?}, sws: {:?}, hpre: {:?}, ppre: {:?}, mco2sel: {:?}, mco2pre: {:?}, mco1sel: {:?}, mco1pre: {:?} }}" , self . sw () , self . sws () , self . hpre () , self . ppre () , self . mco2sel () , self . mco2pre () , self . mco1sel () , self . mco1pre ())
}
}
#[doc = "Clock interrupt clear register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cicr(pub u32);
impl Cicr {
#[doc = "LSI ready interrupt clear"]
#[inline(always)]
pub const fn lsirdyc(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt clear"]
#[inline(always)]
pub fn set_lsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt clear"]
#[inline(always)]
pub const fn lserdyc(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt clear"]
#[inline(always)]
pub fn set_lserdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "HSI ready interrupt clear"]
#[inline(always)]
pub const fn hsirdyc(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt clear"]
#[inline(always)]
pub fn set_hsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt clear"]
#[inline(always)]
pub const fn hserdyc(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt clear"]
#[inline(always)]
pub fn set_hserdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "PLL ready interrupt clear"]
#[inline(always)]
pub const fn pllsysrdyc(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "PLL ready interrupt clear"]
#[inline(always)]
pub fn set_pllsysrdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Clock security system interrupt clear"]
#[inline(always)]
pub const fn cssc(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Clock security system interrupt clear"]
#[inline(always)]
pub fn set_cssc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "LSE Clock security system interrupt clear"]
#[inline(always)]
pub const fn lsecssc(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LSE Clock security system interrupt clear"]
#[inline(always)]
pub fn set_lsecssc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
}
impl Default for Cicr {
#[inline(always)]
fn default() -> Cicr {
Cicr(0)
}
}
impl core::fmt::Debug for Cicr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cicr")
.field("lsirdyc", &self.lsirdyc())
.field("lserdyc", &self.lserdyc())
.field("hsirdyc", &self.hsirdyc())
.field("hserdyc", &self.hserdyc())
.field("pllsysrdyc", &self.pllsysrdyc())
.field("cssc", &self.cssc())
.field("lsecssc", &self.lsecssc())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cicr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cicr {{ lsirdyc: {=bool:?}, lserdyc: {=bool:?}, hsirdyc: {=bool:?}, hserdyc: {=bool:?}, pllsysrdyc: {=bool:?}, cssc: {=bool:?}, lsecssc: {=bool:?} }}" , self . lsirdyc () , self . lserdyc () , self . hsirdyc () , self . hserdyc () , self . pllsysrdyc () , self . cssc () , self . lsecssc ())
}
}
#[doc = "Clock interrupt enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cier(pub u32);
impl Cier {
#[doc = "LSI ready interrupt enable"]
#[inline(always)]
pub const fn lsirdyie(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt enable"]
#[inline(always)]
pub fn set_lsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt enable"]
#[inline(always)]
pub const fn lserdyie(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt enable"]
#[inline(always)]
pub fn set_lserdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "HSI ready interrupt enable"]
#[inline(always)]
pub const fn hsirdyie(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt enable"]
#[inline(always)]
pub fn set_hsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt enable"]
#[inline(always)]
pub const fn hserdyie(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt enable"]
#[inline(always)]
pub fn set_hserdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "PLL ready interrupt enable"]
#[inline(always)]
pub const fn pllsysrdyie(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "PLL ready interrupt enable"]
#[inline(always)]
pub fn set_pllsysrdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
}
impl Default for Cier {
#[inline(always)]
fn default() -> Cier {
Cier(0)
}
}
impl core::fmt::Debug for Cier {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cier")
.field("lsirdyie", &self.lsirdyie())
.field("lserdyie", &self.lserdyie())
.field("hsirdyie", &self.hsirdyie())
.field("hserdyie", &self.hserdyie())
.field("pllsysrdyie", &self.pllsysrdyie())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cier {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cier {{ lsirdyie: {=bool:?}, lserdyie: {=bool:?}, hsirdyie: {=bool:?}, hserdyie: {=bool:?}, pllsysrdyie: {=bool:?} }}" , self . lsirdyie () , self . lserdyie () , self . hsirdyie () , self . hserdyie () , self . pllsysrdyie ())
}
}
#[doc = "Clock interrupt flag register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cifr(pub u32);
impl Cifr {
#[doc = "LSI ready interrupt flag"]
#[inline(always)]
pub const fn lsirdyf(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt flag"]
#[inline(always)]
pub fn set_lsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt flag"]
#[inline(always)]
pub const fn lserdyf(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt flag"]
#[inline(always)]
pub fn set_lserdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "HSI ready interrupt flag"]
#[inline(always)]
pub const fn hsirdyf(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt flag"]
#[inline(always)]
pub fn set_hsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "HSE ready interrupt flag"]
#[inline(always)]
pub const fn hserdyf(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "HSE ready interrupt flag"]
#[inline(always)]
pub fn set_hserdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "PLL ready interrupt flag"]
#[inline(always)]
pub const fn pllsysrdyf(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "PLL ready interrupt flag"]
#[inline(always)]
pub fn set_pllsysrdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Clock security system interrupt flag"]
#[inline(always)]
pub const fn cssf(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Clock security system interrupt flag"]
#[inline(always)]
pub fn set_cssf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "LSE Clock security system interrupt flag"]
#[inline(always)]
pub const fn lsecssf(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LSE Clock security system interrupt flag"]
#[inline(always)]
pub fn set_lsecssf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
}
impl Default for Cifr {
#[inline(always)]
fn default() -> Cifr {
Cifr(0)
}
}
impl core::fmt::Debug for Cifr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cifr")
.field("lsirdyf", &self.lsirdyf())
.field("lserdyf", &self.lserdyf())
.field("hsirdyf", &self.hsirdyf())
.field("hserdyf", &self.hserdyf())
.field("pllsysrdyf", &self.pllsysrdyf())
.field("cssf", &self.cssf())
.field("lsecssf", &self.lsecssf())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cifr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cifr {{ lsirdyf: {=bool:?}, lserdyf: {=bool:?}, hsirdyf: {=bool:?}, hserdyf: {=bool:?}, pllsysrdyf: {=bool:?}, cssf: {=bool:?}, lsecssf: {=bool:?} }}" , self . lsirdyf () , self . lserdyf () , self . hsirdyf () , self . hserdyf () , self . pllsysrdyf () , self . cssf () , self . lsecssf ())
}
}
#[doc = "Clock control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr(pub u32);
impl Cr {
#[doc = "HSI clock enable"]
#[inline(always)]
pub const fn hsion(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "HSI clock enable"]
#[inline(always)]
pub fn set_hsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "HSI always enable for peripheral kernels"]
#[inline(always)]
pub const fn hsikeron(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "HSI always enable for peripheral kernels"]
#[inline(always)]
pub fn set_hsikeron(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "HSI clock ready flag"]
#[inline(always)]
pub const fn hsirdy(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "HSI clock ready flag"]
#[inline(always)]
pub fn set_hsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "HSI clock division factor"]
#[inline(always)]
pub const fn hsidiv(&self) -> super::vals::Hsidiv {
let val = (self.0 >> 11usize) & 0x07;
super::vals::Hsidiv::from_bits(val as u8)
}
#[doc = "HSI clock division factor"]
#[inline(always)]
pub fn set_hsidiv(&mut self, val: super::vals::Hsidiv) {
self.0 = (self.0 & !(0x07 << 11usize)) | (((val.to_bits() as u32) & 0x07) << 11usize);
}
#[doc = "HSE clock enable"]
#[inline(always)]
pub const fn hseon(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "HSE clock enable"]
#[inline(always)]
pub fn set_hseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "HSE clock ready flag"]
#[inline(always)]
pub const fn hserdy(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "HSE clock ready flag"]
#[inline(always)]
pub fn set_hserdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "HSE crystal oscillator bypass"]
#[inline(always)]
pub const fn hsebyp(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "HSE crystal oscillator bypass"]
#[inline(always)]
pub fn set_hsebyp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "Clock security system enable"]
#[inline(always)]
pub const fn csson(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "Clock security system enable"]
#[inline(always)]
pub fn set_csson(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "PLL enable"]
#[inline(always)]
pub const fn pllon(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "PLL enable"]
#[inline(always)]
pub fn set_pllon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "PLL clock ready flag"]
#[inline(always)]
pub const fn pllrdy(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "PLL clock ready flag"]
#[inline(always)]
pub fn set_pllrdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for Cr {
#[inline(always)]
fn default() -> Cr {
Cr(0)
}
}
impl core::fmt::Debug for Cr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cr")
.field("hsion", &self.hsion())
.field("hsikeron", &self.hsikeron())
.field("hsirdy", &self.hsirdy())
.field("hsidiv", &self.hsidiv())
.field("hseon", &self.hseon())
.field("hserdy", &self.hserdy())
.field("hsebyp", &self.hsebyp())
.field("csson", &self.csson())
.field("pllon", &self.pllon())
.field("pllrdy", &self.pllrdy())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cr {{ hsion: {=bool:?}, hsikeron: {=bool:?}, hsirdy: {=bool:?}, hsidiv: {:?}, hseon: {=bool:?}, hserdy: {=bool:?}, hsebyp: {=bool:?}, csson: {=bool:?}, pllon: {=bool:?}, pllrdy: {=bool:?} }}" , self . hsion () , self . hsikeron () , self . hsirdy () , self . hsidiv () , self . hseon () , self . hserdy () , self . hsebyp () , self . csson () , self . pllon () , self . pllrdy ())
}
}
#[doc = "Control/status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csr(pub u32);
impl Csr {
#[doc = "LSI oscillator enable"]
#[inline(always)]
pub const fn lsion(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI oscillator enable"]
#[inline(always)]
pub fn set_lsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSI oscillator ready"]
#[inline(always)]
pub const fn lsirdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSI oscillator ready"]
#[inline(always)]
pub fn set_lsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Remove reset flags"]
#[inline(always)]
pub const fn rmvf(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Remove reset flags"]
#[inline(always)]
pub fn set_rmvf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "Option byte loader reset flag"]
#[inline(always)]
pub const fn oblrstf(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Option byte loader reset flag"]
#[inline(always)]
pub fn set_oblrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "Pin reset flag"]
#[inline(always)]
pub const fn pinrstf(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "Pin reset flag"]
#[inline(always)]
pub fn set_pinrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "BOR or POR/PDR flag"]
#[inline(always)]
pub const fn pwrrstf(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "BOR or POR/PDR flag"]
#[inline(always)]
pub fn set_pwrrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Software reset flag"]
#[inline(always)]
pub const fn sftrstf(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Software reset flag"]
#[inline(always)]
pub fn set_sftrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "Independent window watchdog reset flag"]
#[inline(always)]
pub const fn iwdgrstf(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "Independent window watchdog reset flag"]
#[inline(always)]
pub fn set_iwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Window watchdog reset flag"]
#[inline(always)]
pub const fn wwdgrstf(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Window watchdog reset flag"]
#[inline(always)]
pub fn set_wwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "Low-power reset flag"]
#[inline(always)]
pub const fn lpwrrstf(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Low-power reset flag"]
#[inline(always)]
pub fn set_lpwrrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Csr {
#[inline(always)]
fn default() -> Csr {
Csr(0)
}
}
impl core::fmt::Debug for Csr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Csr")
.field("lsion", &self.lsion())
.field("lsirdy", &self.lsirdy())
.field("rmvf", &self.rmvf())
.field("oblrstf", &self.oblrstf())
.field("pinrstf", &self.pinrstf())
.field("pwrrstf", &self.pwrrstf())
.field("sftrstf", &self.sftrstf())
.field("iwdgrstf", &self.iwdgrstf())
.field("wwdgrstf", &self.wwdgrstf())
.field("lpwrrstf", &self.lpwrrstf())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Csr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Csr {{ lsion: {=bool:?}, lsirdy: {=bool:?}, rmvf: {=bool:?}, oblrstf: {=bool:?}, pinrstf: {=bool:?}, pwrrstf: {=bool:?}, sftrstf: {=bool:?}, iwdgrstf: {=bool:?}, wwdgrstf: {=bool:?}, lpwrrstf: {=bool:?} }}" , self . lsion () , self . lsirdy () , self . rmvf () , self . oblrstf () , self . pinrstf () , self . pwrrstf () , self . sftrstf () , self . iwdgrstf () , self . wwdgrstf () , self . lpwrrstf ())
}
}
#[doc = "GPIO clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Gpioenr(pub u32);
impl Gpioenr {
#[doc = "I/O port A clock enable"]
#[inline(always)]
pub const fn gpioaen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "I/O port A clock enable"]
#[inline(always)]
pub fn set_gpioaen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "I/O port B clock enable"]
#[inline(always)]
pub const fn gpioben(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "I/O port B clock enable"]
#[inline(always)]
pub fn set_gpioben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "I/O port C clock enable"]
#[inline(always)]
pub const fn gpiocen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "I/O port C clock enable"]
#[inline(always)]
pub fn set_gpiocen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "I/O port D clock enable"]
#[inline(always)]
pub const fn gpioden(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "I/O port D clock enable"]
#[inline(always)]
pub fn set_gpioden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "I/O port F clock enable"]
#[inline(always)]
pub const fn gpiofen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "I/O port F clock enable"]
#[inline(always)]
pub fn set_gpiofen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
}
impl Default for Gpioenr {
#[inline(always)]
fn default() -> Gpioenr {
Gpioenr(0)
}
}
impl core::fmt::Debug for Gpioenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpioenr")
.field("gpioaen", &self.gpioaen())
.field("gpioben", &self.gpioben())
.field("gpiocen", &self.gpiocen())
.field("gpioden", &self.gpioden())
.field("gpiofen", &self.gpiofen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Gpioenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Gpioenr {{ gpioaen: {=bool:?}, gpioben: {=bool:?}, gpiocen: {=bool:?}, gpioden: {=bool:?}, gpiofen: {=bool:?} }}" , self . gpioaen () , self . gpioben () , self . gpiocen () , self . gpioden () , self . gpiofen ())
}
}
#[doc = "GPIO reset register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Gpiorstr(pub u32);
impl Gpiorstr {
#[doc = "I/O port A reset"]
#[inline(always)]
pub const fn gpioarst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "I/O port A reset"]
#[inline(always)]
pub fn set_gpioarst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "I/O port B reset"]
#[inline(always)]
pub const fn gpiobrst(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "I/O port B reset"]
#[inline(always)]
pub fn set_gpiobrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "I/O port C reset"]
#[inline(always)]
pub const fn gpiocrst(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "I/O port C reset"]
#[inline(always)]
pub fn set_gpiocrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "I/O port D reset"]
#[inline(always)]
pub const fn gpiodrst(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "I/O port D reset"]
#[inline(always)]
pub fn set_gpiodrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "I/O port F reset"]
#[inline(always)]
pub const fn gpiofrst(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "I/O port F reset"]
#[inline(always)]
pub fn set_gpiofrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
}
impl Default for Gpiorstr {
#[inline(always)]
fn default() -> Gpiorstr {
Gpiorstr(0)
}
}
impl core::fmt::Debug for Gpiorstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpiorstr")
.field("gpioarst", &self.gpioarst())
.field("gpiobrst", &self.gpiobrst())
.field("gpiocrst", &self.gpiocrst())
.field("gpiodrst", &self.gpiodrst())
.field("gpiofrst", &self.gpiofrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Gpiorstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Gpiorstr {{ gpioarst: {=bool:?}, gpiobrst: {=bool:?}, gpiocrst: {=bool:?}, gpiodrst: {=bool:?}, gpiofrst: {=bool:?} }}" , self . gpioarst () , self . gpiobrst () , self . gpiocrst () , self . gpiodrst () , self . gpiofrst ())
}
}
#[doc = "GPIO in Sleep mode clock enable register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Gpiosmenr(pub u32);
impl Gpiosmenr {
#[doc = "I/O port A clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpioasmen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "I/O port A clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpioasmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "I/O port B clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpiobsmen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "I/O port B clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpiobsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "I/O port C clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpiocsmen(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "I/O port C clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpiocsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "I/O port D clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpiodsmen(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "I/O port D clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpiodsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "I/O port F clock enable during Sleep mode"]
#[inline(always)]
pub const fn gpiofsmen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "I/O port F clock enable during Sleep mode"]
#[inline(always)]
pub fn set_gpiofsmen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
}
impl Default for Gpiosmenr {
#[inline(always)]
fn default() -> Gpiosmenr {
Gpiosmenr(0)
}
}
impl core::fmt::Debug for Gpiosmenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpiosmenr")
.field("gpioasmen", &self.gpioasmen())
.field("gpiobsmen", &self.gpiobsmen())
.field("gpiocsmen", &self.gpiocsmen())
.field("gpiodsmen", &self.gpiodsmen())
.field("gpiofsmen", &self.gpiofsmen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Gpiosmenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Gpiosmenr {{ gpioasmen: {=bool:?}, gpiobsmen: {=bool:?}, gpiocsmen: {=bool:?}, gpiodsmen: {=bool:?}, gpiofsmen: {=bool:?} }}" , self . gpioasmen () , self . gpiobsmen () , self . gpiocsmen () , self . gpiodsmen () , self . gpiofsmen ())
}
}
#[doc = "Internal clock sources calibration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Icscr(pub u32);
impl Icscr {
#[doc = "HSI clock calibration"]
#[inline(always)]
pub const fn hsical(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[doc = "HSI clock calibration"]
#[inline(always)]
pub fn set_hsical(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
#[doc = "HSI clock trimming"]
#[inline(always)]
pub const fn hsitrim(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x7f;
val as u8
}
#[doc = "HSI clock trimming"]
#[inline(always)]
pub fn set_hsitrim(&mut self, val: u8) {
self.0 = (self.0 & !(0x7f << 8usize)) | (((val as u32) & 0x7f) << 8usize);
}
}
impl Default for Icscr {
#[inline(always)]
fn default() -> Icscr {
Icscr(0)
}
}
impl core::fmt::Debug for Icscr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Icscr")
.field("hsical", &self.hsical())
.field("hsitrim", &self.hsitrim())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Icscr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Icscr {{ hsical: {=u8:?}, hsitrim: {=u8:?} }}",
self.hsical(),
self.hsitrim()
)
}
}
#[doc = "PLL configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pllcfgr(pub u32);
impl Pllcfgr {
#[doc = "PLL input clock source"]
#[inline(always)]
pub const fn pllsrc(&self) -> super::vals::Pllsrc {
let val = (self.0 >> 0usize) & 0x03;
super::vals::Pllsrc::from_bits(val as u8)
}
#[doc = "PLL input clock source"]
#[inline(always)]
pub fn set_pllsrc(&mut self, val: super::vals::Pllsrc) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "Division factor M of the PLL input clock divider"]
#[inline(always)]
pub const fn pllm(&self) -> super::vals::Pllm {
let val = (self.0 >> 4usize) & 0x07;
super::vals::Pllm::from_bits(val as u8)
}
#[doc = "Division factor M of the PLL input clock divider"]
#[inline(always)]
pub fn set_pllm(&mut self, val: super::vals::Pllm) {
self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
}
#[doc = "PLL frequency multiplication factor N"]
#[inline(always)]
pub const fn plln(&self) -> super::vals::Plln {
let val = (self.0 >> 8usize) & 0x7f;
super::vals::Plln::from_bits(val as u8)
}
#[doc = "PLL frequency multiplication factor N"]
#[inline(always)]
pub fn set_plln(&mut self, val: super::vals::Plln) {
self.0 = (self.0 & !(0x7f << 8usize)) | (((val.to_bits() as u32) & 0x7f) << 8usize);
}
#[doc = "PLLPCLK clock output enable"]
#[inline(always)]
pub const fn pllpen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "PLLPCLK clock output enable"]
#[inline(always)]
pub fn set_pllpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "PLL VCO division factor P for PLLPCLK clock output"]
#[inline(always)]
pub const fn pllp(&self) -> super::vals::Pllp {
let val = (self.0 >> 17usize) & 0x1f;
super::vals::Pllp::from_bits(val as u8)
}
#[doc = "PLL VCO division factor P for PLLPCLK clock output"]
#[inline(always)]
pub fn set_pllp(&mut self, val: super::vals::Pllp) {
self.0 = (self.0 & !(0x1f << 17usize)) | (((val.to_bits() as u32) & 0x1f) << 17usize);
}
#[doc = "PLLQCLK clock output enable"]
#[inline(always)]
pub const fn pllqen(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "PLLQCLK clock output enable"]
#[inline(always)]
pub fn set_pllqen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "PLL VCO division factor Q for PLLQCLK clock output"]
#[inline(always)]
pub const fn pllq(&self) -> super::vals::Pllq {
let val = (self.0 >> 25usize) & 0x07;
super::vals::Pllq::from_bits(val as u8)
}
#[doc = "PLL VCO division factor Q for PLLQCLK clock output"]
#[inline(always)]
pub fn set_pllq(&mut self, val: super::vals::Pllq) {
self.0 = (self.0 & !(0x07 << 25usize)) | (((val.to_bits() as u32) & 0x07) << 25usize);
}
#[doc = "PLLRCLK clock output enable"]
#[inline(always)]
pub const fn pllren(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "PLLRCLK clock output enable"]
#[inline(always)]
pub fn set_pllren(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "PLL VCO division factor R for PLLRCLK clock output"]
#[inline(always)]
pub const fn pllr(&self) -> super::vals::Pllr {
let val = (self.0 >> 29usize) & 0x07;
super::vals::Pllr::from_bits(val as u8)
}
#[doc = "PLL VCO division factor R for PLLRCLK clock output"]
#[inline(always)]
pub fn set_pllr(&mut self, val: super::vals::Pllr) {
self.0 = (self.0 & !(0x07 << 29usize)) | (((val.to_bits() as u32) & 0x07) << 29usize);
}
}
impl Default for Pllcfgr {
#[inline(always)]
fn default() -> Pllcfgr {
Pllcfgr(0)
}
}
impl core::fmt::Debug for Pllcfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pllcfgr")
.field("pllsrc", &self.pllsrc())
.field("pllm", &self.pllm())
.field("plln", &self.plln())
.field("pllpen", &self.pllpen())
.field("pllp", &self.pllp())
.field("pllqen", &self.pllqen())
.field("pllq", &self.pllq())
.field("pllren", &self.pllren())
.field("pllr", &self.pllr())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pllcfgr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Pllcfgr {{ pllsrc: {:?}, pllm: {:?}, plln: {:?}, pllpen: {=bool:?}, pllp: {:?}, pllqen: {=bool:?}, pllq: {:?}, pllren: {=bool:?}, pllr: {:?} }}" , self . pllsrc () , self . pllm () , self . plln () , self . pllpen () , self . pllp () , self . pllqen () , self . pllq () , self . pllren () , self . pllr ())
}
}
}
pub mod vals {
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Adcsel {
#[doc = "SYSCLK used as ADC clock source"]
SYS = 0x0,
#[doc = "PLLPCLK used as ADC clock source"]
PLL1_P = 0x01,
#[doc = "HSI used as ADC clock source"]
HSI = 0x02,
_RESERVED_3 = 0x03,
}
impl Adcsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Adcsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Adcsel {
#[inline(always)]
fn from(val: u8) -> Adcsel {
Adcsel::from_bits(val)
}
}
impl From<Adcsel> for u8 {
#[inline(always)]
fn from(val: Adcsel) -> u8 {
Adcsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Cecsel {
#[doc = "HSI divided by 488 used as CEC clock"]
HSI_DIV_488 = 0x0,
#[doc = "LSE used as CEC clock"]
LSE = 0x01,
}
impl Cecsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Cecsel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Cecsel {
#[inline(always)]
fn from(val: u8) -> Cecsel {
Cecsel::from_bits(val)
}
}
impl From<Cecsel> for u8 {
#[inline(always)]
fn from(val: Cecsel) -> u8 {
Cecsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Fdcansel {
#[doc = "PCLK used as FDCAN clock source"]
PCLK1 = 0x0,
#[doc = "PLLQCLK used as FDCAN clock source"]
PLL1_Q = 0x01,
#[doc = "HSE used as FDCAN clock source"]
HSE = 0x02,
_RESERVED_3 = 0x03,
}
impl Fdcansel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Fdcansel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Fdcansel {
#[inline(always)]
fn from(val: u8) -> Fdcansel {
Fdcansel::from_bits(val)
}
}
impl From<Fdcansel> for u8 {
#[inline(always)]
fn from(val: Fdcansel) -> u8 {
Fdcansel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Hpre {
#[doc = "SYSCLK not divided"]
DIV1 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
_RESERVED_3 = 0x03,
_RESERVED_4 = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
#[doc = "SYSCLK is divided by 2"]
DIV2 = 0x08,
#[doc = "SYSCLK is divided by 4"]
DIV4 = 0x09,
#[doc = "SYSCLK is divided by 8"]
DIV8 = 0x0a,
#[doc = "SYSCLK is divided by 16"]
DIV16 = 0x0b,
#[doc = "SYSCLK is divided by 64"]
DIV64 = 0x0c,
#[doc = "SYSCLK is divided by 128"]
DIV128 = 0x0d,
#[doc = "SYSCLK is divided by 256"]
DIV256 = 0x0e,
#[doc = "SYSCLK is divided by 512"]
DIV512 = 0x0f,
}
impl Hpre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Hpre {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Hpre {
#[inline(always)]
fn from(val: u8) -> Hpre {
Hpre::from_bits(val)
}
}
impl From<Hpre> for u8 {
#[inline(always)]
fn from(val: Hpre) -> u8 {
Hpre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Hsidiv {
#[doc = "HSI clock is not divided"]
DIV1 = 0x0,
#[doc = "HSI clock is divided by 2"]
DIV2 = 0x01,
#[doc = "HSI clock is divided by 4"]
DIV4 = 0x02,
#[doc = "HSI clock is divided by 8"]
DIV8 = 0x03,
#[doc = "HSI clock is divided by 16"]
DIV16 = 0x04,
#[doc = "HSI clock is divided by 32"]
DIV32 = 0x05,
#[doc = "HSI clock is divided by 64"]
DIV64 = 0x06,
#[doc = "HSI clock is divided by 128"]
DIV128 = 0x07,
}
impl Hsidiv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Hsidiv {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Hsidiv {
#[inline(always)]
fn from(val: u8) -> Hsidiv {
Hsidiv::from_bits(val)
}
}
impl From<Hsidiv> for u8 {
#[inline(always)]
fn from(val: Hsidiv) -> u8 {
Hsidiv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum I2c1sel {
#[doc = "PCLK used as I2C1 clock source"]
PCLK1 = 0x0,
#[doc = "SYSCLK used as I2C1 clock source"]
SYS = 0x01,
#[doc = "HSI used as I2C1 clock source"]
HSI = 0x02,
_RESERVED_3 = 0x03,
}
impl I2c1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> I2c1sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for I2c1sel {
#[inline(always)]
fn from(val: u8) -> I2c1sel {
I2c1sel::from_bits(val)
}
}
impl From<I2c1sel> for u8 {
#[inline(always)]
fn from(val: I2c1sel) -> u8 {
I2c1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum I2c2i2s1sel {
#[doc = "PCLK used as I2C2/I2S2 clock source"]
PCLK1 = 0x0,
#[doc = "SYSCLK used as I2C2/I2S2 clock source"]
SYS = 0x01,
#[doc = "HSI used as I2C2/I2S2 clock source"]
HSI = 0x02,
#[doc = "External clock used as I2C2/I2S2 clock source"]
I2S_CKIN = 0x03,
}
impl I2c2i2s1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> I2c2i2s1sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for I2c2i2s1sel {
#[inline(always)]
fn from(val: u8) -> I2c2i2s1sel {
I2c2i2s1sel::from_bits(val)
}
}
impl From<I2c2i2s1sel> for u8 {
#[inline(always)]
fn from(val: I2c2i2s1sel) -> u8 {
I2c2i2s1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum I2s1sel {
#[doc = "SYSCLK used as I2S1 clock source"]
SYS = 0x0,
#[doc = "PLLPCLK used as I2S1 clock source"]
PLL1_P = 0x01,
#[doc = "HSI used as I2S1 clock source"]
HSI = 0x02,
#[doc = "External clock used as I2S1 clock source"]
I2S_CKIN = 0x03,
}
impl I2s1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> I2s1sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for I2s1sel {
#[inline(always)]
fn from(val: u8) -> I2s1sel {
I2s1sel::from_bits(val)
}
}
impl From<I2s1sel> for u8 {
#[inline(always)]
fn from(val: I2s1sel) -> u8 {
I2s1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum I2s2sel {
#[doc = "SYSCLK used as I2S2 clock source"]
SYS = 0x0,
#[doc = "PLLPCLK used as I2S2 clock source"]
PLL1_P = 0x01,
#[doc = "HSI used as I2S2 clock source"]
HSI = 0x02,
#[doc = "External clock used as I2S2 clock source"]
I2S_CKIN = 0x03,
}
impl I2s2sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> I2s2sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for I2s2sel {
#[inline(always)]
fn from(val: u8) -> I2s2sel {
I2s2sel::from_bits(val)
}
}
impl From<I2s2sel> for u8 {
#[inline(always)]
fn from(val: I2s2sel) -> u8 {
I2s2sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lptim1sel {
#[doc = "PCLK used as LPTIM1 clock source"]
PCLK1 = 0x0,
#[doc = "LSI used as LPTIM1 clock source"]
LSI = 0x01,
#[doc = "HSI used as LPTIM1 clock source"]
HSI = 0x02,
#[doc = "LSE used as LPTIM1 clock source"]
LSE = 0x03,
}
impl Lptim1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lptim1sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lptim1sel {
#[inline(always)]
fn from(val: u8) -> Lptim1sel {
Lptim1sel::from_bits(val)
}
}
impl From<Lptim1sel> for u8 {
#[inline(always)]
fn from(val: Lptim1sel) -> u8 {
Lptim1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lptim2sel {
#[doc = "PCLK used as LPTIM2 clock source"]
PCLK1 = 0x0,
#[doc = "LSI used as LPTIM2 clock source"]
LSI = 0x01,
#[doc = "HSI used as LPTIM2 clock source"]
HSI = 0x02,
#[doc = "LSE used as LPTIM2 clock source"]
LSE = 0x03,
}
impl Lptim2sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lptim2sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lptim2sel {
#[inline(always)]
fn from(val: u8) -> Lptim2sel {
Lptim2sel::from_bits(val)
}
}
impl From<Lptim2sel> for u8 {
#[inline(always)]
fn from(val: Lptim2sel) -> u8 {
Lptim2sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lpuart1sel {
#[doc = "PCLK used as LPUART1 clock source"]
PCLK1 = 0x0,
#[doc = "SYSCLK used as LPUART1 clock source"]
SYS = 0x01,
#[doc = "HSI used as LPUART1 clock source"]
HSI = 0x02,
#[doc = "LSE used as LPUART1 clock source"]
LSE = 0x03,
}
impl Lpuart1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lpuart1sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lpuart1sel {
#[inline(always)]
fn from(val: u8) -> Lpuart1sel {
Lpuart1sel::from_bits(val)
}
}
impl From<Lpuart1sel> for u8 {
#[inline(always)]
fn from(val: Lpuart1sel) -> u8 {
Lpuart1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lpuart2sel {
#[doc = "PCLK used as LPUART2 clock source"]
PCLK1 = 0x0,
#[doc = "SYSCLK used as LPUART2 clock source"]
SYS = 0x01,
#[doc = "HSI used as LPUART2 clock source"]
HSI = 0x02,
#[doc = "LSE used as LPUART2 clock source"]
LSE = 0x03,
}
impl Lpuart2sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lpuart2sel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lpuart2sel {
#[inline(always)]
fn from(val: u8) -> Lpuart2sel {
Lpuart2sel::from_bits(val)
}
}
impl From<Lpuart2sel> for u8 {
#[inline(always)]
fn from(val: Lpuart2sel) -> u8 {
Lpuart2sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Lsedrv {
#[doc = "Low driving capability"]
LOW = 0x0,
#[doc = "Medium low driving capability"]
MEDIUM_LOW = 0x01,
#[doc = "Medium high driving capability"]
MEDIUM_HIGH = 0x02,
#[doc = "High driving capability"]
HIGH = 0x03,
}
impl Lsedrv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Lsedrv {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Lsedrv {
#[inline(always)]
fn from(val: u8) -> Lsedrv {
Lsedrv::from_bits(val)
}
}
impl From<Lsedrv> for u8 {
#[inline(always)]
fn from(val: Lsedrv) -> u8 {
Lsedrv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Mcopre {
#[doc = "MCO1 not divided"]
DIV1 = 0x0,
#[doc = "MCO clock is divided by 2"]
DIV2 = 0x01,
#[doc = "MCO clock is divided by 4"]
DIV4 = 0x02,
#[doc = "MCO clock is divided by 8"]
DIV8 = 0x03,
#[doc = "MCO clock is divided divided by 16"]
DIV16 = 0x04,
#[doc = "MCO clock is divided divided by 32"]
DIV32 = 0x05,
#[doc = "MCO clock is divided divided by 64"]
DIV64 = 0x06,
#[doc = "MCO clock is divided divided by 128"]
DIV128 = 0x07,
#[doc = "MCO clock is divided divided by 256"]
DIV256 = 0x08,
#[doc = "MCO clock is divided divided by 512"]
DIV512 = 0x09,
#[doc = "MCO clock is divided divided by 1024"]
DIV1024 = 0x0a,
_RESERVED_b = 0x0b,
_RESERVED_c = 0x0c,
_RESERVED_d = 0x0d,
_RESERVED_e = 0x0e,
_RESERVED_f = 0x0f,
}
impl Mcopre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Mcopre {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Mcopre {
#[inline(always)]
fn from(val: u8) -> Mcopre {
Mcopre::from_bits(val)
}
}
impl From<Mcopre> for u8 {
#[inline(always)]
fn from(val: Mcopre) -> u8 {
Mcopre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Mcosel {
#[doc = "No clock, MCO output disabled"]
DISABLE = 0x0,
#[doc = "SYSCLK selected as MCO source"]
SYS = 0x01,
_RESERVED_2 = 0x02,
#[doc = "HSI selected as MCO source"]
HSI = 0x03,
#[doc = "HSE selected as MCO source"]
HSE = 0x04,
#[doc = "PLLRCLK selected as MCO source"]
PLLRCLK = 0x05,
#[doc = "LSI selected as MCO source"]
LSI = 0x06,
#[doc = "LSE selected as MCO source"]
LSE = 0x07,
#[doc = "PLLPCLK selected as MCO source"]
PLL1_P = 0x08,
#[doc = "PLLQCLK selected as MCO source"]
PLL1_Q = 0x09,
#[doc = "RTCCLK selected as MCO source"]
RTCCLK = 0x0a,
#[doc = "RTC_Wakeup selected as MCO source"]
RTC_WKUP = 0x0b,
_RESERVED_c = 0x0c,
_RESERVED_d = 0x0d,
_RESERVED_e = 0x0e,
_RESERVED_f = 0x0f,
}
impl Mcosel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Mcosel {
unsafe { core::mem::transmute(val & 0x0f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Mcosel {
#[inline(always)]
fn from(val: u8) -> Mcosel {
Mcosel::from_bits(val)
}
}
impl From<Mcosel> for u8 {
#[inline(always)]
fn from(val: Mcosel) -> u8 {
Mcosel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllm {
DIV1 = 0x0,
DIV2 = 0x01,
DIV3 = 0x02,
DIV4 = 0x03,
DIV5 = 0x04,
DIV6 = 0x05,
DIV7 = 0x06,
DIV8 = 0x07,
}
impl Pllm {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllm {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllm {
#[inline(always)]
fn from(val: u8) -> Pllm {
Pllm::from_bits(val)
}
}
impl From<Pllm> for u8 {
#[inline(always)]
fn from(val: Pllm) -> u8 {
Pllm::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Plln {
_RESERVED_0 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
_RESERVED_3 = 0x03,
_RESERVED_4 = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
MUL8 = 0x08,
MUL9 = 0x09,
MUL10 = 0x0a,
MUL11 = 0x0b,
MUL12 = 0x0c,
MUL13 = 0x0d,
MUL14 = 0x0e,
MUL15 = 0x0f,
MUL16 = 0x10,
MUL17 = 0x11,
MUL18 = 0x12,
MUL19 = 0x13,
MUL20 = 0x14,
MUL21 = 0x15,
MUL22 = 0x16,
MUL23 = 0x17,
MUL24 = 0x18,
MUL25 = 0x19,
MUL26 = 0x1a,
MUL27 = 0x1b,
MUL28 = 0x1c,
MUL29 = 0x1d,
MUL30 = 0x1e,
MUL31 = 0x1f,
MUL32 = 0x20,
MUL33 = 0x21,
MUL34 = 0x22,
MUL35 = 0x23,
MUL36 = 0x24,
MUL37 = 0x25,
MUL38 = 0x26,
MUL39 = 0x27,
MUL40 = 0x28,
MUL41 = 0x29,
MUL42 = 0x2a,
MUL43 = 0x2b,
MUL44 = 0x2c,
MUL45 = 0x2d,
MUL46 = 0x2e,
MUL47 = 0x2f,
MUL48 = 0x30,
MUL49 = 0x31,
MUL50 = 0x32,
MUL51 = 0x33,
MUL52 = 0x34,
MUL53 = 0x35,
MUL54 = 0x36,
MUL55 = 0x37,
MUL56 = 0x38,
MUL57 = 0x39,
MUL58 = 0x3a,
MUL59 = 0x3b,
MUL60 = 0x3c,
MUL61 = 0x3d,
MUL62 = 0x3e,
MUL63 = 0x3f,
MUL64 = 0x40,
MUL65 = 0x41,
MUL66 = 0x42,
MUL67 = 0x43,
MUL68 = 0x44,
MUL69 = 0x45,
MUL70 = 0x46,
MUL71 = 0x47,
MUL72 = 0x48,
MUL73 = 0x49,
MUL74 = 0x4a,
MUL75 = 0x4b,
MUL76 = 0x4c,
MUL77 = 0x4d,
MUL78 = 0x4e,
MUL79 = 0x4f,
MUL80 = 0x50,
MUL81 = 0x51,
MUL82 = 0x52,
MUL83 = 0x53,
MUL84 = 0x54,
MUL85 = 0x55,
MUL86 = 0x56,
_RESERVED_57 = 0x57,
_RESERVED_58 = 0x58,
_RESERVED_59 = 0x59,
_RESERVED_5a = 0x5a,
_RESERVED_5b = 0x5b,
_RESERVED_5c = 0x5c,
_RESERVED_5d = 0x5d,
_RESERVED_5e = 0x5e,
_RESERVED_5f = 0x5f,
_RESERVED_60 = 0x60,
_RESERVED_61 = 0x61,
_RESERVED_62 = 0x62,
_RESERVED_63 = 0x63,
_RESERVED_64 = 0x64,
_RESERVED_65 = 0x65,
_RESERVED_66 = 0x66,
_RESERVED_67 = 0x67,
_RESERVED_68 = 0x68,
_RESERVED_69 = 0x69,
_RESERVED_6a = 0x6a,
_RESERVED_6b = 0x6b,
_RESERVED_6c = 0x6c,
_RESERVED_6d = 0x6d,
_RESERVED_6e = 0x6e,
_RESERVED_6f = 0x6f,
_RESERVED_70 = 0x70,
_RESERVED_71 = 0x71,
_RESERVED_72 = 0x72,
_RESERVED_73 = 0x73,
_RESERVED_74 = 0x74,
_RESERVED_75 = 0x75,
_RESERVED_76 = 0x76,
_RESERVED_77 = 0x77,
_RESERVED_78 = 0x78,
_RESERVED_79 = 0x79,
_RESERVED_7a = 0x7a,
_RESERVED_7b = 0x7b,
_RESERVED_7c = 0x7c,
_RESERVED_7d = 0x7d,
_RESERVED_7e = 0x7e,
_RESERVED_7f = 0x7f,
}
impl Plln {
#[inline(always)]
pub const fn from_bits(val: u8) -> Plln {
unsafe { core::mem::transmute(val & 0x7f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Plln {
#[inline(always)]
fn from(val: u8) -> Plln {
Plln::from_bits(val)
}
}
impl From<Plln> for u8 {
#[inline(always)]
fn from(val: Plln) -> u8 {
Plln::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllp {
_RESERVED_0 = 0x0,
DIV2 = 0x01,
DIV3 = 0x02,
DIV4 = 0x03,
DIV5 = 0x04,
DIV6 = 0x05,
DIV7 = 0x06,
DIV8 = 0x07,
DIV9 = 0x08,
DIV10 = 0x09,
DIV11 = 0x0a,
DIV12 = 0x0b,
DIV13 = 0x0c,
DIV14 = 0x0d,
DIV15 = 0x0e,
DIV16 = 0x0f,
DIV17 = 0x10,
DIV18 = 0x11,
DIV19 = 0x12,
DIV20 = 0x13,
DIV21 = 0x14,
DIV22 = 0x15,
DIV23 = 0x16,
DIV24 = 0x17,
DIV25 = 0x18,
DIV26 = 0x19,
DIV27 = 0x1a,
DIV28 = 0x1b,
DIV29 = 0x1c,
DIV30 = 0x1d,
DIV31 = 0x1e,
DIV32 = 0x1f,
}
impl Pllp {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllp {
unsafe { core::mem::transmute(val & 0x1f) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllp {
#[inline(always)]
fn from(val: u8) -> Pllp {
Pllp::from_bits(val)
}
}
impl From<Pllp> for u8 {
#[inline(always)]
fn from(val: Pllp) -> u8 {
Pllp::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllq {
_RESERVED_0 = 0x0,
DIV2 = 0x01,
DIV3 = 0x02,
DIV4 = 0x03,
DIV5 = 0x04,
DIV6 = 0x05,
DIV7 = 0x06,
DIV8 = 0x07,
}
impl Pllq {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllq {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllq {
#[inline(always)]
fn from(val: u8) -> Pllq {
Pllq::from_bits(val)
}
}
impl From<Pllq> for u8 {
#[inline(always)]
fn from(val: Pllq) -> u8 {
Pllq::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllr {
_RESERVED_0 = 0x0,
DIV2 = 0x01,
DIV3 = 0x02,
DIV4 = 0x03,
DIV5 = 0x04,
DIV6 = 0x05,
DIV7 = 0x06,
DIV8 = 0x07,
}
impl Pllr {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllr {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllr {
#[inline(always)]
fn from(val: u8) -> Pllr {
Pllr::from_bits(val)
}
}
impl From<Pllr> for u8 {
#[inline(always)]
fn from(val: Pllr) -> u8 {
Pllr::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pllsrc {
#[doc = "No clock selected as PLL entry clock source"]
DISABLE = 0x0,
_RESERVED_1 = 0x01,
#[doc = "HSI selected as PLL entry clock source"]
HSI = 0x02,
#[doc = "HSE selected as PLL entry clock source"]
HSE = 0x03,
}
impl Pllsrc {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pllsrc {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pllsrc {
#[inline(always)]
fn from(val: u8) -> Pllsrc {
Pllsrc::from_bits(val)
}
}
impl From<Pllsrc> for u8 {
#[inline(always)]
fn from(val: Pllsrc) -> u8 {
Pllsrc::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Ppre {
#[doc = "HCLK not divided"]
DIV1 = 0x0,
_RESERVED_1 = 0x01,
_RESERVED_2 = 0x02,
_RESERVED_3 = 0x03,
#[doc = "HCLK is divided by 2"]
DIV2 = 0x04,
#[doc = "HCLK is divided by 4"]
DIV4 = 0x05,
#[doc = "HCLK is divided by 8"]
DIV8 = 0x06,
#[doc = "HCLK is divided by 16"]
DIV16 = 0x07,
}
impl Ppre {
#[inline(always)]
pub const fn from_bits(val: u8) -> Ppre {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Ppre {
#[inline(always)]
fn from(val: u8) -> Ppre {
Ppre::from_bits(val)
}
}
impl From<Ppre> for u8 {
#[inline(always)]
fn from(val: Ppre) -> u8 {
Ppre::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Rngdiv {
#[doc = "RNG clock is not divided"]
DIV1 = 0x0,
#[doc = "RNG clock is divided by 2"]
DIV2 = 0x01,
#[doc = "RNG clock is divided by 4"]
DIV4 = 0x02,
#[doc = "RNG clock is divided by 8"]
DIV8 = 0x03,
}
impl Rngdiv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Rngdiv {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Rngdiv {
#[inline(always)]
fn from(val: u8) -> Rngdiv {
Rngdiv::from_bits(val)
}
}
impl From<Rngdiv> for u8 {
#[inline(always)]
fn from(val: Rngdiv) -> u8 {
Rngdiv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Rngsel {
#[doc = "No clock used as RNG clock source"]
DISABLE = 0x0,
#[doc = "HSI divided by 8 used as RNG clock source"]
HSI_DIV_8 = 0x01,
#[doc = "SYSCLK used as RNG clock source"]
SYS = 0x02,
#[doc = "PLLQCLK used as RNG clock source"]
PLL1_Q = 0x03,
}
impl Rngsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Rngsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Rngsel {
#[inline(always)]
fn from(val: u8) -> Rngsel {
Rngsel::from_bits(val)
}
}
impl From<Rngsel> for u8 {
#[inline(always)]
fn from(val: Rngsel) -> u8 {
Rngsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Rtcsel {
#[doc = "No clock used as RTC clock"]
DISABLE = 0x0,
#[doc = "LSE used as RTC clock"]
LSE = 0x01,
#[doc = "LSI used as RTC clock"]
LSI = 0x02,
#[doc = "HSE divided by 32 used as RTC clock"]
HSE_DIV_32 = 0x03,
}
impl Rtcsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Rtcsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Rtcsel {
#[inline(always)]
fn from(val: u8) -> Rtcsel {
Rtcsel::from_bits(val)
}
}
impl From<Rtcsel> for u8 {
#[inline(always)]
fn from(val: Rtcsel) -> u8 {
Rtcsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Sw {
#[doc = "HSI selected as system clock"]
HSI = 0x0,
#[doc = "HSE selected as system clock"]
HSE = 0x01,
#[doc = "PLLRCLK selected as system clock"]
PLL1_R = 0x02,
#[doc = "LSI selected as system clock"]
LSI = 0x03,
#[doc = "LSE selected as system clock"]
LSE = 0x04,
_RESERVED_5 = 0x05,
_RESERVED_6 = 0x06,
_RESERVED_7 = 0x07,
}
impl Sw {
#[inline(always)]
pub const fn from_bits(val: u8) -> Sw {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Sw {
#[inline(always)]
fn from(val: u8) -> Sw {
Sw::from_bits(val)
}
}
impl From<Sw> for u8 {
#[inline(always)]
fn from(val: Sw) -> u8 {
Sw::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Tim15sel {
#[doc = "TIMPCLK used as TIM15 clock source"]
PCLK1_TIM = 0x0,
#[doc = "PLLQCLK used as TIM15 clock source"]
PLL1_Q = 0x01,
}
impl Tim15sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Tim15sel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Tim15sel {
#[inline(always)]
fn from(val: u8) -> Tim15sel {
Tim15sel::from_bits(val)
}
}
impl From<Tim15sel> for u8 {
#[inline(always)]
fn from(val: Tim15sel) -> u8 {
Tim15sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Tim1sel {
#[doc = "TIMPCLK used as TIM1 clock source"]
PCLK1_TIM = 0x0,
#[doc = "PLLQCLK used as TIM1 clock source"]
PLL1_Q = 0x01,
}
impl Tim1sel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Tim1sel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Tim1sel {
#[inline(always)]
fn from(val: u8) -> Tim1sel {
Tim1sel::from_bits(val)
}
}
impl From<Tim1sel> for u8 {
#[inline(always)]
fn from(val: Tim1sel) -> u8 {
Tim1sel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Usartsel {
#[doc = "PCLK used as USART clock source"]
PCLK1 = 0x0,
#[doc = "SYSCLK used as USART clock source"]
SYS = 0x01,
#[doc = "HSI used as USART clock source"]
HSI = 0x02,
#[doc = "LSE used as USART clock source"]
LSE = 0x03,
}
impl Usartsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Usartsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Usartsel {
#[inline(always)]
fn from(val: u8) -> Usartsel {
Usartsel::from_bits(val)
}
}
impl From<Usartsel> for u8 {
#[inline(always)]
fn from(val: Usartsel) -> u8 {
Usartsel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Usbsel {
_RESERVED_0 = 0x0,
#[doc = "HSE used as USB clock source"]
HSE = 0x01,
#[doc = "PLLQCLK used as USB clock source"]
PLL1_Q = 0x02,
_RESERVED_3 = 0x03,
}
impl Usbsel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Usbsel {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Usbsel {
#[inline(always)]
fn from(val: u8) -> Usbsel {
Usbsel::from_bits(val)
}
}
impl From<Usbsel> for u8 {
#[inline(always)]
fn from(val: Usbsel) -> u8 {
Usbsel::to_bits(val)
}
}
}