#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
#[doc = "FLASH address block description"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Flash {
ptr: *mut u8,
}
unsafe impl Send for Flash {}
unsafe impl Sync for Flash {}
impl Flash {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "FLASH access control register"]
#[inline(always)]
pub const fn acr(self) -> crate::common::Reg<regs::Acr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "FLASH key register"]
#[inline(always)]
pub const fn nskeyr(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "FLASH option key register"]
#[inline(always)]
pub const fn optkeyr(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
#[doc = "FLASH operation status register"]
#[inline(always)]
pub const fn opsr(self) -> crate::common::Reg<regs::Opsr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
}
#[doc = "FLASH option control register"]
#[inline(always)]
pub const fn optcr(self) -> crate::common::Reg<regs::Optcr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
}
#[doc = "FLASH non-secure status register"]
#[inline(always)]
pub const fn nssr(self) -> crate::common::Reg<regs::Nssr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
}
#[doc = "FLASH secure status register"]
#[inline(always)]
pub const fn secsr(self) -> crate::common::Reg<regs::Secsr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
}
#[doc = "FLASH Non Secure control register"]
#[inline(always)]
pub const fn nscr(self) -> crate::common::Reg<regs::Nscr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
}
#[doc = "FLASH non-secure clear control register"]
#[inline(always)]
pub const fn nsccr(self) -> crate::common::Reg<regs::Nsccr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
}
#[doc = "FLASH privilege configuration register"]
#[inline(always)]
pub const fn privcfgr(self) -> crate::common::Reg<regs::Privcfgr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
}
#[doc = "FLASH HDP extension register"]
#[inline(always)]
pub const fn hdpextr(self) -> crate::common::Reg<regs::Hdpextr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
}
#[doc = "FLASH option status register"]
#[inline(always)]
pub const fn optsr_cur(self) -> crate::common::Reg<regs::Optsr, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
}
#[doc = "FLASH option status register"]
#[inline(always)]
pub const fn optsr_prg(self) -> crate::common::Reg<regs::Optsr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
}
#[doc = "FLASH option status register 2"]
#[inline(always)]
pub const fn optsr2_cur(self) -> crate::common::Reg<regs::Optsr2, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) }
}
#[doc = "FLASH option status register 2"]
#[inline(always)]
pub const fn optsr2_prg(self) -> crate::common::Reg<regs::Optsr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) }
}
#[doc = "FLASH non-secure unique boot entry register"]
#[inline(always)]
pub const fn nsbootr_cur(self) -> crate::common::Reg<regs::Nsbootr, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
}
#[doc = "FLASH non-secure unique boot entry address"]
#[inline(always)]
pub const fn nsbootr_prg(self) -> crate::common::Reg<regs::Nsbootr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x84usize) as _) }
}
#[doc = "FLASH non-secure OTP block lock"]
#[inline(always)]
pub const fn otpblr_cur(self) -> crate::common::Reg<regs::Otpblr, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) }
}
#[doc = "FLASH non-secure OTP block lock"]
#[inline(always)]
pub const fn otpblr_prg(self) -> crate::common::Reg<regs::Otpblr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) }
}
#[doc = "FLASH privilege register for bank 1"]
#[inline(always)]
pub const fn privbb1r(self) -> crate::common::Reg<regs::Privbb, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc0usize) as _) }
}
#[doc = "FLASH write sector protection for Bank1"]
#[inline(always)]
pub const fn wrpsgn1r_cur(self) -> crate::common::Reg<regs::Wrp, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe8usize) as _) }
}
#[doc = "FLASH write sector protection for Bank1"]
#[inline(always)]
pub const fn wrpsgn1r_prg(self) -> crate::common::Reg<regs::Wrp, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xecusize) as _) }
}
#[doc = "FLASH HDP Bank1 register"]
#[inline(always)]
pub const fn hdp1r_cur(self) -> crate::common::Reg<regs::Hdp1r, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf8usize) as _) }
}
#[doc = "FLASH HDP Bank1 register"]
#[inline(always)]
pub const fn hdp1r_prg(self) -> crate::common::Reg<regs::Hdp1r, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xfcusize) as _) }
}
#[doc = "FLASH Flash ECC correction register"]
#[inline(always)]
pub const fn ecccorr(self) -> crate::common::Reg<regs::Ecccorr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0100usize) as _) }
}
#[doc = "FLASH ECC detection register"]
#[inline(always)]
pub const fn eccdetr(self) -> crate::common::Reg<regs::Eccdetr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0104usize) as _) }
}
#[doc = "FLASH ECC data"]
#[inline(always)]
pub const fn eccdr(self) -> crate::common::Reg<regs::Eccdr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0108usize) as _) }
}
#[doc = "FLASH write sector protection for Bank2"]
#[inline(always)]
pub const fn wrpsgn2r_cur(self) -> crate::common::Reg<regs::Wrp, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01e8usize) as _) }
}
#[doc = "FLASH write sector protection for Bank2"]
#[inline(always)]
pub const fn wrpsgn2r_prg(self) -> crate::common::Reg<regs::Wrp, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01ecusize) as _) }
}
#[doc = "FLASH HDP Bank2 register"]
#[inline(always)]
pub const fn hdp2r_cur(self) -> crate::common::Reg<regs::Hdp2r, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01f8usize) as _) }
}
#[doc = "FLASH HDP Bank2 register"]
#[inline(always)]
pub const fn hdp2r_prg(self) -> crate::common::Reg<regs::Hdp2r, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x01fcusize) as _) }
}
}
pub mod regs {
#[doc = "FLASH access control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Acr(pub u32);
impl Acr {
#[doc = "Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. ... Note: No check is performed by hardware to verify that the configuration is correct."]
#[inline(always)]
pub const fn latency(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x0f;
val as u8
}
#[doc = "Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. ... Note: No check is performed by hardware to verify that the configuration is correct."]
#[inline(always)]
pub fn set_latency(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
}
#[doc = "Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to for details. Note: No check is performed to verify that the configuration is correct. Two WRHIGHFREQ values can be selected for some frequencies."]
#[inline(always)]
pub const fn wrhighfreq(&self) -> u8 {
let val = (self.0 >> 4usize) & 0x03;
val as u8
}
#[doc = "Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to for details. Note: No check is performed to verify that the configuration is correct. Two WRHIGHFREQ values can be selected for some frequencies."]
#[inline(always)]
pub fn set_wrhighfreq(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
}
#[doc = "Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account. Bits used to control the prefetch."]
#[inline(always)]
pub const fn prften(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account. Bits used to control the prefetch."]
#[inline(always)]
pub fn set_prften(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "Smart prefetch enable. When bit value is modified, user must read back ACR register to be sure S_PRFTEN has been taken into account. Bits used to control the prefetch functionality."]
#[inline(always)]
pub const fn s_prften(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "Smart prefetch enable. When bit value is modified, user must read back ACR register to be sure S_PRFTEN has been taken into account. Bits used to control the prefetch functionality."]
#[inline(always)]
pub fn set_s_prften(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
}
impl Default for Acr {
#[inline(always)]
fn default() -> Acr {
Acr(0)
}
}
impl core::fmt::Debug for Acr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Acr")
.field("latency", &self.latency())
.field("wrhighfreq", &self.wrhighfreq())
.field("prften", &self.prften())
.field("s_prften", &self.s_prften())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Acr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Acr {{ latency: {=u8:?}, wrhighfreq: {=u8:?}, prften: {=bool:?}, s_prften: {=bool:?} }}",
self.latency(),
self.wrhighfreq(),
self.prften(),
self.s_prften()
)
}
}
#[doc = "FLASH Flash ECC correction register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ecccorr(pub u32);
impl Ecccorr {
#[doc = "ECC error address When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)."]
#[inline(always)]
pub const fn addr_ecc(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[doc = "ECC error address When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)."]
#[inline(always)]
pub fn set_addr_ecc(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
#[doc = "ECC bank flag for corrected ECC error It indicates which bank is concerned by ECC error"]
#[inline(always)]
pub const fn bk_ecc(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "ECC bank flag for corrected ECC error It indicates which bank is concerned by ECC error"]
#[inline(always)]
pub fn set_bk_ecc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "ECC flag for corrected ECC error in system FLASH It indicates if system Flash memory is concerned by ECC error."]
#[inline(always)]
pub const fn sysf_ecc(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "ECC flag for corrected ECC error in system FLASH It indicates if system Flash memory is concerned by ECC error."]
#[inline(always)]
pub fn set_sysf_ecc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "OTP ECC error bit This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield."]
#[inline(always)]
pub const fn otp_ecc(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "OTP ECC error bit This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield."]
#[inline(always)]
pub fn set_otp_ecc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation."]
#[inline(always)]
pub const fn ecccie(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation."]
#[inline(always)]
pub fn set_ecccie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
#[doc = "ECC correction set by hardware when single ECC error has been detected and corrected. Cleared by writing 1."]
#[inline(always)]
pub const fn eccc(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "ECC correction set by hardware when single ECC error has been detected and corrected. Cleared by writing 1."]
#[inline(always)]
pub fn set_eccc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
}
impl Default for Ecccorr {
#[inline(always)]
fn default() -> Ecccorr {
Ecccorr(0)
}
}
impl core::fmt::Debug for Ecccorr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ecccorr")
.field("addr_ecc", &self.addr_ecc())
.field("bk_ecc", &self.bk_ecc())
.field("sysf_ecc", &self.sysf_ecc())
.field("otp_ecc", &self.otp_ecc())
.field("ecccie", &self.ecccie())
.field("eccc", &self.eccc())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ecccorr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ecccorr {{ addr_ecc: {=u16:?}, bk_ecc: {=bool:?}, sysf_ecc: {=bool:?}, otp_ecc: {=bool:?}, ecccie: {=bool:?}, eccc: {=bool:?} }}" , self . addr_ecc () , self . bk_ecc () , self . sysf_ecc () , self . otp_ecc () , self . ecccie () , self . eccc ())
}
}
#[doc = "FLASH ECC detection register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Eccdetr(pub u32);
impl Eccdetr {
#[doc = "ECC error address When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved. The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)."]
#[inline(always)]
pub const fn addr_ecc(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[doc = "ECC error address When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved. The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)."]
#[inline(always)]
pub fn set_addr_ecc(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
#[doc = "ECC fail bank for double ECC Error It indicates which bank is concerned by ECC error"]
#[inline(always)]
pub const fn bk_ecc(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "ECC fail bank for double ECC Error It indicates which bank is concerned by ECC error"]
#[inline(always)]
pub fn set_bk_ecc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "ECC fail for double ECC error in system Flash memory It indicates if system Flash memory is concerned by ECC error."]
#[inline(always)]
pub const fn sysf_ecc(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "ECC fail for double ECC error in system Flash memory It indicates if system Flash memory is concerned by ECC error."]
#[inline(always)]
pub fn set_sysf_ecc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "OTP ECC error bit This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bit field."]
#[inline(always)]
pub const fn otp_ecc(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "OTP ECC error bit This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bit field."]
#[inline(always)]
pub fn set_otp_ecc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "ECC detection set by hardware when two ECC error has been detected. When this bit is set, a NMI is generated. Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors."]
#[inline(always)]
pub const fn eccd(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "ECC detection set by hardware when two ECC error has been detected. When this bit is set, a NMI is generated. Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors."]
#[inline(always)]
pub fn set_eccd(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Eccdetr {
#[inline(always)]
fn default() -> Eccdetr {
Eccdetr(0)
}
}
impl core::fmt::Debug for Eccdetr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Eccdetr")
.field("addr_ecc", &self.addr_ecc())
.field("bk_ecc", &self.bk_ecc())
.field("sysf_ecc", &self.sysf_ecc())
.field("otp_ecc", &self.otp_ecc())
.field("eccd", &self.eccd())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Eccdetr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Eccdetr {{ addr_ecc: {=u16:?}, bk_ecc: {=bool:?}, sysf_ecc: {=bool:?}, otp_ecc: {=bool:?}, eccd: {=bool:?} }}" , self . addr_ecc () , self . bk_ecc () , self . sysf_ecc () , self . otp_ecc () , self . eccd ())
}
}
#[doc = "FLASH ECC data"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Eccdr(pub u32);
impl Eccdr {
#[doc = "ECC error data When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit of data (data area, read-only/OTP area), the failing data is read to this register. By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory."]
#[inline(always)]
pub const fn data_ecc(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[doc = "ECC error data When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit of data (data area, read-only/OTP area), the failing data is read to this register. By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory."]
#[inline(always)]
pub fn set_data_ecc(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
}
impl Default for Eccdr {
#[inline(always)]
fn default() -> Eccdr {
Eccdr(0)
}
}
impl core::fmt::Debug for Eccdr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Eccdr").field("data_ecc", &self.data_ecc()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Eccdr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Eccdr {{ data_ecc: {=u16:?} }}", self.data_ecc())
}
}
#[doc = "FLASH HDP Bank1 register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Hdp1r(pub u32);
impl Hdp1r {
#[doc = "HDPL barrier start set in number of 8 Kbytes sectors"]
#[inline(always)]
pub const fn hdp1_strt(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x07;
val as u8
}
#[doc = "HDPL barrier start set in number of 8 Kbytes sectors"]
#[inline(always)]
pub fn set_hdp1_strt(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
}
#[doc = "HDPL barrier end set in number of 8 Kbytes sectors"]
#[inline(always)]
pub const fn hdp1_end(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x07;
val as u8
}
#[doc = "HDPL barrier end set in number of 8 Kbytes sectors"]
#[inline(always)]
pub fn set_hdp1_end(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
}
}
impl Default for Hdp1r {
#[inline(always)]
fn default() -> Hdp1r {
Hdp1r(0)
}
}
impl core::fmt::Debug for Hdp1r {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Hdp1r")
.field("hdp1_strt", &self.hdp1_strt())
.field("hdp1_end", &self.hdp1_end())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Hdp1r {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Hdp1r {{ hdp1_strt: {=u8:?}, hdp1_end: {=u8:?} }}",
self.hdp1_strt(),
self.hdp1_end()
)
}
}
#[doc = "FLASH HDP Bank2 register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Hdp2r(pub u32);
impl Hdp2r {
#[doc = "Bank 2 HDPL barrier start set in number of 8 Kbytes sectors"]
#[inline(always)]
pub const fn hdp2_strt(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x07;
val as u8
}
#[doc = "Bank 2 HDPL barrier start set in number of 8 Kbytes sectors"]
#[inline(always)]
pub fn set_hdp2_strt(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
}
#[doc = "Bank 2 HDPL barrier end set in number of 8 Kbytes sectors"]
#[inline(always)]
pub const fn hdp2_end(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x07;
val as u8
}
#[doc = "Bank 2 HDPL barrier end set in number of 8 Kbytes sectors"]
#[inline(always)]
pub fn set_hdp2_end(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
}
}
impl Default for Hdp2r {
#[inline(always)]
fn default() -> Hdp2r {
Hdp2r(0)
}
}
impl core::fmt::Debug for Hdp2r {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Hdp2r")
.field("hdp2_strt", &self.hdp2_strt())
.field("hdp2_end", &self.hdp2_end())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Hdp2r {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Hdp2r {{ hdp2_strt: {=u8:?}, hdp2_end: {=u8:?} }}",
self.hdp2_strt(),
self.hdp2_end()
)
}
}
#[doc = "FLASH HDP extension register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Hdpextr(pub u32);
impl Hdpextr {
#[doc = "HDP area extension in 8 Kbytes sectors in Bank1. Extension is added after the HDP1_END sector."]
#[inline(always)]
pub const fn hdp1_ext(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x07;
val as u8
}
#[doc = "HDP area extension in 8 Kbytes sectors in Bank1. Extension is added after the HDP1_END sector."]
#[inline(always)]
pub fn set_hdp1_ext(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
}
#[doc = "HDP area extension in 8 Kbytes sectors in Bank2. Extension is added after the HDP2_END sector."]
#[inline(always)]
pub const fn hdp2_ext(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x07;
val as u8
}
#[doc = "HDP area extension in 8 Kbytes sectors in Bank2. Extension is added after the HDP2_END sector."]
#[inline(always)]
pub fn set_hdp2_ext(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
}
}
impl Default for Hdpextr {
#[inline(always)]
fn default() -> Hdpextr {
Hdpextr(0)
}
}
impl core::fmt::Debug for Hdpextr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Hdpextr")
.field("hdp1_ext", &self.hdp1_ext())
.field("hdp2_ext", &self.hdp2_ext())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Hdpextr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Hdpextr {{ hdp1_ext: {=u8:?}, hdp2_ext: {=u8:?} }}",
self.hdp1_ext(),
self.hdp2_ext()
)
}
}
#[doc = "FLASH non-secure unique boot entry register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Nsbootr(pub u32);
impl Nsbootr {
#[doc = "A field locking the values of SWAP_BANK, and NSBOOTADD settings."]
#[inline(always)]
pub const fn nsboot_lock(&self) -> super::vals::NsbootrNsbootLock {
let val = (self.0 >> 0usize) & 0xff;
super::vals::NsbootrNsbootLock::from_bits(val as u8)
}
#[doc = "A field locking the values of SWAP_BANK, and NSBOOTADD settings."]
#[inline(always)]
pub fn set_nsboot_lock(&mut self, val: super::vals::NsbootrNsbootLock) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize);
}
#[doc = "unique boot entry address These bits reflect the UBE address"]
#[inline(always)]
pub const fn nsbootadd(&self) -> u32 {
let val = (self.0 >> 8usize) & 0x00ff_ffff;
val as u32
}
#[doc = "unique boot entry address These bits reflect the UBE address"]
#[inline(always)]
pub fn set_nsbootadd(&mut self, val: u32) {
self.0 = (self.0 & !(0x00ff_ffff << 8usize)) | (((val as u32) & 0x00ff_ffff) << 8usize);
}
}
impl Default for Nsbootr {
#[inline(always)]
fn default() -> Nsbootr {
Nsbootr(0)
}
}
impl core::fmt::Debug for Nsbootr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Nsbootr")
.field("nsboot_lock", &self.nsboot_lock())
.field("nsbootadd", &self.nsbootadd())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Nsbootr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Nsbootr {{ nsboot_lock: {:?}, nsbootadd: {=u32:?} }}",
self.nsboot_lock(),
self.nsbootadd()
)
}
}
#[doc = "FLASH non-secure clear control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Nsccr(pub u32);
impl Nsccr {
#[doc = "EOP flag clear bit Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register."]
#[inline(always)]
pub const fn clr_eop(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "EOP flag clear bit Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register."]
#[inline(always)]
pub fn set_clr_eop(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "WRPERR flag clear bit Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register."]
#[inline(always)]
pub const fn clr_wrperr(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "WRPERR flag clear bit Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register."]
#[inline(always)]
pub fn set_clr_wrperr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "PGSERR flag clear bit Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register."]
#[inline(always)]
pub const fn clr_pgserr(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "PGSERR flag clear bit Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register."]
#[inline(always)]
pub fn set_clr_pgserr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "STRBERR flag clear bit Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register."]
#[inline(always)]
pub const fn clr_strberr(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "STRBERR flag clear bit Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register."]
#[inline(always)]
pub fn set_clr_strberr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "INCERR flag clear bit Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register."]
#[inline(always)]
pub const fn clr_incerr(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "INCERR flag clear bit Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register."]
#[inline(always)]
pub fn set_clr_incerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "Clear the flag corresponding flag in FLASH_NSSR by writing this bit."]
#[inline(always)]
pub const fn clr_optchangeerr(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Clear the flag corresponding flag in FLASH_NSSR by writing this bit."]
#[inline(always)]
pub fn set_clr_optchangeerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
}
impl Default for Nsccr {
#[inline(always)]
fn default() -> Nsccr {
Nsccr(0)
}
}
impl core::fmt::Debug for Nsccr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Nsccr")
.field("clr_eop", &self.clr_eop())
.field("clr_wrperr", &self.clr_wrperr())
.field("clr_pgserr", &self.clr_pgserr())
.field("clr_strberr", &self.clr_strberr())
.field("clr_incerr", &self.clr_incerr())
.field("clr_optchangeerr", &self.clr_optchangeerr())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Nsccr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Nsccr {{ clr_eop: {=bool:?}, clr_wrperr: {=bool:?}, clr_pgserr: {=bool:?}, clr_strberr: {=bool:?}, clr_incerr: {=bool:?}, clr_optchangeerr: {=bool:?} }}" , self . clr_eop () , self . clr_wrperr () , self . clr_pgserr () , self . clr_strberr () , self . clr_incerr () , self . clr_optchangeerr ())
}
}
#[doc = "FLASH Non Secure control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Nscr(pub u32);
impl Nscr {
#[doc = "configuration lock bit This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change."]
#[inline(always)]
pub const fn lock(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "configuration lock bit This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change."]
#[inline(always)]
pub fn set_lock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "programming control bit PG can be programmed only when LOCK is cleared to 0. PG allows programming in Bank1 and Bank2."]
#[inline(always)]
pub const fn pg(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "programming control bit PG can be programmed only when LOCK is cleared to 0. PG allows programming in Bank1 and Bank2."]
#[inline(always)]
pub fn set_pg(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "sector erase request Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised."]
#[inline(always)]
pub const fn ser(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "sector erase request Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised."]
#[inline(always)]
pub fn set_ser(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "erase request Setting BER bit to 1 requests a bank erase operation (user Flash memory only). BER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. Note: Write protection error is triggered when a bank erase is required and some sectors are protected."]
#[inline(always)]
pub const fn ber(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "erase request Setting BER bit to 1 requests a bank erase operation (user Flash memory only). BER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. Note: Write protection error is triggered when a bank erase is required and some sectors are protected."]
#[inline(always)]
pub fn set_ber(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "write forcing control bit FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively). Since there is just one write buffer, FW can force a write in bank1 or bank2."]
#[inline(always)]
pub const fn fw(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "write forcing control bit FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively). Since there is just one write buffer, FW can force a write in bank1 or bank2."]
#[inline(always)]
pub fn set_fw(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "erase start control bit STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software."]
#[inline(always)]
pub const fn strt(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "erase start control bit STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software."]
#[inline(always)]
pub fn set_strt(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0. ..."]
#[inline(always)]
pub const fn snb(&self) -> u8 {
let val = (self.0 >> 6usize) & 0x07;
val as u8
}
#[doc = "sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0. ..."]
#[inline(always)]
pub fn set_snb(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 6usize)) | (((val as u32) & 0x07) << 6usize);
}
#[doc = "Mass erase request Setting MER bit to 1 requests a mass erase operation (user Flash memory only). MER can be programmed only when LOCK is cleared to 0. If BER or SER are both set, a PGSERR is raised. Error is triggered when a mass erase is required and some sectors are protected."]
#[inline(always)]
pub const fn mer(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "Mass erase request Setting MER bit to 1 requests a mass erase operation (user Flash memory only). MER can be programmed only when LOCK is cleared to 0. If BER or SER are both set, a PGSERR is raised. Error is triggered when a mass erase is required and some sectors are protected."]
#[inline(always)]
pub fn set_mer(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "end of operation interrupt control bit Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0."]
#[inline(always)]
pub const fn eopie(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "end of operation interrupt control bit Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0."]
#[inline(always)]
pub fn set_eopie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "write protection error interrupt enable bit When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0."]
#[inline(always)]
pub const fn wrperrie(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "write protection error interrupt enable bit When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0."]
#[inline(always)]
pub fn set_wrperrie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "programming sequence error interrupt enable bit When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0."]
#[inline(always)]
pub const fn pgserrie(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "programming sequence error interrupt enable bit When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0."]
#[inline(always)]
pub fn set_pgserrie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "strobe error interrupt enable bit When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0."]
#[inline(always)]
pub const fn strberrie(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "strobe error interrupt enable bit When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0."]
#[inline(always)]
pub fn set_strberrie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "inconsistency error interrupt enable bit When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0."]
#[inline(always)]
pub const fn incerrie(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "inconsistency error interrupt enable bit When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0."]
#[inline(always)]
pub fn set_incerrie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "Option byte change error interrupt enable bit OPTCHANGEERRIE bit controls if an interrupt has to be generated when an error occurs during an option byte change. This bit can be programmed only when LOCK bit is cleared to 0."]
#[inline(always)]
pub const fn optchangeerrie(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Option byte change error interrupt enable bit OPTCHANGEERRIE bit controls if an interrupt has to be generated when an error occurs during an option byte change. This bit can be programmed only when LOCK bit is cleared to 0."]
#[inline(always)]
pub fn set_optchangeerrie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "Bank selector bit BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored."]
#[inline(always)]
pub const fn bksel(&self) -> super::vals::Bksel {
let val = (self.0 >> 31usize) & 0x01;
super::vals::Bksel::from_bits(val as u8)
}
#[doc = "Bank selector bit BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored."]
#[inline(always)]
pub fn set_bksel(&mut self, val: super::vals::Bksel) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize);
}
}
impl Default for Nscr {
#[inline(always)]
fn default() -> Nscr {
Nscr(0)
}
}
impl core::fmt::Debug for Nscr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Nscr")
.field("lock", &self.lock())
.field("pg", &self.pg())
.field("ser", &self.ser())
.field("ber", &self.ber())
.field("fw", &self.fw())
.field("strt", &self.strt())
.field("snb", &self.snb())
.field("mer", &self.mer())
.field("eopie", &self.eopie())
.field("wrperrie", &self.wrperrie())
.field("pgserrie", &self.pgserrie())
.field("strberrie", &self.strberrie())
.field("incerrie", &self.incerrie())
.field("optchangeerrie", &self.optchangeerrie())
.field("bksel", &self.bksel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Nscr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Nscr {{ lock: {=bool:?}, pg: {=bool:?}, ser: {=bool:?}, ber: {=bool:?}, fw: {=bool:?}, strt: {=bool:?}, snb: {=u8:?}, mer: {=bool:?}, eopie: {=bool:?}, wrperrie: {=bool:?}, pgserrie: {=bool:?}, strberrie: {=bool:?}, incerrie: {=bool:?}, optchangeerrie: {=bool:?}, bksel: {:?} }}" , self . lock () , self . pg () , self . ser () , self . ber () , self . fw () , self . strt () , self . snb () , self . mer () , self . eopie () , self . wrperrie () , self . pgserrie () , self . strberrie () , self . incerrie () , self . optchangeerrie () , self . bksel ())
}
}
#[doc = "FLASH non-secure status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Nssr(pub u32);
impl Nssr {
#[doc = "busy flag BSY flag indicates that a Flash memory is busy by an operation (write, erase, option byte change). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs."]
#[inline(always)]
pub const fn bsy(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "busy flag BSY flag indicates that a Flash memory is busy by an operation (write, erase, option byte change). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs."]
#[inline(always)]
pub fn set_bsy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "write buffer not empty flag WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_NSCR the embedded Flash memory detects an error that involves data loss This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data."]
#[inline(always)]
pub const fn wbne(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "write buffer not empty flag WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_NSCR the embedded Flash memory detects an error that involves data loss This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data."]
#[inline(always)]
pub fn set_wbne(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "data buffer not empty flag DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free."]
#[inline(always)]
pub const fn dbne(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "data buffer not empty flag DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free."]
#[inline(always)]
pub fn set_dbne(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register."]
#[inline(always)]
pub const fn eop(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register."]
#[inline(always)]
pub fn set_eop(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR."]
#[inline(always)]
pub const fn wrperr(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR."]
#[inline(always)]
pub fn set_wrperr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR."]
#[inline(always)]
pub const fn pgserr(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR."]
#[inline(always)]
pub fn set_pgserr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR."]
#[inline(always)]
pub const fn strberr(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR."]
#[inline(always)]
pub fn set_strberr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears INCERR."]
#[inline(always)]
pub const fn incerr(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears INCERR."]
#[inline(always)]
pub fn set_incerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "Option byte change error flag OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1. Writing 1 to CLR_OPTCHANGEERR of register FLASH_CCR clears OPTCHANGEERR. Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set."]
#[inline(always)]
pub const fn optchangeerr(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Option byte change error flag OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1. Writing 1 to CLR_OPTCHANGEERR of register FLASH_CCR clears OPTCHANGEERR. Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set."]
#[inline(always)]
pub fn set_optchangeerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
}
impl Default for Nssr {
#[inline(always)]
fn default() -> Nssr {
Nssr(0)
}
}
impl core::fmt::Debug for Nssr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Nssr")
.field("bsy", &self.bsy())
.field("wbne", &self.wbne())
.field("dbne", &self.dbne())
.field("eop", &self.eop())
.field("wrperr", &self.wrperr())
.field("pgserr", &self.pgserr())
.field("strberr", &self.strberr())
.field("incerr", &self.incerr())
.field("optchangeerr", &self.optchangeerr())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Nssr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Nssr {{ bsy: {=bool:?}, wbne: {=bool:?}, dbne: {=bool:?}, eop: {=bool:?}, wrperr: {=bool:?}, pgserr: {=bool:?}, strberr: {=bool:?}, incerr: {=bool:?}, optchangeerr: {=bool:?} }}" , self . bsy () , self . wbne () , self . dbne () , self . eop () , self . wrperr () , self . pgserr () , self . strberr () , self . incerr () , self . optchangeerr ())
}
}
#[doc = "FLASH operation status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Opsr(pub u32);
impl Opsr {
#[doc = "Interrupted operation address."]
#[inline(always)]
pub const fn addr_op(&self) -> u32 {
let val = (self.0 >> 0usize) & 0x000f_ffff;
val as u32
}
#[doc = "Interrupted operation address."]
#[inline(always)]
pub fn set_addr_op(&mut self, val: u32) {
self.0 = (self.0 & !(0x000f_ffff << 0usize)) | (((val as u32) & 0x000f_ffff) << 0usize);
}
#[doc = "Interrupted operation bank It indicates which bank was concerned by operation."]
#[inline(always)]
pub const fn bk_op(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "Interrupted operation bank It indicates which bank was concerned by operation."]
#[inline(always)]
pub fn set_bk_op(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "Operation in system Flash memory interrupted Indicates that reset interrupted an ongoing operation in System Flash."]
#[inline(always)]
pub const fn sysf_op(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Operation in system Flash memory interrupted Indicates that reset interrupted an ongoing operation in System Flash."]
#[inline(always)]
pub fn set_sysf_op(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "OTP operation interrupted Indicates that reset interrupted an ongoing operation in OTP area."]
#[inline(always)]
pub const fn otp_op(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "OTP operation interrupted Indicates that reset interrupted an ongoing operation in OTP area."]
#[inline(always)]
pub fn set_otp_op(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Flash memory operation code"]
#[inline(always)]
pub const fn code_op(&self) -> super::vals::CodeOp {
let val = (self.0 >> 29usize) & 0x07;
super::vals::CodeOp::from_bits(val as u8)
}
#[doc = "Flash memory operation code"]
#[inline(always)]
pub fn set_code_op(&mut self, val: super::vals::CodeOp) {
self.0 = (self.0 & !(0x07 << 29usize)) | (((val.to_bits() as u32) & 0x07) << 29usize);
}
}
impl Default for Opsr {
#[inline(always)]
fn default() -> Opsr {
Opsr(0)
}
}
impl core::fmt::Debug for Opsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Opsr")
.field("addr_op", &self.addr_op())
.field("bk_op", &self.bk_op())
.field("sysf_op", &self.sysf_op())
.field("otp_op", &self.otp_op())
.field("code_op", &self.code_op())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Opsr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Opsr {{ addr_op: {=u32:?}, bk_op: {=bool:?}, sysf_op: {=bool:?}, otp_op: {=bool:?}, code_op: {:?} }}",
self.addr_op(),
self.bk_op(),
self.sysf_op(),
self.otp_op(),
self.code_op()
)
}
}
#[doc = "FLASH option control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Optcr(pub u32);
impl Optcr {
#[doc = "FLASH_OPTCR lock option configuration bit The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset. It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change."]
#[inline(always)]
pub const fn optlock(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "FLASH_OPTCR lock option configuration bit The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset. It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change."]
#[inline(always)]
pub fn set_optlock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Option byte start change option configuration bit OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It’s set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It’s reseted at the same time as BSY bit. The user application cannot modify any FLASH_XXX_PRG embedded Flash memory register until the option change operation has been completed. Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in non-volatile memory."]
#[inline(always)]
pub const fn optstrt(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Option byte start change option configuration bit OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It’s set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It’s reseted at the same time as BSY bit. The user application cannot modify any FLASH_XXX_PRG embedded Flash memory register until the option change operation has been completed. Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in non-volatile memory."]
#[inline(always)]
pub fn set_optstrt(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Bank swapping option configuration bit SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR."]
#[inline(always)]
pub const fn swap_bank(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Bank swapping option configuration bit SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR."]
#[inline(always)]
pub fn set_swap_bank(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Optcr {
#[inline(always)]
fn default() -> Optcr {
Optcr(0)
}
}
impl core::fmt::Debug for Optcr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Optcr")
.field("optlock", &self.optlock())
.field("optstrt", &self.optstrt())
.field("swap_bank", &self.swap_bank())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Optcr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Optcr {{ optlock: {=bool:?}, optstrt: {=bool:?}, swap_bank: {=bool:?} }}",
self.optlock(),
self.optstrt(),
self.swap_bank()
)
}
}
#[doc = "FLASH option status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Optsr(pub u32);
impl Optsr {
#[doc = "Brownout level option status bit These bits reflects the power level that generates a system reset."]
#[inline(always)]
pub const fn bor_lev(&self) -> super::vals::OptsrBorLev {
let val = (self.0 >> 0usize) & 0x03;
super::vals::OptsrBorLev::from_bits(val as u8)
}
#[doc = "Brownout level option status bit These bits reflects the power level that generates a system reset."]
#[inline(always)]
pub fn set_bor_lev(&mut self, val: super::vals::OptsrBorLev) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "Brownout high enable status bit"]
#[inline(always)]
pub const fn borh_en(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Brownout high enable status bit"]
#[inline(always)]
pub fn set_borh_en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "IWDG control mode option status bit"]
#[inline(always)]
pub const fn iwdg_sw(&self) -> super::vals::OptsrIwdgSw {
let val = (self.0 >> 3usize) & 0x01;
super::vals::OptsrIwdgSw::from_bits(val as u8)
}
#[doc = "IWDG control mode option status bit"]
#[inline(always)]
pub fn set_iwdg_sw(&mut self, val: super::vals::OptsrIwdgSw) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize);
}
#[doc = "WWDG control mode option status bit"]
#[inline(always)]
pub const fn wwdg_sw(&self) -> super::vals::OptsrWwdgSw {
let val = (self.0 >> 4usize) & 0x01;
super::vals::OptsrWwdgSw::from_bits(val as u8)
}
#[doc = "WWDG control mode option status bit"]
#[inline(always)]
pub fn set_wwdg_sw(&mut self, val: super::vals::OptsrWwdgSw) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
}
#[doc = "Core domain Shutdown entry reset option status bit"]
#[inline(always)]
pub const fn nrst_shdw(&self) -> super::vals::OptsrNrstShdw {
let val = (self.0 >> 5usize) & 0x01;
super::vals::OptsrNrstShdw::from_bits(val as u8)
}
#[doc = "Core domain Shutdown entry reset option status bit"]
#[inline(always)]
pub fn set_nrst_shdw(&mut self, val: super::vals::OptsrNrstShdw) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize);
}
#[doc = "Core domain Stop entry reset option status bit"]
#[inline(always)]
pub const fn nrst_stop(&self) -> super::vals::OptsrNrstStop {
let val = (self.0 >> 6usize) & 0x01;
super::vals::OptsrNrstStop::from_bits(val as u8)
}
#[doc = "Core domain Stop entry reset option status bit"]
#[inline(always)]
pub fn set_nrst_stop(&mut self, val: super::vals::OptsrNrstStop) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
}
#[doc = "Core domain Standby entry reset option status bit"]
#[inline(always)]
pub const fn nrst_stdby(&self) -> super::vals::OptsrNrstStdby {
let val = (self.0 >> 7usize) & 0x01;
super::vals::OptsrNrstStdby::from_bits(val as u8)
}
#[doc = "Core domain Standby entry reset option status bit"]
#[inline(always)]
pub fn set_nrst_stdby(&mut self, val: super::vals::OptsrNrstStdby) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
}
#[doc = "Life state code (based on Hamming 8,4)."]
#[inline(always)]
pub const fn product_state(&self) -> super::vals::ProductState {
let val = (self.0 >> 8usize) & 0xff;
super::vals::ProductState::from_bits(val as u8)
}
#[doc = "Life state code (based on Hamming 8,4)."]
#[inline(always)]
pub fn set_product_state(&mut self, val: super::vals::ProductState) {
self.0 = (self.0 & !(0xff << 8usize)) | (((val.to_bits() as u32) & 0xff) << 8usize);
}
#[doc = "High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V."]
#[inline(always)]
pub const fn io_vdd_hslv(&self) -> super::vals::OptsrIoVddHslv {
let val = (self.0 >> 16usize) & 0x01;
super::vals::OptsrIoVddHslv::from_bits(val as u8)
}
#[doc = "High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V."]
#[inline(always)]
pub fn set_io_vdd_hslv(&mut self, val: super::vals::OptsrIoVddHslv) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32) & 0x01) << 16usize);
}
#[doc = "High-speed IO at low VDDIO2 voltage status bit. This bit can be set only with VDDIO2 below 2.5 V."]
#[inline(always)]
pub const fn io_vddio2_hslv(&self) -> super::vals::OptsrIoVddioHslv {
let val = (self.0 >> 17usize) & 0x01;
super::vals::OptsrIoVddioHslv::from_bits(val as u8)
}
#[doc = "High-speed IO at low VDDIO2 voltage status bit. This bit can be set only with VDDIO2 below 2.5 V."]
#[inline(always)]
pub fn set_io_vddio2_hslv(&mut self, val: super::vals::OptsrIoVddioHslv) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize);
}
#[doc = "IWDG Stop mode freeze option status bit When set the independent watchdog IWDG is in system Stop mode."]
#[inline(always)]
pub const fn iwdg_stop(&self) -> super::vals::OptsrIwdgStop {
let val = (self.0 >> 20usize) & 0x01;
super::vals::OptsrIwdgStop::from_bits(val as u8)
}
#[doc = "IWDG Stop mode freeze option status bit When set the independent watchdog IWDG is in system Stop mode."]
#[inline(always)]
pub fn set_iwdg_stop(&mut self, val: super::vals::OptsrIwdgStop) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val.to_bits() as u32) & 0x01) << 20usize);
}
#[doc = "IWDG Standby mode freeze option status bit When set the independent watchdog IWDG is frozen in system Standby mode."]
#[inline(always)]
pub const fn iwdg_stdby(&self) -> super::vals::OptsrIwdgStdby {
let val = (self.0 >> 21usize) & 0x01;
super::vals::OptsrIwdgStdby::from_bits(val as u8)
}
#[doc = "IWDG Standby mode freeze option status bit When set the independent watchdog IWDG is frozen in system Standby mode."]
#[inline(always)]
pub fn set_iwdg_stdby(&mut self, val: super::vals::OptsrIwdgStdby) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val.to_bits() as u32) & 0x01) << 21usize);
}
#[doc = "Bank swapping option status bit SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset."]
#[inline(always)]
pub const fn swap_bank(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Bank swapping option status bit SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not. SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset."]
#[inline(always)]
pub fn set_swap_bank(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Optsr {
#[inline(always)]
fn default() -> Optsr {
Optsr(0)
}
}
impl core::fmt::Debug for Optsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Optsr")
.field("bor_lev", &self.bor_lev())
.field("borh_en", &self.borh_en())
.field("iwdg_sw", &self.iwdg_sw())
.field("wwdg_sw", &self.wwdg_sw())
.field("nrst_shdw", &self.nrst_shdw())
.field("nrst_stop", &self.nrst_stop())
.field("nrst_stdby", &self.nrst_stdby())
.field("product_state", &self.product_state())
.field("io_vdd_hslv", &self.io_vdd_hslv())
.field("io_vddio2_hslv", &self.io_vddio2_hslv())
.field("iwdg_stop", &self.iwdg_stop())
.field("iwdg_stdby", &self.iwdg_stdby())
.field("swap_bank", &self.swap_bank())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Optsr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Optsr {{ bor_lev: {:?}, borh_en: {=bool:?}, iwdg_sw: {:?}, wwdg_sw: {:?}, nrst_shdw: {:?}, nrst_stop: {:?}, nrst_stdby: {:?}, product_state: {:?}, io_vdd_hslv: {:?}, io_vddio2_hslv: {:?}, iwdg_stop: {:?}, iwdg_stdby: {:?}, swap_bank: {=bool:?} }}" , self . bor_lev () , self . borh_en () , self . iwdg_sw () , self . wwdg_sw () , self . nrst_shdw () , self . nrst_stop () , self . nrst_stdby () , self . product_state () , self . io_vdd_hslv () , self . io_vddio2_hslv () , self . iwdg_stop () , self . iwdg_stdby () , self . swap_bank ())
}
}
#[doc = "FLASH option status register 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Optsr2(pub u32);
impl Optsr2 {
#[doc = "SRAM2 erase when system reset"]
#[inline(always)]
pub const fn sram2_rst(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "SRAM2 erase when system reset"]
#[inline(always)]
pub fn set_sram2_rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "Backup RAM ECC detection and correction disable"]
#[inline(always)]
pub const fn bkpram_ecc(&self) -> super::vals::OptsrBkpramEcc {
let val = (self.0 >> 4usize) & 0x01;
super::vals::OptsrBkpramEcc::from_bits(val as u8)
}
#[doc = "Backup RAM ECC detection and correction disable"]
#[inline(always)]
pub fn set_bkpram_ecc(&mut self, val: super::vals::OptsrBkpramEcc) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
}
#[doc = "SRAM2 ECC detection and correction disable"]
#[inline(always)]
pub const fn sram2_ecc(&self) -> super::vals::OptsrSramEcc {
let val = (self.0 >> 6usize) & 0x01;
super::vals::OptsrSramEcc::from_bits(val as u8)
}
#[doc = "SRAM2 ECC detection and correction disable"]
#[inline(always)]
pub fn set_sram2_ecc(&mut self, val: super::vals::OptsrSramEcc) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
}
#[doc = "SRAM1 erase upon system reset"]
#[inline(always)]
pub const fn sram1_rst(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "SRAM1 erase upon system reset"]
#[inline(always)]
pub fn set_sram1_rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "SRAM1 ECC detection and correction disable"]
#[inline(always)]
pub const fn sram1_ecc(&self) -> super::vals::OptsrSramEcc {
let val = (self.0 >> 10usize) & 0x01;
super::vals::OptsrSramEcc::from_bits(val as u8)
}
#[doc = "SRAM1 ECC detection and correction disable"]
#[inline(always)]
pub fn set_sram1_ecc(&mut self, val: super::vals::OptsrSramEcc) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize);
}
}
impl Default for Optsr2 {
#[inline(always)]
fn default() -> Optsr2 {
Optsr2(0)
}
}
impl core::fmt::Debug for Optsr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Optsr2")
.field("sram2_rst", &self.sram2_rst())
.field("bkpram_ecc", &self.bkpram_ecc())
.field("sram2_ecc", &self.sram2_ecc())
.field("sram1_rst", &self.sram1_rst())
.field("sram1_ecc", &self.sram1_ecc())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Optsr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Optsr2 {{ sram2_rst: {=bool:?}, bkpram_ecc: {:?}, sram2_ecc: {:?}, sram1_rst: {=bool:?}, sram1_ecc: {:?} }}" , self . sram2_rst () , self . bkpram_ecc () , self . sram2_ecc () , self . sram1_rst () , self . sram1_ecc ())
}
}
#[doc = "FLASH non-secure OTP block lock"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Otpblr(pub u32);
impl Otpblr {
#[doc = "OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL\\[n\\]
= 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL\\[n\\]
= 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it is not possible to remove the write protection. LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared."]
#[inline(always)]
pub const fn lockbl(&self) -> u32 {
let val = (self.0 >> 0usize) & 0xffff_ffff;
val as u32
}
#[doc = "OTP block lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL\\[n\\]
= 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR. LOCKBL\\[n\\]
= 0 indicates that all OTP 16-bit words in OTP Block n are not locked. When one block is locked, it is not possible to remove the write protection. LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared."]
#[inline(always)]
pub fn set_lockbl(&mut self, val: u32) {
self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
}
}
impl Default for Otpblr {
#[inline(always)]
fn default() -> Otpblr {
Otpblr(0)
}
}
impl core::fmt::Debug for Otpblr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Otpblr").field("lockbl", &self.lockbl()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Otpblr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Otpblr {{ lockbl: {=u32:?} }}", self.lockbl())
}
}
#[doc = "FLASH privilege register for bank 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Privbb(pub u32);
impl Privbb {
#[doc = "Privileged / unprivileged 8 Kbytes Flash Bank1 sector attribute (y = 0 to 7)"]
#[inline(always)]
pub const fn privbb(&self) -> super::vals::Privbb {
let val = (self.0 >> 0usize) & 0xff;
super::vals::Privbb::from_bits(val as u8)
}
#[doc = "Privileged / unprivileged 8 Kbytes Flash Bank1 sector attribute (y = 0 to 7)"]
#[inline(always)]
pub fn set_privbb(&mut self, val: super::vals::Privbb) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize);
}
}
impl Default for Privbb {
#[inline(always)]
fn default() -> Privbb {
Privbb(0)
}
}
impl core::fmt::Debug for Privbb {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Privbb").field("privbb", &self.privbb()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Privbb {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Privbb {{ privbb: {:?} }}", self.privbb())
}
}
#[doc = "FLASH privilege configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Privcfgr(pub u32);
impl Privcfgr {
#[doc = "privilege attribute for non secure registers"]
#[inline(always)]
pub const fn nspriv(&self) -> super::vals::Nspriv {
let val = (self.0 >> 1usize) & 0x01;
super::vals::Nspriv::from_bits(val as u8)
}
#[doc = "privilege attribute for non secure registers"]
#[inline(always)]
pub fn set_nspriv(&mut self, val: super::vals::Nspriv) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize);
}
}
impl Default for Privcfgr {
#[inline(always)]
fn default() -> Privcfgr {
Privcfgr(0)
}
}
impl core::fmt::Debug for Privcfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Privcfgr").field("nspriv", &self.nspriv()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Privcfgr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Privcfgr {{ nspriv: {:?} }}", self.nspriv())
}
}
#[doc = "FLASH secure status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Secsr(pub u32);
impl Secsr {
#[doc = "busy flag BSY flag indicates that a FLASH memory is busy by an operation (write, erase, option byte change, OBK operations, PUF operation). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs."]
#[inline(always)]
pub const fn secbsy(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "busy flag BSY flag indicates that a FLASH memory is busy by an operation (write, erase, option byte change, OBK operations, PUF operation). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs."]
#[inline(always)]
pub fn set_secbsy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "write buffer not empty flag WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_SECCR the embedded Flash memory detects an error that involves data loss This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data."]
#[inline(always)]
pub const fn secwbne(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "write buffer not empty flag WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_SECCR the embedded Flash memory detects an error that involves data loss This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data."]
#[inline(always)]
pub fn set_secwbne(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "data buffer not empty flag DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free."]
#[inline(always)]
pub const fn secdbne(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "data buffer not empty flag DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free."]
#[inline(always)]
pub fn set_secdbne(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register."]
#[inline(always)]
pub const fn seceop(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register."]
#[inline(always)]
pub fn set_seceop(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR."]
#[inline(always)]
pub const fn secwrperr(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR."]
#[inline(always)]
pub fn set_secwrperr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR."]
#[inline(always)]
pub const fn secpgserr(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR."]
#[inline(always)]
pub fn set_secpgserr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR."]
#[inline(always)]
pub const fn secstrberr(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR."]
#[inline(always)]
pub fn set_secstrberr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR."]
#[inline(always)]
pub const fn secincerr(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR."]
#[inline(always)]
pub fn set_secincerr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Secsr {
#[inline(always)]
fn default() -> Secsr {
Secsr(0)
}
}
impl core::fmt::Debug for Secsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Secsr")
.field("secbsy", &self.secbsy())
.field("secwbne", &self.secwbne())
.field("secdbne", &self.secdbne())
.field("seceop", &self.seceop())
.field("secwrperr", &self.secwrperr())
.field("secpgserr", &self.secpgserr())
.field("secstrberr", &self.secstrberr())
.field("secincerr", &self.secincerr())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Secsr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Secsr {{ secbsy: {=bool:?}, secwbne: {=bool:?}, secdbne: {=bool:?}, seceop: {=bool:?}, secwrperr: {=bool:?}, secpgserr: {=bool:?}, secstrberr: {=bool:?}, secincerr: {=bool:?} }}" , self . secbsy () , self . secwbne () , self . secdbne () , self . seceop () , self . secwrperr () , self . secpgserr () , self . secstrberr () , self . secincerr ())
}
}
#[doc = "FLASH write sector protection for Bank2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Wrp(pub u32);
impl Wrp {
#[doc = "Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected)"]
#[inline(always)]
pub const fn wrpsg(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[doc = "Bank2 sector protection option status byte Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected)"]
#[inline(always)]
pub fn set_wrpsg(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
}
impl Default for Wrp {
#[inline(always)]
fn default() -> Wrp {
Wrp(0)
}
}
impl core::fmt::Debug for Wrp {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wrp").field("wrpsg", &self.wrpsg()).finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Wrp {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Wrp {{ wrpsg: {=u8:?} }}", self.wrpsg())
}
}
}
pub mod vals {
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Bksel {
#[doc = "Bank1 is selected for Bank erase / sector erase / interrupt enable"]
BANK1 = 0x0,
#[doc = "Bank1 is selected for Bank erase / sector erase / interrupt enable"]
BANK2 = 0x01,
}
impl Bksel {
#[inline(always)]
pub const fn from_bits(val: u8) -> Bksel {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Bksel {
#[inline(always)]
fn from(val: u8) -> Bksel {
Bksel::from_bits(val)
}
}
impl From<Bksel> for u8 {
#[inline(always)]
fn from(val: Bksel) -> u8 {
Bksel::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum CodeOp {
#[doc = "No Flash operation on going during previous reset"]
B_0X0 = 0x0,
#[doc = "Single write operation interrupted"]
B_0X1 = 0x01,
_RESERVED_2 = 0x02,
#[doc = "Sector erase operation interrupted"]
B_0X3 = 0x03,
#[doc = "Bank erase operation interrupted"]
B_0X4 = 0x04,
#[doc = "Mass erase operation interrupted"]
B_0X5 = 0x05,
#[doc = "Option change operation interrupted"]
B_0X6 = 0x06,
_RESERVED_7 = 0x07,
}
impl CodeOp {
#[inline(always)]
pub const fn from_bits(val: u8) -> CodeOp {
unsafe { core::mem::transmute(val & 0x07) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for CodeOp {
#[inline(always)]
fn from(val: u8) -> CodeOp {
CodeOp::from_bits(val)
}
}
impl From<CodeOp> for u8 {
#[inline(always)]
fn from(val: CodeOp) -> u8 {
CodeOp::to_bits(val)
}
}
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
pub struct NsbootrNsbootLock(u8);
impl NsbootrNsbootLock {
#[doc = "The NSBOOTADD and SWAP_BANK are frozen."]
pub const B_0X_B4: Self = Self(0xb4);
#[doc = "The SWAP_BANK and NSBOOTADD can still be modified following their individual rules."]
pub const B_0X_C3: Self = Self(0xc3);
}
impl NsbootrNsbootLock {
pub const fn from_bits(val: u8) -> NsbootrNsbootLock {
Self(val & 0xff)
}
pub const fn to_bits(self) -> u8 {
self.0
}
}
impl core::fmt::Debug for NsbootrNsbootLock {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
match self.0 {
0xb4 => f.write_str("B_0X_B4"),
0xc3 => f.write_str("B_0X_C3"),
other => core::write!(f, "0x{:02X}", other),
}
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for NsbootrNsbootLock {
fn format(&self, f: defmt::Formatter) {
match self.0 {
0xb4 => defmt::write!(f, "B_0X_B4"),
0xc3 => defmt::write!(f, "B_0X_C3"),
other => defmt::write!(f, "0x{:02X}", other),
}
}
}
impl From<u8> for NsbootrNsbootLock {
#[inline(always)]
fn from(val: u8) -> NsbootrNsbootLock {
NsbootrNsbootLock::from_bits(val)
}
}
impl From<NsbootrNsbootLock> for u8 {
#[inline(always)]
fn from(val: NsbootrNsbootLock) -> u8 {
NsbootrNsbootLock::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Nspriv {
#[doc = "access to non secure registers is always granted"]
B_0X0 = 0x0,
#[doc = "access to non secure registers is denied in case of non privileged access."]
B_0X1 = 0x01,
}
impl Nspriv {
#[inline(always)]
pub const fn from_bits(val: u8) -> Nspriv {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Nspriv {
#[inline(always)]
fn from(val: u8) -> Nspriv {
Nspriv::from_bits(val)
}
}
impl From<Nspriv> for u8 {
#[inline(always)]
fn from(val: Nspriv) -> u8 {
Nspriv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrBkpramEcc {
#[doc = "BKPRAM ECC check enabled"]
B_0X0 = 0x0,
#[doc = "BKPRAM ECC check disabled"]
B_0X1 = 0x01,
}
impl OptsrBkpramEcc {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrBkpramEcc {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrBkpramEcc {
#[inline(always)]
fn from(val: u8) -> OptsrBkpramEcc {
OptsrBkpramEcc::from_bits(val)
}
}
impl From<OptsrBkpramEcc> for u8 {
#[inline(always)]
fn from(val: OptsrBkpramEcc) -> u8 {
OptsrBkpramEcc::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrBorLev {
#[doc = "BOR OFF, POR/PDR reset threshold level is applied"]
B_0X0 = 0x0,
#[doc = "BOR Level 1, the threshold level is low (around 2.1 V)"]
B_0X1 = 0x01,
#[doc = "BOR Level 2, the threshold level is medium (around 2.4 V)"]
B_0X2 = 0x02,
#[doc = "BOR Level 3, the threshold level is high (around 2.7 V)"]
B_0X3 = 0x03,
}
impl OptsrBorLev {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrBorLev {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrBorLev {
#[inline(always)]
fn from(val: u8) -> OptsrBorLev {
OptsrBorLev::from_bits(val)
}
}
impl From<OptsrBorLev> for u8 {
#[inline(always)]
fn from(val: OptsrBorLev) -> u8 {
OptsrBorLev::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrIoVddHslv {
#[doc = "High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)"]
B_0X0 = 0x0,
#[doc = "High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)"]
B_0X1 = 0x01,
}
impl OptsrIoVddHslv {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrIoVddHslv {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrIoVddHslv {
#[inline(always)]
fn from(val: u8) -> OptsrIoVddHslv {
OptsrIoVddHslv::from_bits(val)
}
}
impl From<OptsrIoVddHslv> for u8 {
#[inline(always)]
fn from(val: OptsrIoVddHslv) -> u8 {
OptsrIoVddHslv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrIoVddioHslv {
#[doc = "High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)"]
B_0X0 = 0x0,
#[doc = "High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)"]
B_0X1 = 0x01,
}
impl OptsrIoVddioHslv {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrIoVddioHslv {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrIoVddioHslv {
#[inline(always)]
fn from(val: u8) -> OptsrIoVddioHslv {
OptsrIoVddioHslv::from_bits(val)
}
}
impl From<OptsrIoVddioHslv> for u8 {
#[inline(always)]
fn from(val: OptsrIoVddioHslv) -> u8 {
OptsrIoVddioHslv::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrIwdgStdby {
#[doc = "Independent watchdog frozen in Standby mode"]
B_0X0 = 0x0,
#[doc = "Independent watchdog keep running in Standby mode."]
B_0X1 = 0x01,
}
impl OptsrIwdgStdby {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrIwdgStdby {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrIwdgStdby {
#[inline(always)]
fn from(val: u8) -> OptsrIwdgStdby {
OptsrIwdgStdby::from_bits(val)
}
}
impl From<OptsrIwdgStdby> for u8 {
#[inline(always)]
fn from(val: OptsrIwdgStdby) -> u8 {
OptsrIwdgStdby::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrIwdgStop {
#[doc = "Independent watchdog frozen in system Stop mode"]
B_0X0 = 0x0,
#[doc = "Independent watchdog keep running in system Stop mode."]
B_0X1 = 0x01,
}
impl OptsrIwdgStop {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrIwdgStop {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrIwdgStop {
#[inline(always)]
fn from(val: u8) -> OptsrIwdgStop {
OptsrIwdgStop::from_bits(val)
}
}
impl From<OptsrIwdgStop> for u8 {
#[inline(always)]
fn from(val: OptsrIwdgStop) -> u8 {
OptsrIwdgStop::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrIwdgSw {
#[doc = "IWDG watchdog is controlled by hardware"]
B_0X0 = 0x0,
#[doc = "IWDG watchdog is controlled by software"]
B_0X1 = 0x01,
}
impl OptsrIwdgSw {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrIwdgSw {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrIwdgSw {
#[inline(always)]
fn from(val: u8) -> OptsrIwdgSw {
OptsrIwdgSw::from_bits(val)
}
}
impl From<OptsrIwdgSw> for u8 {
#[inline(always)]
fn from(val: OptsrIwdgSw) -> u8 {
OptsrIwdgSw::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrNrstShdw {
#[doc = "a reset is generated when entering Shutdown mode on core domain"]
B_0X0 = 0x0,
#[doc = "no reset generated when entering Shutdown mode on core domain."]
B_0X1 = 0x01,
}
impl OptsrNrstShdw {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrNrstShdw {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrNrstShdw {
#[inline(always)]
fn from(val: u8) -> OptsrNrstShdw {
OptsrNrstShdw::from_bits(val)
}
}
impl From<OptsrNrstShdw> for u8 {
#[inline(always)]
fn from(val: OptsrNrstShdw) -> u8 {
OptsrNrstShdw::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrNrstStdby {
#[doc = "a reset is generated when entering Standby mode on core domain"]
B_0X0 = 0x0,
#[doc = "no reset generated when entering Standby mode on core domain."]
B_0X1 = 0x01,
}
impl OptsrNrstStdby {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrNrstStdby {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrNrstStdby {
#[inline(always)]
fn from(val: u8) -> OptsrNrstStdby {
OptsrNrstStdby::from_bits(val)
}
}
impl From<OptsrNrstStdby> for u8 {
#[inline(always)]
fn from(val: OptsrNrstStdby) -> u8 {
OptsrNrstStdby::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrNrstStop {
#[doc = "a reset is generated when entering Stop mode on core domain"]
B_0X0 = 0x0,
#[doc = "no reset generated when entering Stop mode on core domain."]
B_0X1 = 0x01,
}
impl OptsrNrstStop {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrNrstStop {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrNrstStop {
#[inline(always)]
fn from(val: u8) -> OptsrNrstStop {
OptsrNrstStop::from_bits(val)
}
}
impl From<OptsrNrstStop> for u8 {
#[inline(always)]
fn from(val: OptsrNrstStop) -> u8 {
OptsrNrstStop::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrSramEcc {
#[doc = "SRAM2 ECC check enabled"]
B_0X0 = 0x0,
#[doc = "SRAM2 ECC check disabled"]
B_0X1 = 0x01,
}
impl OptsrSramEcc {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrSramEcc {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrSramEcc {
#[inline(always)]
fn from(val: u8) -> OptsrSramEcc {
OptsrSramEcc::from_bits(val)
}
}
impl From<OptsrSramEcc> for u8 {
#[inline(always)]
fn from(val: OptsrSramEcc) -> u8 {
OptsrSramEcc::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum OptsrWwdgSw {
#[doc = "WWDG watchdog is controlled by hardware"]
B_0X0 = 0x0,
#[doc = "WWDG watchdog is controlled by software"]
B_0X1 = 0x01,
}
impl OptsrWwdgSw {
#[inline(always)]
pub const fn from_bits(val: u8) -> OptsrWwdgSw {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for OptsrWwdgSw {
#[inline(always)]
fn from(val: u8) -> OptsrWwdgSw {
OptsrWwdgSw::from_bits(val)
}
}
impl From<OptsrWwdgSw> for u8 {
#[inline(always)]
fn from(val: OptsrWwdgSw) -> u8 {
OptsrWwdgSw::to_bits(val)
}
}
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
pub struct Privbb(u8);
impl Privbb {
#[doc = "sectors y in bank 1 is non privileged"]
pub const B_0X0: Self = Self(0x0);
#[doc = "sector y in bank 1 is privileged"]
pub const B_0X1: Self = Self(0x01);
}
impl Privbb {
pub const fn from_bits(val: u8) -> Privbb {
Self(val & 0xff)
}
pub const fn to_bits(self) -> u8 {
self.0
}
}
impl core::fmt::Debug for Privbb {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
match self.0 {
0x0 => f.write_str("B_0X0"),
0x01 => f.write_str("B_0X1"),
other => core::write!(f, "0x{:02X}", other),
}
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Privbb {
fn format(&self, f: defmt::Formatter) {
match self.0 {
0x0 => defmt::write!(f, "B_0X0"),
0x01 => defmt::write!(f, "B_0X1"),
other => defmt::write!(f, "0x{:02X}", other),
}
}
}
impl From<u8> for Privbb {
#[inline(always)]
fn from(val: u8) -> Privbb {
Privbb::from_bits(val)
}
}
impl From<Privbb> for u8 {
#[inline(always)]
fn from(val: Privbb) -> u8 {
Privbb::to_bits(val)
}
}
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
pub struct ProductState(u8);
impl ProductState {
#[doc = "Provisioning"]
pub const PROVISIONING: Self = Self(0x17);
#[doc = "iROT-Provisioned"]
pub const IROT_PROVISIONED: Self = Self(0x2e);
#[doc = "Locked"]
pub const LOCKED: Self = Self(0x5c);
#[doc = "Closed"]
pub const CLOSED: Self = Self(0x72);
#[doc = "Regression"]
pub const REGRESSION: Self = Self(0x9a);
#[doc = "Open"]
pub const OPEN: Self = Self(0xed);
}
impl ProductState {
pub const fn from_bits(val: u8) -> ProductState {
Self(val & 0xff)
}
pub const fn to_bits(self) -> u8 {
self.0
}
}
impl core::fmt::Debug for ProductState {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
match self.0 {
0x17 => f.write_str("PROVISIONING"),
0x2e => f.write_str("IROT_PROVISIONED"),
0x5c => f.write_str("LOCKED"),
0x72 => f.write_str("CLOSED"),
0x9a => f.write_str("REGRESSION"),
0xed => f.write_str("OPEN"),
other => core::write!(f, "0x{:02X}", other),
}
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for ProductState {
fn format(&self, f: defmt::Formatter) {
match self.0 {
0x17 => defmt::write!(f, "PROVISIONING"),
0x2e => defmt::write!(f, "IROT_PROVISIONED"),
0x5c => defmt::write!(f, "LOCKED"),
0x72 => defmt::write!(f, "CLOSED"),
0x9a => defmt::write!(f, "REGRESSION"),
0xed => defmt::write!(f, "OPEN"),
other => defmt::write!(f, "0x{:02X}", other),
}
}
}
impl From<u8> for ProductState {
#[inline(always)]
fn from(val: u8) -> ProductState {
ProductState::from_bits(val)
}
}
impl From<ProductState> for u8 {
#[inline(always)]
fn from(val: ProductState) -> u8 {
ProductState::to_bits(val)
}
}
}