rigless 0.0.5

// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `SAI1` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `ACR1` at offset `0x4`, resets to `0x0000_0040`, read-write.
    Acr1 = 0,
    /// `ACR2` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Acr2 = 1,
    /// `AFRCR` at offset `0xC`, resets to `0x0000_0007`, read-write.
    Afrcr = 2,
    /// `ASLOTR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Aslotr = 3,
    /// `AIM` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Aim = 4,
    /// `ASR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Asr = 5,
    /// `ACLRFR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Aclrfr = 6,
    /// `ADR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Adr = 7,
    /// `BCR1` at offset `0x24`, resets to `0x0000_0040`, read-write.
    Bcr1 = 8,
    /// `BCR2` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Bcr2 = 9,
    /// `BFRCR` at offset `0x2C`, resets to `0x0000_0007`, read-write.
    Bfrcr = 10,
    /// `BSLOTR` at offset `0x30`, resets to `0x0000_0000`, read-write.
    Bslotr = 11,
    /// `BIM` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Bim = 12,
    /// `BSR` at offset `0x38`, resets to `0x0000_0000`, read-only.
    Bsr = 13,
    /// `BCLRFR` at offset `0x3C`, resets to `0x0000_0000`, write-only.
    Bclrfr = 14,
    /// `BDR` at offset `0x40`, resets to `0x0000_0000`, read-write.
    Bdr = 15,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 16] = [Self::Acr1, Self::Acr2, Self::Afrcr, Self::Aslotr, Self::Aim, Self::Asr, Self::Aclrfr, Self::Adr, Self::Bcr1, Self::Bcr2, Self::Bfrcr, Self::Bslotr, Self::Bim, Self::Bsr, Self::Bclrfr, Self::Bdr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `ACR1`.
pub mod acr1 {
    use super::FieldSpec;
    /// `MODE`, bits 0..=1.
    pub const MODE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `PRTCFG`, bits 2..=3.
    pub const PRTCFG: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `DS`, bits 5..=7.
    pub const DS: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `LSBFIRST`, bit 8.
    pub const LSBFIRST: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `CKSTR`, bit 9.
    pub const CKSTR: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `SYNCEN`, bits 10..=11.
    pub const SYNCEN: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `MONO`, bit 12.
    pub const MONO: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `OutDri`, bit 13.
    pub const OUTDRI: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `SAIAEN`, bit 16.
    pub const SAIAEN: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `DMAEN`, bit 17.
    pub const DMAEN: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `NODIV`, bit 19.
    pub const NODIV: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `MCJDIV`, bits 20..=23.
    pub const MCJDIV: &FieldSpec = &super::REGISTERS[0].fields[11];
}

/// The fields of `ACR2`.
pub mod acr2 {
    use super::FieldSpec;
    /// `FTH`, bits 0..=2.
    pub const FTH: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `FFLUS`, bit 3.
    pub const FFLUS: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `TRIS`, bit 4.
    pub const TRIS: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `MUTE`, bit 5.
    pub const MUTE: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `MUTEVAL`, bit 6.
    pub const MUTEVAL: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `MUTECN`, bits 7..=12.
    pub const MUTECN: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `CPL`, bit 13.
    pub const CPL: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `COMP`, bits 14..=15.
    pub const COMP: &FieldSpec = &super::REGISTERS[1].fields[7];
}

/// The fields of `AFRCR`.
pub mod afrcr {
    use super::FieldSpec;
    /// `FRL`, bits 0..=7.
    pub const FRL: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `FSALL`, bits 8..=14.
    pub const FSALL: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `FSDEF`, bit 16.
    pub const FSDEF: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `FSPOL`, bit 17.
    pub const FSPOL: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `FSOFF`, bit 18.
    pub const FSOFF: &FieldSpec = &super::REGISTERS[2].fields[4];
}

/// The fields of `ASLOTR`.
pub mod aslotr {
    use super::FieldSpec;
    /// `FBOFF`, bits 0..=4.
    pub const FBOFF: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `SLOTSZ`, bits 6..=7.
    pub const SLOTSZ: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `NBSLOT`, bits 8..=11.
    pub const NBSLOT: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `SLOTEN`, bits 16..=31.
    pub const SLOTEN: &FieldSpec = &super::REGISTERS[3].fields[3];
}

/// The fields of `AIM`.
pub mod aim {
    use super::FieldSpec;
    /// `OVRUDRIE`, bit 0.
    pub const OVRUDRIE: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `MUTEDET`, bit 1.
    pub const MUTEDET: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `WCKCFG`, bit 2.
    pub const WCKCFG: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `FREQIE`, bit 3.
    pub const FREQIE: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `CNRDYIE`, bit 4.
    pub const CNRDYIE: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `AFSDETIE`, bit 5.
    pub const AFSDETIE: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `LFSDET`, bit 6.
    pub const LFSDET: &FieldSpec = &super::REGISTERS[4].fields[6];
}

/// The fields of `ASR`.
pub mod asr {
    use super::FieldSpec;
    /// `OVRUDR`, bit 0.
    pub const OVRUDR: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `MUTEDET`, bit 1.
    pub const MUTEDET: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `WCKCFG`, bit 2.
    pub const WCKCFG: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `FREQ`, bit 3.
    pub const FREQ: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `CNRDY`, bit 4.
    pub const CNRDY: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `AFSDET`, bit 5.
    pub const AFSDET: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `LFSDET`, bit 6.
    pub const LFSDET: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `FLVL`, bits 16..=18.
    pub const FLVL: &FieldSpec = &super::REGISTERS[5].fields[7];
}

/// The fields of `ACLRFR`.
pub mod aclrfr {
    use super::FieldSpec;
    /// `OVRUDR`, bit 0.
    pub const OVRUDR: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `MUTEDET`, bit 1.
    pub const MUTEDET: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `WCKCFG`, bit 2.
    pub const WCKCFG: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `CNRDY`, bit 4.
    pub const CNRDY: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `CAFSDET`, bit 5.
    pub const CAFSDET: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `LFSDET`, bit 6.
    pub const LFSDET: &FieldSpec = &super::REGISTERS[6].fields[5];
}

/// The fields of `ADR`.
pub mod adr {
    use super::FieldSpec;
    /// `DATA`, bits 0..=31.
    pub const DATA: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `BCR1`.
pub mod bcr1 {
    use super::FieldSpec;
    /// `MODE`, bits 0..=1.
    pub const MODE: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `PRTCFG`, bits 2..=3.
    pub const PRTCFG: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `DS`, bits 5..=7.
    pub const DS: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `LSBFIRST`, bit 8.
    pub const LSBFIRST: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `CKSTR`, bit 9.
    pub const CKSTR: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `SYNCEN`, bits 10..=11.
    pub const SYNCEN: &FieldSpec = &super::REGISTERS[8].fields[5];
    /// `MONO`, bit 12.
    pub const MONO: &FieldSpec = &super::REGISTERS[8].fields[6];
    /// `OutDri`, bit 13.
    pub const OUTDRI: &FieldSpec = &super::REGISTERS[8].fields[7];
    /// `SAIBEN`, bit 16.
    pub const SAIBEN: &FieldSpec = &super::REGISTERS[8].fields[8];
    /// `DMAEN`, bit 17.
    pub const DMAEN: &FieldSpec = &super::REGISTERS[8].fields[9];
    /// `NODIV`, bit 19.
    pub const NODIV: &FieldSpec = &super::REGISTERS[8].fields[10];
    /// `MCJDIV`, bits 20..=23.
    pub const MCJDIV: &FieldSpec = &super::REGISTERS[8].fields[11];
}

/// The fields of `BCR2`.
pub mod bcr2 {
    use super::FieldSpec;
    /// `FTH`, bits 0..=2.
    pub const FTH: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `FFLUS`, bit 3.
    pub const FFLUS: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `TRIS`, bit 4.
    pub const TRIS: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `MUTE`, bit 5.
    pub const MUTE: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `MUTEVAL`, bit 6.
    pub const MUTEVAL: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `MUTECN`, bits 7..=12.
    pub const MUTECN: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `CPL`, bit 13.
    pub const CPL: &FieldSpec = &super::REGISTERS[9].fields[6];
    /// `COMP`, bits 14..=15.
    pub const COMP: &FieldSpec = &super::REGISTERS[9].fields[7];
}

/// The fields of `BFRCR`.
pub mod bfrcr {
    use super::FieldSpec;
    /// `FRL`, bits 0..=7.
    pub const FRL: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `FSALL`, bits 8..=14.
    pub const FSALL: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `FSDEF`, bit 16.
    pub const FSDEF: &FieldSpec = &super::REGISTERS[10].fields[2];
    /// `FSPOL`, bit 17.
    pub const FSPOL: &FieldSpec = &super::REGISTERS[10].fields[3];
    /// `FSOFF`, bit 18.
    pub const FSOFF: &FieldSpec = &super::REGISTERS[10].fields[4];
}

/// The fields of `BSLOTR`.
pub mod bslotr {
    use super::FieldSpec;
    /// `FBOFF`, bits 0..=4.
    pub const FBOFF: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `SLOTSZ`, bits 6..=7.
    pub const SLOTSZ: &FieldSpec = &super::REGISTERS[11].fields[1];
    /// `NBSLOT`, bits 8..=11.
    pub const NBSLOT: &FieldSpec = &super::REGISTERS[11].fields[2];
    /// `SLOTEN`, bits 16..=31.
    pub const SLOTEN: &FieldSpec = &super::REGISTERS[11].fields[3];
}

/// The fields of `BIM`.
pub mod bim {
    use super::FieldSpec;
    /// `OVRUDRIE`, bit 0.
    pub const OVRUDRIE: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `MUTEDET`, bit 1.
    pub const MUTEDET: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `WCKCFG`, bit 2.
    pub const WCKCFG: &FieldSpec = &super::REGISTERS[12].fields[2];
    /// `FREQIE`, bit 3.
    pub const FREQIE: &FieldSpec = &super::REGISTERS[12].fields[3];
    /// `CNRDYIE`, bit 4.
    pub const CNRDYIE: &FieldSpec = &super::REGISTERS[12].fields[4];
    /// `AFSDETIE`, bit 5.
    pub const AFSDETIE: &FieldSpec = &super::REGISTERS[12].fields[5];
    /// `LFSDETIE`, bit 6.
    pub const LFSDETIE: &FieldSpec = &super::REGISTERS[12].fields[6];
}

/// The fields of `BSR`.
pub mod bsr {
    use super::FieldSpec;
    /// `OVRUDR`, bit 0.
    pub const OVRUDR: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `MUTEDET`, bit 1.
    pub const MUTEDET: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `WCKCFG`, bit 2.
    pub const WCKCFG: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `FREQ`, bit 3.
    pub const FREQ: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `CNRDY`, bit 4.
    pub const CNRDY: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `AFSDET`, bit 5.
    pub const AFSDET: &FieldSpec = &super::REGISTERS[13].fields[5];
    /// `LFSDET`, bit 6.
    pub const LFSDET: &FieldSpec = &super::REGISTERS[13].fields[6];
    /// `FLVL`, bits 16..=18.
    pub const FLVL: &FieldSpec = &super::REGISTERS[13].fields[7];
}

/// The fields of `BCLRFR`.
pub mod bclrfr {
    use super::FieldSpec;
    /// `OVRUDR`, bit 0.
    pub const OVRUDR: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `MUTEDET`, bit 1.
    pub const MUTEDET: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `WCKCFG`, bit 2.
    pub const WCKCFG: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `CNRDY`, bit 4.
    pub const CNRDY: &FieldSpec = &super::REGISTERS[14].fields[3];
    /// `CAFSDET`, bit 5.
    pub const CAFSDET: &FieldSpec = &super::REGISTERS[14].fields[4];
    /// `LFSDET`, bit 6.
    pub const LFSDET: &FieldSpec = &super::REGISTERS[14].fields[5];
}

/// The fields of `BDR`.
pub mod bdr {
    use super::FieldSpec;
    /// `DATA`, bits 0..=31.
    pub const DATA: &FieldSpec = &super::REGISTERS[15].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 16] = [
    RegisterSpec { name: "ACR1", offset: 0x4, width: Width::W32, reset: 0x0000_0040, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MODE", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRTCFG", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DS", bit: 5, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSBFIRST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKSTR", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCEN", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MONO", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OutDri", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SAIAEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NODIV", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCJDIV", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ACR2", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FFLUS", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIS", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEVAL", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTECN", bit: 7, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPL", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COMP", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AFRCR", offset: 0xC, width: Width::W32, reset: 0x0000_0007, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FRL", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSALL", bit: 8, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSDEF", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSPOL", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSOFF", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ASLOTR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FBOFF", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SLOTSZ", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBSLOT", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SLOTEN", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AIM", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OVRUDRIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEDET", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WCKCFG", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FREQIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNRDYIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSDETIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LFSDET", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ASR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OVRUDR", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEDET", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WCKCFG", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FREQ", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNRDY", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSDET", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LFSDET", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLVL", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ACLRFR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OVRUDR", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEDET", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WCKCFG", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNRDY", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAFSDET", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LFSDET", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ADR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BCR1", offset: 0x24, width: Width::W32, reset: 0x0000_0040, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MODE", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRTCFG", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DS", bit: 5, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSBFIRST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKSTR", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCEN", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MONO", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OutDri", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SAIBEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NODIV", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCJDIV", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BCR2", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FFLUS", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIS", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEVAL", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTECN", bit: 7, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPL", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COMP", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BFRCR", offset: 0x2C, width: Width::W32, reset: 0x0000_0007, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FRL", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSALL", bit: 8, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSDEF", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSPOL", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSOFF", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BSLOTR", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FBOFF", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SLOTSZ", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBSLOT", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SLOTEN", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BIM", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OVRUDRIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEDET", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WCKCFG", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FREQIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNRDYIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSDETIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LFSDETIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BSR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OVRUDR", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEDET", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WCKCFG", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FREQ", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNRDY", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSDET", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LFSDET", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLVL", bit: 16, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BCLRFR", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OVRUDR", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEDET", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WCKCFG", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNRDY", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAFSDET", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LFSDET", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];