rigless 0.0.5

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model, and unit of virtual time in Rust; a fork of QEMU is built in and executes the instructions
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `I2C3` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR1` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr1 = 0,
    /// `CR2` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cr2 = 1,
    /// `OAR1` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Oar1 = 2,
    /// `OAR2` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Oar2 = 3,
    /// `DR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Dr = 4,
    /// `SR1` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Sr1 = 5,
    /// `SR2` at offset `0x18`, resets to `0x0000_0000`, read-only.
    Sr2 = 6,
    /// `CCR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Ccr = 7,
    /// `TRISE` at offset `0x20`, resets to `0x0000_0002`, read-write.
    Trise = 8,
    /// `FLTR` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Fltr = 9,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 10] = [Self::Cr1, Self::Cr2, Self::Oar1, Self::Oar2, Self::Dr, Self::Sr1, Self::Sr2, Self::Ccr, Self::Trise, Self::Fltr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `PE`, bit 0.
    pub const PE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `SMBUS`, bit 1.
    pub const SMBUS: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `SMBTYPE`, bit 3.
    pub const SMBTYPE: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `ENARP`, bit 4.
    pub const ENARP: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `ENPEC`, bit 5.
    pub const ENPEC: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `ENGC`, bit 6.
    pub const ENGC: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `NOSTRETCH`, bit 7.
    pub const NOSTRETCH: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `START`, bit 8.
    pub const START: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `STOP`, bit 9.
    pub const STOP: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `ACK`, bit 10.
    pub const ACK: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `POS`, bit 11.
    pub const POS: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `PEC`, bit 12.
    pub const PEC: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `ALERT`, bit 13.
    pub const ALERT: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `SWRST`, bit 15.
    pub const SWRST: &FieldSpec = &super::REGISTERS[0].fields[13];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `FREQ`, bits 0..=5.
    pub const FREQ: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `ITERREN`, bit 8.
    pub const ITERREN: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `ITEVTEN`, bit 9.
    pub const ITEVTEN: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `ITBUFEN`, bit 10.
    pub const ITBUFEN: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `DMAEN`, bit 11.
    pub const DMAEN: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `LAST`, bit 12.
    pub const LAST: &FieldSpec = &super::REGISTERS[1].fields[5];
}

/// The fields of `OAR1`.
pub mod oar1 {
    use super::FieldSpec;
    /// `ADD0`, bit 0.
    pub const ADD0: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `ADD7`, bits 1..=7.
    pub const ADD7: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `ADD10`, bits 8..=9.
    pub const ADD10: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `ADDMODE`, bit 15.
    pub const ADDMODE: &FieldSpec = &super::REGISTERS[2].fields[3];
}

/// The fields of `OAR2`.
pub mod oar2 {
    use super::FieldSpec;
    /// `ENDUAL`, bit 0.
    pub const ENDUAL: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `ADD2`, bits 1..=7.
    pub const ADD2: &FieldSpec = &super::REGISTERS[3].fields[1];
}

/// The fields of `DR`.
pub mod dr {
    use super::FieldSpec;
    /// `DR`, bits 0..=7.
    pub const DR: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `SR1`.
pub mod sr1 {
    use super::FieldSpec;
    /// `SB`, bit 0, read-only.
    pub const SB: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `ADDR`, bit 1, read-only.
    pub const ADDR: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `BTF`, bit 2, read-only.
    pub const BTF: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `ADD10`, bit 3, read-only.
    pub const ADD10: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `STOPF`, bit 4, read-only.
    pub const STOPF: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `RxNE`, bit 6, read-only.
    pub const RXNE: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `TxE`, bit 7, read-only.
    pub const TXE: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `BERR`, bit 8.
    pub const BERR: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `ARLO`, bit 9.
    pub const ARLO: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `AF`, bit 10.
    pub const AF: &FieldSpec = &super::REGISTERS[5].fields[9];
    /// `OVR`, bit 11.
    pub const OVR: &FieldSpec = &super::REGISTERS[5].fields[10];
    /// `PECERR`, bit 12.
    pub const PECERR: &FieldSpec = &super::REGISTERS[5].fields[11];
    /// `TIMEOUT`, bit 14.
    pub const TIMEOUT: &FieldSpec = &super::REGISTERS[5].fields[12];
    /// `SMBALERT`, bit 15.
    pub const SMBALERT: &FieldSpec = &super::REGISTERS[5].fields[13];
}

/// The fields of `SR2`.
pub mod sr2 {
    use super::FieldSpec;
    /// `MSL`, bit 0.
    pub const MSL: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `BUSY`, bit 1.
    pub const BUSY: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `TRA`, bit 2.
    pub const TRA: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `GENCALL`, bit 4.
    pub const GENCALL: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `SMBDEFAULT`, bit 5.
    pub const SMBDEFAULT: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `SMBHOST`, bit 6.
    pub const SMBHOST: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `DUALF`, bit 7.
    pub const DUALF: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `PEC`, bits 8..=15.
    pub const PEC: &FieldSpec = &super::REGISTERS[6].fields[7];
}

/// The fields of `CCR`.
pub mod ccr {
    use super::FieldSpec;
    /// `CCR`, bits 0..=11.
    pub const CCR: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `DUTY`, bit 14.
    pub const DUTY: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `F_S`, bit 15.
    pub const F_S: &FieldSpec = &super::REGISTERS[7].fields[2];
}

/// The fields of `TRISE`.
pub mod trise {
    use super::FieldSpec;
    /// `TRISE`, bits 0..=5.
    pub const TRISE: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `FLTR`.
pub mod fltr {
    use super::FieldSpec;
    /// `DNF`, bits 0..=3.
    pub const DNF: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `ANOFF`, bit 4.
    pub const ANOFF: &FieldSpec = &super::REGISTERS[9].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 10] = [
    RegisterSpec { name: "CR1", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMBUS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMBTYPE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ENARP", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ENPEC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ENGC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NOSTRETCH", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "START", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STOP", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACK", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "POS", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PEC", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALERT", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWRST", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FREQ", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ITERREN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ITEVTEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ITBUFEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LAST", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OAR1", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADD0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADD7", bit: 1, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADD10", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDMODE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OAR2", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ENDUAL", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADD2", bit: 1, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DR", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR1", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SB", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDR", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BTF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADD10", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STOPF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RxNE", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TxE", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BERR", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARLO", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AF", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PECERR", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMEOUT", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMBALERT", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR2", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MSL", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSY", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRA", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GENCALL", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMBDEFAULT", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMBHOST", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DUALF", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PEC", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCR", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DUTY", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "F_S", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TRISE", offset: 0x20, width: Width::W32, reset: 0x0000_0002, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TRISE", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FLTR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DNF", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ANOFF", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];