rigless 0.0.5

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model, and unit of virtual time in Rust; a fork of QEMU is built in and executes the instructions
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `C_ADC` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CSR` at offset `0x0`, resets to `0x0000_0000`, read-only.
    Csr = 0,
    /// `CCR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Ccr = 1,
    /// `CDR` at offset `0x8`, resets to `0x0000_0000`, read-only.
    Cdr = 2,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 3] = [Self::Csr, Self::Ccr, Self::Cdr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CSR`.
pub mod csr {
    use super::FieldSpec;
    /// `AWD1`, bit 0.
    pub const AWD1: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `EOC1`, bit 1.
    pub const EOC1: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `JEOC1`, bit 2.
    pub const JEOC1: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `JSTRT1`, bit 3.
    pub const JSTRT1: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `STRT1`, bit 4.
    pub const STRT1: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `OVR1`, bit 5.
    pub const OVR1: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `AWD2`, bit 8.
    pub const AWD2: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `EOC2`, bit 9.
    pub const EOC2: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `JEOC2`, bit 10.
    pub const JEOC2: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `JSTRT2`, bit 11.
    pub const JSTRT2: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `STRT2`, bit 12.
    pub const STRT2: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `OVR2`, bit 13.
    pub const OVR2: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `AWD3`, bit 16.
    pub const AWD3: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `EOC3`, bit 17.
    pub const EOC3: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `JEOC3`, bit 18.
    pub const JEOC3: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `JSTRT3`, bit 19.
    pub const JSTRT3: &FieldSpec = &super::REGISTERS[0].fields[15];
    /// `STRT3`, bit 20.
    pub const STRT3: &FieldSpec = &super::REGISTERS[0].fields[16];
    /// `OVR3`, bit 21.
    pub const OVR3: &FieldSpec = &super::REGISTERS[0].fields[17];
}

/// The fields of `CCR`.
pub mod ccr {
    use super::FieldSpec;
    /// `MULT`, bits 0..=4.
    pub const MULT: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `DELAY`, bits 8..=11.
    pub const DELAY: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `DDS`, bit 13.
    pub const DDS: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `DMA`, bits 14..=15.
    pub const DMA: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `ADCPRE`, bits 16..=17.
    pub const ADCPRE: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `VBATE`, bit 22.
    pub const VBATE: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `TSVREFE`, bit 23.
    pub const TSVREFE: &FieldSpec = &super::REGISTERS[1].fields[6];
}

/// The fields of `CDR`.
pub mod cdr {
    use super::FieldSpec;
    /// `DATA1`, bits 0..=15.
    pub const DATA1: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `DATA2`, bits 16..=31.
    pub const DATA2: &FieldSpec = &super::REGISTERS[2].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 3] = [
    RegisterSpec { name: "CSR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AWD1", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOC1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOC1", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSTRT1", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STRT1", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR1", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD2", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOC2", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOC2", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSTRT2", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STRT2", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR2", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD3", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOC3", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOC3", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSTRT3", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STRT3", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR3", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MULT", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DELAY", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DDS", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMA", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADCPRE", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VBATE", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSVREFE", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CDR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATA1", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATA2", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];