rigless 0.0.5

// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `RCC` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR` at offset `0x0`, resets to `0x0000_0083`, read-write.
    Cr = 0,
    /// `PLLCFGR` at offset `0x4`, resets to `0x2400_3010`, read-write.
    Pllcfgr = 1,
    /// `CFGR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Cfgr = 2,
    /// `CIR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Cir = 3,
    /// `AHB1RSTR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Ahb1rstr = 4,
    /// `AHB2RSTR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Ahb2rstr = 5,
    /// `AHB3RSTR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Ahb3rstr = 6,
    /// `APB1RSTR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Apb1rstr = 7,
    /// `APB2RSTR` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Apb2rstr = 8,
    /// `AHB1ENR` at offset `0x30`, resets to `0x0010_0000`, read-write.
    Ahb1enr = 9,
    /// `AHB2ENR` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Ahb2enr = 10,
    /// `AHB3ENR` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Ahb3enr = 11,
    /// `APB1ENR` at offset `0x40`, resets to `0x0000_0000`, read-write.
    Apb1enr = 12,
    /// `APB2ENR` at offset `0x44`, resets to `0x0000_0000`, read-write.
    Apb2enr = 13,
    /// `AHB1LPENR` at offset `0x50`, resets to `0x7E67_91FF`, read-write.
    Ahb1lpenr = 14,
    /// `AHB2LPENR` at offset `0x54`, resets to `0x0000_00F1`, read-write.
    Ahb2lpenr = 15,
    /// `AHB3LPENR` at offset `0x58`, resets to `0x0000_0001`, read-write.
    Ahb3lpenr = 16,
    /// `APB1LPENR` at offset `0x60`, resets to `0x36FE_C9FF`, read-write.
    Apb1lpenr = 17,
    /// `APB2LPENR` at offset `0x64`, resets to `0x0007_5F33`, read-write.
    Apb2lpenr = 18,
    /// `BDCR` at offset `0x70`, resets to `0x0000_0000`, read-write.
    Bdcr = 19,
    /// `CSR` at offset `0x74`, resets to `0x0E00_0000`, read-write.
    Csr = 20,
    /// `SSCGR` at offset `0x80`, resets to `0x0000_0000`, read-write.
    Sscgr = 21,
    /// `PLLI2SCFGR` at offset `0x84`, resets to `0x2000_3000`, read-write.
    Plli2scfgr = 22,
    /// `PLLSAICFGR` at offset `0x88`, resets to `0x2400_3000`, read-write.
    Pllsaicfgr = 23,
    /// `DCKCFGR` at offset `0x8C`, resets to `0x0000_0000`, read-write.
    Dckcfgr = 24,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 25] = [Self::Cr, Self::Pllcfgr, Self::Cfgr, Self::Cir, Self::Ahb1rstr, Self::Ahb2rstr, Self::Ahb3rstr, Self::Apb1rstr, Self::Apb2rstr, Self::Ahb1enr, Self::Ahb2enr, Self::Ahb3enr, Self::Apb1enr, Self::Apb2enr, Self::Ahb1lpenr, Self::Ahb2lpenr, Self::Ahb3lpenr, Self::Apb1lpenr, Self::Apb2lpenr, Self::Bdcr, Self::Csr, Self::Sscgr, Self::Plli2scfgr, Self::Pllsaicfgr, Self::Dckcfgr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `HSION`, bit 0.
    pub const HSION: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `HSIRDY`, bit 1, read-only.
    pub const HSIRDY: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `HSITRIM`, bits 3..=7.
    pub const HSITRIM: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `HSICAL`, bits 8..=15, read-only.
    pub const HSICAL: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `HSEON`, bit 16.
    pub const HSEON: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `HSERDY`, bit 17, read-only.
    pub const HSERDY: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `HSEBYP`, bit 18.
    pub const HSEBYP: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `CSSON`, bit 19.
    pub const CSSON: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `PLLON`, bit 24.
    pub const PLLON: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `PLLRDY`, bit 25, read-only.
    pub const PLLRDY: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `PLLI2SON`, bit 26.
    pub const PLLI2SON: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `PLLI2SRDY`, bit 27, read-only.
    pub const PLLI2SRDY: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `PLLSAION`, bit 28.
    pub const PLLSAION: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `PLLSAIRDY`, bit 29.
    pub const PLLSAIRDY: &FieldSpec = &super::REGISTERS[0].fields[13];
}

/// The fields of `PLLCFGR`.
pub mod pllcfgr {
    use super::FieldSpec;
    /// `PLLM0`, bit 0.
    pub const PLLM0: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `PLLM1`, bit 1.
    pub const PLLM1: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `PLLM2`, bit 2.
    pub const PLLM2: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `PLLM3`, bit 3.
    pub const PLLM3: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `PLLM4`, bit 4.
    pub const PLLM4: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `PLLM5`, bit 5.
    pub const PLLM5: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `PLLN0`, bit 6.
    pub const PLLN0: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `PLLN1`, bit 7.
    pub const PLLN1: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `PLLN2`, bit 8.
    pub const PLLN2: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `PLLN3`, bit 9.
    pub const PLLN3: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `PLLN4`, bit 10.
    pub const PLLN4: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `PLLN5`, bit 11.
    pub const PLLN5: &FieldSpec = &super::REGISTERS[1].fields[11];
    /// `PLLN6`, bit 12.
    pub const PLLN6: &FieldSpec = &super::REGISTERS[1].fields[12];
    /// `PLLN7`, bit 13.
    pub const PLLN7: &FieldSpec = &super::REGISTERS[1].fields[13];
    /// `PLLN8`, bit 14.
    pub const PLLN8: &FieldSpec = &super::REGISTERS[1].fields[14];
    /// `PLLP0`, bit 16.
    pub const PLLP0: &FieldSpec = &super::REGISTERS[1].fields[15];
    /// `PLLP1`, bit 17.
    pub const PLLP1: &FieldSpec = &super::REGISTERS[1].fields[16];
    /// `PLLSRC`, bit 22.
    pub const PLLSRC: &FieldSpec = &super::REGISTERS[1].fields[17];
    /// `PLLQ0`, bit 24.
    pub const PLLQ0: &FieldSpec = &super::REGISTERS[1].fields[18];
    /// `PLLQ1`, bit 25.
    pub const PLLQ1: &FieldSpec = &super::REGISTERS[1].fields[19];
    /// `PLLQ2`, bit 26.
    pub const PLLQ2: &FieldSpec = &super::REGISTERS[1].fields[20];
    /// `PLLQ3`, bit 27.
    pub const PLLQ3: &FieldSpec = &super::REGISTERS[1].fields[21];
}

/// The fields of `CFGR`.
pub mod cfgr {
    use super::FieldSpec;
    /// `SW0`, bit 0.
    pub const SW0: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `SW1`, bit 1.
    pub const SW1: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `SWS0`, bit 2, read-only.
    pub const SWS0: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `SWS1`, bit 3, read-only.
    pub const SWS1: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `HPRE`, bits 4..=7.
    pub const HPRE: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `PPRE1`, bits 10..=12.
    pub const PPRE1: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `PPRE2`, bits 13..=15.
    pub const PPRE2: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `RTCPRE`, bits 16..=20.
    pub const RTCPRE: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `MCO1`, bits 21..=22.
    pub const MCO1: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `I2SSRC`, bit 23.
    pub const I2SSRC: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `MCO1PRE`, bits 24..=26.
    pub const MCO1PRE: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `MCO2PRE`, bits 27..=29.
    pub const MCO2PRE: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `MCO2`, bits 30..=31.
    pub const MCO2: &FieldSpec = &super::REGISTERS[2].fields[12];
}

/// The fields of `CIR`.
pub mod cir {
    use super::FieldSpec;
    /// `LSIRDYF`, bit 0, read-only.
    pub const LSIRDYF: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `LSERDYF`, bit 1, read-only.
    pub const LSERDYF: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `HSIRDYF`, bit 2, read-only.
    pub const HSIRDYF: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `HSERDYF`, bit 3, read-only.
    pub const HSERDYF: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `PLLRDYF`, bit 4, read-only.
    pub const PLLRDYF: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `PLLI2SRDYF`, bit 5, read-only.
    pub const PLLI2SRDYF: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `CSSF`, bit 7, read-only.
    pub const CSSF: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `LSIRDYIE`, bit 8.
    pub const LSIRDYIE: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `LSERDYIE`, bit 9.
    pub const LSERDYIE: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `HSIRDYIE`, bit 10.
    pub const HSIRDYIE: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `HSERDYIE`, bit 11.
    pub const HSERDYIE: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `PLLRDYIE`, bit 12.
    pub const PLLRDYIE: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `PLLI2SRDYIE`, bit 13.
    pub const PLLI2SRDYIE: &FieldSpec = &super::REGISTERS[3].fields[12];
    /// `LSIRDYC`, bit 16, write-only.
    pub const LSIRDYC: &FieldSpec = &super::REGISTERS[3].fields[13];
    /// `LSERDYC`, bit 17, write-only.
    pub const LSERDYC: &FieldSpec = &super::REGISTERS[3].fields[14];
    /// `HSIRDYC`, bit 18, write-only.
    pub const HSIRDYC: &FieldSpec = &super::REGISTERS[3].fields[15];
    /// `HSERDYC`, bit 19, write-only.
    pub const HSERDYC: &FieldSpec = &super::REGISTERS[3].fields[16];
    /// `PLLRDYC`, bit 20, write-only.
    pub const PLLRDYC: &FieldSpec = &super::REGISTERS[3].fields[17];
    /// `PLLI2SRDYC`, bit 21, write-only.
    pub const PLLI2SRDYC: &FieldSpec = &super::REGISTERS[3].fields[18];
    /// `CSSC`, bit 23, write-only.
    pub const CSSC: &FieldSpec = &super::REGISTERS[3].fields[19];
}

/// The fields of `AHB1RSTR`.
pub mod ahb1rstr {
    use super::FieldSpec;
    /// `GPIOARST`, bit 0.
    pub const GPIOARST: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `GPIOBRST`, bit 1.
    pub const GPIOBRST: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `GPIOCRST`, bit 2.
    pub const GPIOCRST: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `GPIODRST`, bit 3.
    pub const GPIODRST: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `GPIOERST`, bit 4.
    pub const GPIOERST: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `GPIOFRST`, bit 5.
    pub const GPIOFRST: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `GPIOGRST`, bit 6.
    pub const GPIOGRST: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `GPIOHRST`, bit 7.
    pub const GPIOHRST: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `GPIOIRST`, bit 8.
    pub const GPIOIRST: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `CRCRST`, bit 12.
    pub const CRCRST: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `DMA1RST`, bit 21.
    pub const DMA1RST: &FieldSpec = &super::REGISTERS[4].fields[10];
    /// `DMA2RST`, bit 22.
    pub const DMA2RST: &FieldSpec = &super::REGISTERS[4].fields[11];
    /// `ETHMACRST`, bit 25.
    pub const ETHMACRST: &FieldSpec = &super::REGISTERS[4].fields[12];
    /// `OTGHSRST`, bit 29.
    pub const OTGHSRST: &FieldSpec = &super::REGISTERS[4].fields[13];
}

/// The fields of `AHB2RSTR`.
pub mod ahb2rstr {
    use super::FieldSpec;
    /// `DCMIRST`, bit 0.
    pub const DCMIRST: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `CRYPRST`, bit 4.
    pub const CRYPRST: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `HSAHRST`, bit 5.
    pub const HSAHRST: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `RNGRST`, bit 6.
    pub const RNGRST: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `OTGFSRST`, bit 7.
    pub const OTGFSRST: &FieldSpec = &super::REGISTERS[5].fields[4];
}

/// The fields of `AHB3RSTR`.
pub mod ahb3rstr {
    use super::FieldSpec;
    /// `FMCRST`, bit 0.
    pub const FMCRST: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `APB1RSTR`.
pub mod apb1rstr {
    use super::FieldSpec;
    /// `TIM2RST`, bit 0.
    pub const TIM2RST: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `TIM3RST`, bit 1.
    pub const TIM3RST: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `TIM4RST`, bit 2.
    pub const TIM4RST: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `TIM5RST`, bit 3.
    pub const TIM5RST: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `TIM6RST`, bit 4.
    pub const TIM6RST: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `TIM7RST`, bit 5.
    pub const TIM7RST: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `TIM12RST`, bit 6.
    pub const TIM12RST: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `TIM13RST`, bit 7.
    pub const TIM13RST: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `TIM14RST`, bit 8.
    pub const TIM14RST: &FieldSpec = &super::REGISTERS[7].fields[8];
    /// `WWDGRST`, bit 11.
    pub const WWDGRST: &FieldSpec = &super::REGISTERS[7].fields[9];
    /// `SPI2RST`, bit 14.
    pub const SPI2RST: &FieldSpec = &super::REGISTERS[7].fields[10];
    /// `SPI3RST`, bit 15.
    pub const SPI3RST: &FieldSpec = &super::REGISTERS[7].fields[11];
    /// `UART2RST`, bit 17.
    pub const UART2RST: &FieldSpec = &super::REGISTERS[7].fields[12];
    /// `UART3RST`, bit 18.
    pub const UART3RST: &FieldSpec = &super::REGISTERS[7].fields[13];
    /// `UART4RST`, bit 19.
    pub const UART4RST: &FieldSpec = &super::REGISTERS[7].fields[14];
    /// `UART5RST`, bit 20.
    pub const UART5RST: &FieldSpec = &super::REGISTERS[7].fields[15];
    /// `I2C1RST`, bit 21.
    pub const I2C1RST: &FieldSpec = &super::REGISTERS[7].fields[16];
    /// `I2C2RST`, bit 22.
    pub const I2C2RST: &FieldSpec = &super::REGISTERS[7].fields[17];
    /// `I2C3RST`, bit 23.
    pub const I2C3RST: &FieldSpec = &super::REGISTERS[7].fields[18];
    /// `CAN1RST`, bit 25.
    pub const CAN1RST: &FieldSpec = &super::REGISTERS[7].fields[19];
    /// `CAN2RST`, bit 26.
    pub const CAN2RST: &FieldSpec = &super::REGISTERS[7].fields[20];
    /// `PWRRST`, bit 28.
    pub const PWRRST: &FieldSpec = &super::REGISTERS[7].fields[21];
    /// `DACRST`, bit 29.
    pub const DACRST: &FieldSpec = &super::REGISTERS[7].fields[22];
    /// `UART7RST`, bit 30.
    pub const UART7RST: &FieldSpec = &super::REGISTERS[7].fields[23];
    /// `UART8RST`, bit 31.
    pub const UART8RST: &FieldSpec = &super::REGISTERS[7].fields[24];
}

/// The fields of `APB2RSTR`.
pub mod apb2rstr {
    use super::FieldSpec;
    /// `TIM1RST`, bit 0.
    pub const TIM1RST: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `TIM8RST`, bit 1.
    pub const TIM8RST: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `USART1RST`, bit 4.
    pub const USART1RST: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `USART6RST`, bit 5.
    pub const USART6RST: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `ADCRST`, bit 8.
    pub const ADCRST: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `SDIORST`, bit 11.
    pub const SDIORST: &FieldSpec = &super::REGISTERS[8].fields[5];
    /// `SPI1RST`, bit 12.
    pub const SPI1RST: &FieldSpec = &super::REGISTERS[8].fields[6];
    /// `SPI4RST`, bit 13.
    pub const SPI4RST: &FieldSpec = &super::REGISTERS[8].fields[7];
    /// `SYSCFGRST`, bit 14.
    pub const SYSCFGRST: &FieldSpec = &super::REGISTERS[8].fields[8];
    /// `TIM9RST`, bit 16.
    pub const TIM9RST: &FieldSpec = &super::REGISTERS[8].fields[9];
    /// `TIM10RST`, bit 17.
    pub const TIM10RST: &FieldSpec = &super::REGISTERS[8].fields[10];
    /// `TIM11RST`, bit 18.
    pub const TIM11RST: &FieldSpec = &super::REGISTERS[8].fields[11];
    /// `SPI5RST`, bit 20.
    pub const SPI5RST: &FieldSpec = &super::REGISTERS[8].fields[12];
    /// `SPI6RST`, bit 21.
    pub const SPI6RST: &FieldSpec = &super::REGISTERS[8].fields[13];
}

/// The fields of `AHB1ENR`.
pub mod ahb1enr {
    use super::FieldSpec;
    /// `GPIOAEN`, bit 0.
    pub const GPIOAEN: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `GPIOBEN`, bit 1.
    pub const GPIOBEN: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `GPIOCEN`, bit 2.
    pub const GPIOCEN: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `GPIODEN`, bit 3.
    pub const GPIODEN: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `GPIOEEN`, bit 4.
    pub const GPIOEEN: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `GPIOFEN`, bit 5.
    pub const GPIOFEN: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `GPIOGEN`, bit 6.
    pub const GPIOGEN: &FieldSpec = &super::REGISTERS[9].fields[6];
    /// `GPIOHEN`, bit 7.
    pub const GPIOHEN: &FieldSpec = &super::REGISTERS[9].fields[7];
    /// `GPIOIEN`, bit 8.
    pub const GPIOIEN: &FieldSpec = &super::REGISTERS[9].fields[8];
    /// `CRCEN`, bit 12.
    pub const CRCEN: &FieldSpec = &super::REGISTERS[9].fields[9];
    /// `BKPSRAMEN`, bit 18.
    pub const BKPSRAMEN: &FieldSpec = &super::REGISTERS[9].fields[10];
    /// `CCMDATARAMEN`, bit 20.
    pub const CCMDATARAMEN: &FieldSpec = &super::REGISTERS[9].fields[11];
    /// `DMA1EN`, bit 21.
    pub const DMA1EN: &FieldSpec = &super::REGISTERS[9].fields[12];
    /// `DMA2EN`, bit 22.
    pub const DMA2EN: &FieldSpec = &super::REGISTERS[9].fields[13];
    /// `ETHMACEN`, bit 25.
    pub const ETHMACEN: &FieldSpec = &super::REGISTERS[9].fields[14];
    /// `ETHMACTXEN`, bit 26.
    pub const ETHMACTXEN: &FieldSpec = &super::REGISTERS[9].fields[15];
    /// `ETHMACRXEN`, bit 27.
    pub const ETHMACRXEN: &FieldSpec = &super::REGISTERS[9].fields[16];
    /// `ETHMACPTPEN`, bit 28.
    pub const ETHMACPTPEN: &FieldSpec = &super::REGISTERS[9].fields[17];
    /// `OTGHSEN`, bit 29.
    pub const OTGHSEN: &FieldSpec = &super::REGISTERS[9].fields[18];
    /// `OTGHSULPIEN`, bit 30.
    pub const OTGHSULPIEN: &FieldSpec = &super::REGISTERS[9].fields[19];
}

/// The fields of `AHB2ENR`.
pub mod ahb2enr {
    use super::FieldSpec;
    /// `DCMIEN`, bit 0.
    pub const DCMIEN: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `CRYPEN`, bit 4.
    pub const CRYPEN: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `HASHEN`, bit 5.
    pub const HASHEN: &FieldSpec = &super::REGISTERS[10].fields[2];
    /// `RNGEN`, bit 6.
    pub const RNGEN: &FieldSpec = &super::REGISTERS[10].fields[3];
    /// `OTGFSEN`, bit 7.
    pub const OTGFSEN: &FieldSpec = &super::REGISTERS[10].fields[4];
}

/// The fields of `AHB3ENR`.
pub mod ahb3enr {
    use super::FieldSpec;
    /// `FMCEN`, bit 0.
    pub const FMCEN: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `APB1ENR`.
pub mod apb1enr {
    use super::FieldSpec;
    /// `TIM2EN`, bit 0.
    pub const TIM2EN: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `TIM3EN`, bit 1.
    pub const TIM3EN: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `TIM4EN`, bit 2.
    pub const TIM4EN: &FieldSpec = &super::REGISTERS[12].fields[2];
    /// `TIM5EN`, bit 3.
    pub const TIM5EN: &FieldSpec = &super::REGISTERS[12].fields[3];
    /// `TIM6EN`, bit 4.
    pub const TIM6EN: &FieldSpec = &super::REGISTERS[12].fields[4];
    /// `TIM7EN`, bit 5.
    pub const TIM7EN: &FieldSpec = &super::REGISTERS[12].fields[5];
    /// `TIM12EN`, bit 6.
    pub const TIM12EN: &FieldSpec = &super::REGISTERS[12].fields[6];
    /// `TIM13EN`, bit 7.
    pub const TIM13EN: &FieldSpec = &super::REGISTERS[12].fields[7];
    /// `TIM14EN`, bit 8.
    pub const TIM14EN: &FieldSpec = &super::REGISTERS[12].fields[8];
    /// `WWDGEN`, bit 11.
    pub const WWDGEN: &FieldSpec = &super::REGISTERS[12].fields[9];
    /// `SPI2EN`, bit 14.
    pub const SPI2EN: &FieldSpec = &super::REGISTERS[12].fields[10];
    /// `SPI3EN`, bit 15.
    pub const SPI3EN: &FieldSpec = &super::REGISTERS[12].fields[11];
    /// `USART2EN`, bit 17.
    pub const USART2EN: &FieldSpec = &super::REGISTERS[12].fields[12];
    /// `USART3EN`, bit 18.
    pub const USART3EN: &FieldSpec = &super::REGISTERS[12].fields[13];
    /// `UART4EN`, bit 19.
    pub const UART4EN: &FieldSpec = &super::REGISTERS[12].fields[14];
    /// `UART5EN`, bit 20.
    pub const UART5EN: &FieldSpec = &super::REGISTERS[12].fields[15];
    /// `I2C1EN`, bit 21.
    pub const I2C1EN: &FieldSpec = &super::REGISTERS[12].fields[16];
    /// `I2C2EN`, bit 22.
    pub const I2C2EN: &FieldSpec = &super::REGISTERS[12].fields[17];
    /// `I2C3EN`, bit 23.
    pub const I2C3EN: &FieldSpec = &super::REGISTERS[12].fields[18];
    /// `CAN1EN`, bit 25.
    pub const CAN1EN: &FieldSpec = &super::REGISTERS[12].fields[19];
    /// `CAN2EN`, bit 26.
    pub const CAN2EN: &FieldSpec = &super::REGISTERS[12].fields[20];
    /// `PWREN`, bit 28.
    pub const PWREN: &FieldSpec = &super::REGISTERS[12].fields[21];
    /// `DACEN`, bit 29.
    pub const DACEN: &FieldSpec = &super::REGISTERS[12].fields[22];
    /// `UART7ENR`, bit 30.
    pub const UART7ENR: &FieldSpec = &super::REGISTERS[12].fields[23];
    /// `UART8ENR`, bit 31.
    pub const UART8ENR: &FieldSpec = &super::REGISTERS[12].fields[24];
}

/// The fields of `APB2ENR`.
pub mod apb2enr {
    use super::FieldSpec;
    /// `TIM1EN`, bit 0.
    pub const TIM1EN: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `TIM8EN`, bit 1.
    pub const TIM8EN: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `USART1EN`, bit 4.
    pub const USART1EN: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `USART6EN`, bit 5.
    pub const USART6EN: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `ADC1EN`, bit 8.
    pub const ADC1EN: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `ADC2EN`, bit 9.
    pub const ADC2EN: &FieldSpec = &super::REGISTERS[13].fields[5];
    /// `ADC3EN`, bit 10.
    pub const ADC3EN: &FieldSpec = &super::REGISTERS[13].fields[6];
    /// `SDIOEN`, bit 11.
    pub const SDIOEN: &FieldSpec = &super::REGISTERS[13].fields[7];
    /// `SPI1EN`, bit 12.
    pub const SPI1EN: &FieldSpec = &super::REGISTERS[13].fields[8];
    /// `SPI4EN`, bit 13.
    pub const SPI4EN: &FieldSpec = &super::REGISTERS[13].fields[9];
    /// `SYSCFGEN`, bit 14.
    pub const SYSCFGEN: &FieldSpec = &super::REGISTERS[13].fields[10];
    /// `TIM9EN`, bit 16.
    pub const TIM9EN: &FieldSpec = &super::REGISTERS[13].fields[11];
    /// `TIM10EN`, bit 17.
    pub const TIM10EN: &FieldSpec = &super::REGISTERS[13].fields[12];
    /// `TIM11EN`, bit 18.
    pub const TIM11EN: &FieldSpec = &super::REGISTERS[13].fields[13];
    /// `SPI5EN`, bit 20.
    pub const SPI5EN: &FieldSpec = &super::REGISTERS[13].fields[14];
    /// `SPI6EN`, bit 21.
    pub const SPI6EN: &FieldSpec = &super::REGISTERS[13].fields[15];
    /// `SAI1EN`, bit 22.
    pub const SAI1EN: &FieldSpec = &super::REGISTERS[13].fields[16];
    /// `LTDCEN`, bit 26.
    pub const LTDCEN: &FieldSpec = &super::REGISTERS[13].fields[17];
}

/// The fields of `AHB1LPENR`.
pub mod ahb1lpenr {
    use super::FieldSpec;
    /// `GPIOALPEN`, bit 0.
    pub const GPIOALPEN: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `GPIOBLPEN`, bit 1.
    pub const GPIOBLPEN: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `GPIOCLPEN`, bit 2.
    pub const GPIOCLPEN: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `GPIODLPEN`, bit 3.
    pub const GPIODLPEN: &FieldSpec = &super::REGISTERS[14].fields[3];
    /// `GPIOELPEN`, bit 4.
    pub const GPIOELPEN: &FieldSpec = &super::REGISTERS[14].fields[4];
    /// `GPIOFLPEN`, bit 5.
    pub const GPIOFLPEN: &FieldSpec = &super::REGISTERS[14].fields[5];
    /// `GPIOGLPEN`, bit 6.
    pub const GPIOGLPEN: &FieldSpec = &super::REGISTERS[14].fields[6];
    /// `GPIOHLPEN`, bit 7.
    pub const GPIOHLPEN: &FieldSpec = &super::REGISTERS[14].fields[7];
    /// `GPIOILPEN`, bit 8.
    pub const GPIOILPEN: &FieldSpec = &super::REGISTERS[14].fields[8];
    /// `CRCLPEN`, bit 12.
    pub const CRCLPEN: &FieldSpec = &super::REGISTERS[14].fields[9];
    /// `FLITFLPEN`, bit 15.
    pub const FLITFLPEN: &FieldSpec = &super::REGISTERS[14].fields[10];
    /// `SRAM1LPEN`, bit 16.
    pub const SRAM1LPEN: &FieldSpec = &super::REGISTERS[14].fields[11];
    /// `SRAM2LPEN`, bit 17.
    pub const SRAM2LPEN: &FieldSpec = &super::REGISTERS[14].fields[12];
    /// `BKPSRAMLPEN`, bit 18.
    pub const BKPSRAMLPEN: &FieldSpec = &super::REGISTERS[14].fields[13];
    /// `SRAM3LPEN`, bit 19.
    pub const SRAM3LPEN: &FieldSpec = &super::REGISTERS[14].fields[14];
    /// `DMA1LPEN`, bit 21.
    pub const DMA1LPEN: &FieldSpec = &super::REGISTERS[14].fields[15];
    /// `DMA2LPEN`, bit 22.
    pub const DMA2LPEN: &FieldSpec = &super::REGISTERS[14].fields[16];
    /// `ETHMACLPEN`, bit 25.
    pub const ETHMACLPEN: &FieldSpec = &super::REGISTERS[14].fields[17];
    /// `ETHMACTXLPEN`, bit 26.
    pub const ETHMACTXLPEN: &FieldSpec = &super::REGISTERS[14].fields[18];
    /// `ETHMACRXLPEN`, bit 27.
    pub const ETHMACRXLPEN: &FieldSpec = &super::REGISTERS[14].fields[19];
    /// `ETHMACPTPLPEN`, bit 28.
    pub const ETHMACPTPLPEN: &FieldSpec = &super::REGISTERS[14].fields[20];
    /// `OTGHSLPEN`, bit 29.
    pub const OTGHSLPEN: &FieldSpec = &super::REGISTERS[14].fields[21];
    /// `OTGHSULPILPEN`, bit 30.
    pub const OTGHSULPILPEN: &FieldSpec = &super::REGISTERS[14].fields[22];
}

/// The fields of `AHB2LPENR`.
pub mod ahb2lpenr {
    use super::FieldSpec;
    /// `DCMILPEN`, bit 0.
    pub const DCMILPEN: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `CRYPLPEN`, bit 4.
    pub const CRYPLPEN: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `HASHLPEN`, bit 5.
    pub const HASHLPEN: &FieldSpec = &super::REGISTERS[15].fields[2];
    /// `RNGLPEN`, bit 6.
    pub const RNGLPEN: &FieldSpec = &super::REGISTERS[15].fields[3];
    /// `OTGFSLPEN`, bit 7.
    pub const OTGFSLPEN: &FieldSpec = &super::REGISTERS[15].fields[4];
}

/// The fields of `AHB3LPENR`.
pub mod ahb3lpenr {
    use super::FieldSpec;
    /// `FMCLPEN`, bit 0.
    pub const FMCLPEN: &FieldSpec = &super::REGISTERS[16].fields[0];
}

/// The fields of `APB1LPENR`.
pub mod apb1lpenr {
    use super::FieldSpec;
    /// `TIM2LPEN`, bit 0.
    pub const TIM2LPEN: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `TIM3LPEN`, bit 1.
    pub const TIM3LPEN: &FieldSpec = &super::REGISTERS[17].fields[1];
    /// `TIM4LPEN`, bit 2.
    pub const TIM4LPEN: &FieldSpec = &super::REGISTERS[17].fields[2];
    /// `TIM5LPEN`, bit 3.
    pub const TIM5LPEN: &FieldSpec = &super::REGISTERS[17].fields[3];
    /// `TIM6LPEN`, bit 4.
    pub const TIM6LPEN: &FieldSpec = &super::REGISTERS[17].fields[4];
    /// `TIM7LPEN`, bit 5.
    pub const TIM7LPEN: &FieldSpec = &super::REGISTERS[17].fields[5];
    /// `TIM12LPEN`, bit 6.
    pub const TIM12LPEN: &FieldSpec = &super::REGISTERS[17].fields[6];
    /// `TIM13LPEN`, bit 7.
    pub const TIM13LPEN: &FieldSpec = &super::REGISTERS[17].fields[7];
    /// `TIM14LPEN`, bit 8.
    pub const TIM14LPEN: &FieldSpec = &super::REGISTERS[17].fields[8];
    /// `WWDGLPEN`, bit 11.
    pub const WWDGLPEN: &FieldSpec = &super::REGISTERS[17].fields[9];
    /// `SPI2LPEN`, bit 14.
    pub const SPI2LPEN: &FieldSpec = &super::REGISTERS[17].fields[10];
    /// `SPI3LPEN`, bit 15.
    pub const SPI3LPEN: &FieldSpec = &super::REGISTERS[17].fields[11];
    /// `USART2LPEN`, bit 17.
    pub const USART2LPEN: &FieldSpec = &super::REGISTERS[17].fields[12];
    /// `USART3LPEN`, bit 18.
    pub const USART3LPEN: &FieldSpec = &super::REGISTERS[17].fields[13];
    /// `UART4LPEN`, bit 19.
    pub const UART4LPEN: &FieldSpec = &super::REGISTERS[17].fields[14];
    /// `UART5LPEN`, bit 20.
    pub const UART5LPEN: &FieldSpec = &super::REGISTERS[17].fields[15];
    /// `I2C1LPEN`, bit 21.
    pub const I2C1LPEN: &FieldSpec = &super::REGISTERS[17].fields[16];
    /// `I2C2LPEN`, bit 22.
    pub const I2C2LPEN: &FieldSpec = &super::REGISTERS[17].fields[17];
    /// `I2C3LPEN`, bit 23.
    pub const I2C3LPEN: &FieldSpec = &super::REGISTERS[17].fields[18];
    /// `CAN1LPEN`, bit 25.
    pub const CAN1LPEN: &FieldSpec = &super::REGISTERS[17].fields[19];
    /// `CAN2LPEN`, bit 26.
    pub const CAN2LPEN: &FieldSpec = &super::REGISTERS[17].fields[20];
    /// `PWRLPEN`, bit 28.
    pub const PWRLPEN: &FieldSpec = &super::REGISTERS[17].fields[21];
    /// `DACLPEN`, bit 29.
    pub const DACLPEN: &FieldSpec = &super::REGISTERS[17].fields[22];
    /// `UART7LPEN`, bit 30.
    pub const UART7LPEN: &FieldSpec = &super::REGISTERS[17].fields[23];
    /// `UART8LPEN`, bit 31.
    pub const UART8LPEN: &FieldSpec = &super::REGISTERS[17].fields[24];
}

/// The fields of `APB2LPENR`.
pub mod apb2lpenr {
    use super::FieldSpec;
    /// `TIM1LPEN`, bit 0.
    pub const TIM1LPEN: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `TIM8LPEN`, bit 1.
    pub const TIM8LPEN: &FieldSpec = &super::REGISTERS[18].fields[1];
    /// `USART1LPEN`, bit 4.
    pub const USART1LPEN: &FieldSpec = &super::REGISTERS[18].fields[2];
    /// `USART6LPEN`, bit 5.
    pub const USART6LPEN: &FieldSpec = &super::REGISTERS[18].fields[3];
    /// `ADC1LPEN`, bit 8.
    pub const ADC1LPEN: &FieldSpec = &super::REGISTERS[18].fields[4];
    /// `ADC2LPEN`, bit 9.
    pub const ADC2LPEN: &FieldSpec = &super::REGISTERS[18].fields[5];
    /// `ADC3LPEN`, bit 10.
    pub const ADC3LPEN: &FieldSpec = &super::REGISTERS[18].fields[6];
    /// `SDIOLPEN`, bit 11.
    pub const SDIOLPEN: &FieldSpec = &super::REGISTERS[18].fields[7];
    /// `SPI1LPEN`, bit 12.
    pub const SPI1LPEN: &FieldSpec = &super::REGISTERS[18].fields[8];
    /// `SPI4LPEN`, bit 13.
    pub const SPI4LPEN: &FieldSpec = &super::REGISTERS[18].fields[9];
    /// `SYSCFGLPEN`, bit 14.
    pub const SYSCFGLPEN: &FieldSpec = &super::REGISTERS[18].fields[10];
    /// `TIM9LPEN`, bit 16.
    pub const TIM9LPEN: &FieldSpec = &super::REGISTERS[18].fields[11];
    /// `TIM10LPEN`, bit 17.
    pub const TIM10LPEN: &FieldSpec = &super::REGISTERS[18].fields[12];
    /// `TIM11LPEN`, bit 18.
    pub const TIM11LPEN: &FieldSpec = &super::REGISTERS[18].fields[13];
    /// `SPI5LPEN`, bit 20.
    pub const SPI5LPEN: &FieldSpec = &super::REGISTERS[18].fields[14];
    /// `SPI6LPEN`, bit 21.
    pub const SPI6LPEN: &FieldSpec = &super::REGISTERS[18].fields[15];
}

/// The fields of `BDCR`.
pub mod bdcr {
    use super::FieldSpec;
    /// `LSEON`, bit 0.
    pub const LSEON: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `LSERDY`, bit 1, read-only.
    pub const LSERDY: &FieldSpec = &super::REGISTERS[19].fields[1];
    /// `LSEBYP`, bit 2.
    pub const LSEBYP: &FieldSpec = &super::REGISTERS[19].fields[2];
    /// `RTCSEL0`, bit 8.
    pub const RTCSEL0: &FieldSpec = &super::REGISTERS[19].fields[3];
    /// `RTCSEL1`, bit 9.
    pub const RTCSEL1: &FieldSpec = &super::REGISTERS[19].fields[4];
    /// `RTCEN`, bit 15.
    pub const RTCEN: &FieldSpec = &super::REGISTERS[19].fields[5];
    /// `BDRST`, bit 16.
    pub const BDRST: &FieldSpec = &super::REGISTERS[19].fields[6];
}

/// The fields of `CSR`.
pub mod csr {
    use super::FieldSpec;
    /// `LSION`, bit 0.
    pub const LSION: &FieldSpec = &super::REGISTERS[20].fields[0];
    /// `LSIRDY`, bit 1, read-only.
    pub const LSIRDY: &FieldSpec = &super::REGISTERS[20].fields[1];
    /// `RMVF`, bit 24.
    pub const RMVF: &FieldSpec = &super::REGISTERS[20].fields[2];
    /// `BORRSTF`, bit 25.
    pub const BORRSTF: &FieldSpec = &super::REGISTERS[20].fields[3];
    /// `PADRSTF`, bit 26.
    pub const PADRSTF: &FieldSpec = &super::REGISTERS[20].fields[4];
    /// `PORRSTF`, bit 27.
    pub const PORRSTF: &FieldSpec = &super::REGISTERS[20].fields[5];
    /// `SFTRSTF`, bit 28.
    pub const SFTRSTF: &FieldSpec = &super::REGISTERS[20].fields[6];
    /// `WDGRSTF`, bit 29.
    pub const WDGRSTF: &FieldSpec = &super::REGISTERS[20].fields[7];
    /// `WWDGRSTF`, bit 30.
    pub const WWDGRSTF: &FieldSpec = &super::REGISTERS[20].fields[8];
    /// `LPWRRSTF`, bit 31.
    pub const LPWRRSTF: &FieldSpec = &super::REGISTERS[20].fields[9];
}

/// The fields of `SSCGR`.
pub mod sscgr {
    use super::FieldSpec;
    /// `MODPER`, bits 0..=12.
    pub const MODPER: &FieldSpec = &super::REGISTERS[21].fields[0];
    /// `INCSTEP`, bits 13..=27.
    pub const INCSTEP: &FieldSpec = &super::REGISTERS[21].fields[1];
    /// `SPREADSEL`, bit 30.
    pub const SPREADSEL: &FieldSpec = &super::REGISTERS[21].fields[2];
    /// `SSCGEN`, bit 31.
    pub const SSCGEN: &FieldSpec = &super::REGISTERS[21].fields[3];
}

/// The fields of `PLLI2SCFGR`.
pub mod plli2scfgr {
    use super::FieldSpec;
    /// `PLLI2SNx`, bits 6..=14.
    pub const PLLI2SNX: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `PLLI2SRx`, bits 28..=30.
    pub const PLLI2SRX: &FieldSpec = &super::REGISTERS[22].fields[1];
}

/// The fields of `PLLSAICFGR`.
pub mod pllsaicfgr {
    use super::FieldSpec;
    /// `PLLSAIN`, bits 6..=14.
    pub const PLLSAIN: &FieldSpec = &super::REGISTERS[23].fields[0];
    /// `PLLSAIQ`, bits 24..=27.
    pub const PLLSAIQ: &FieldSpec = &super::REGISTERS[23].fields[1];
    /// `PLLSAIR`, bits 28..=30.
    pub const PLLSAIR: &FieldSpec = &super::REGISTERS[23].fields[2];
}

/// The fields of `DCKCFGR`.
pub mod dckcfgr {
    use super::FieldSpec;
    /// `PLLI2SDIVQ`, bits 0..=4.
    pub const PLLI2SDIVQ: &FieldSpec = &super::REGISTERS[24].fields[0];
    /// `PLLSAIDIVQ`, bits 8..=12.
    pub const PLLSAIDIVQ: &FieldSpec = &super::REGISTERS[24].fields[1];
    /// `PLLSAIDIVR`, bits 16..=17.
    pub const PLLSAIDIVR: &FieldSpec = &super::REGISTERS[24].fields[2];
    /// `SAI1ASRC`, bits 20..=21.
    pub const SAI1ASRC: &FieldSpec = &super::REGISTERS[24].fields[3];
    /// `SAI1BSRC`, bits 22..=23.
    pub const SAI1BSRC: &FieldSpec = &super::REGISTERS[24].fields[4];
    /// `TIMPRE`, bit 24.
    pub const TIMPRE: &FieldSpec = &super::REGISTERS[24].fields[5];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 25] = [
    RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0083, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HSION", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSIRDY", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSITRIM", bit: 3, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSICAL", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSEON", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSERDY", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSEBYP", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSSON", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLON", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLRDY", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLI2SON", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLI2SRDY", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLSAION", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLSAIRDY", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PLLCFGR", offset: 0x4, width: Width::W32, reset: 0x2400_3010, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PLLM0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLM1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLM2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLM3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLM4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLM5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLN0", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLN1", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLN2", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLN3", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLN4", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLN5", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLN6", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLN7", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLN8", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLP0", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLP1", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLSRC", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLQ0", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLQ1", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLQ2", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLQ3", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFGR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SW0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SW1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWS0", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWS1", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HPRE", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PPRE1", bit: 10, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PPRE2", bit: 13, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTCPRE", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCO1", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2SSRC", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCO1PRE", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCO2PRE", bit: 27, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCO2", bit: 30, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CIR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LSIRDYF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSERDYF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSIRDYF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSERDYF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLRDYF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLI2SRDYF", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSSF", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSIRDYIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSERDYIE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSIRDYIE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSERDYIE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLRDYIE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLI2SRDYIE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSIRDYC", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSERDYC", bit: 17, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSIRDYC", bit: 18, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSERDYC", bit: 19, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLRDYC", bit: 20, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLI2SRDYC", bit: 21, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSSC", bit: 23, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AHB1RSTR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "GPIOARST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOBRST", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOCRST", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIODRST", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOERST", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOFRST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOGRST", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOHRST", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOIRST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRCRST", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMA1RST", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMA2RST", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETHMACRST", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OTGHSRST", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AHB2RSTR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DCMIRST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRYPRST", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSAHRST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RNGRST", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OTGFSRST", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AHB3RSTR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FMCRST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "APB1RSTR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIM2RST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM3RST", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM4RST", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM5RST", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM6RST", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM7RST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM12RST", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM13RST", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM14RST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WWDGRST", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI2RST", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI3RST", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART2RST", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART3RST", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART4RST", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART5RST", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C1RST", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C2RST", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C3RST", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAN1RST", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAN2RST", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWRRST", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DACRST", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART7RST", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART8RST", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "APB2RSTR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIM1RST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM8RST", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USART1RST", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USART6RST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADCRST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIORST", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI1RST", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI4RST", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYSCFGRST", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM9RST", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM10RST", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM11RST", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI5RST", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI6RST", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AHB1ENR", offset: 0x30, width: Width::W32, reset: 0x0010_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "GPIOAEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOBEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOCEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIODEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOEEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOFEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOGEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOHEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOIEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRCEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKPSRAMEN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCMDATARAMEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMA1EN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMA2EN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETHMACEN", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETHMACTXEN", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETHMACRXEN", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETHMACPTPEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OTGHSEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OTGHSULPIEN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AHB2ENR", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DCMIEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRYPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HASHEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RNGEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OTGFSEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AHB3ENR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FMCEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "APB1ENR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIM2EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM3EN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM4EN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM5EN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM6EN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM7EN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM12EN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM13EN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM14EN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WWDGEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI2EN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI3EN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USART2EN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USART3EN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART4EN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART5EN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C1EN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C2EN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C3EN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAN1EN", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAN2EN", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWREN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DACEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART7ENR", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART8ENR", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "APB2ENR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIM1EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM8EN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USART1EN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USART6EN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADC1EN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADC2EN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADC3EN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIOEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI1EN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI4EN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYSCFGEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM9EN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM10EN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM11EN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI5EN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI6EN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SAI1EN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LTDCEN", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AHB1LPENR", offset: 0x50, width: Width::W32, reset: 0x7E67_91FF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "GPIOALPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOBLPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOCLPEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIODLPEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOELPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOFLPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOGLPEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOHLPEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GPIOILPEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRCLPEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLITFLPEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SRAM1LPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SRAM2LPEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKPSRAMLPEN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SRAM3LPEN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMA1LPEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMA2LPEN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETHMACLPEN", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETHMACTXLPEN", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETHMACRXLPEN", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETHMACPTPLPEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OTGHSLPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OTGHSULPILPEN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AHB2LPENR", offset: 0x54, width: Width::W32, reset: 0x0000_00F1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DCMILPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CRYPLPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HASHLPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RNGLPEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OTGFSLPEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AHB3LPENR", offset: 0x58, width: Width::W32, reset: 0x0000_0001, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FMCLPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "APB1LPENR", offset: 0x60, width: Width::W32, reset: 0x36FE_C9FF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIM2LPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM3LPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM4LPEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM5LPEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM6LPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM7LPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM12LPEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM13LPEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM14LPEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WWDGLPEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI2LPEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI3LPEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USART2LPEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USART3LPEN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART4LPEN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART5LPEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C1LPEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C2LPEN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C3LPEN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAN1LPEN", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAN2LPEN", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWRLPEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DACLPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART7LPEN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UART8LPEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "APB2LPENR", offset: 0x64, width: Width::W32, reset: 0x0007_5F33, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIM1LPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM8LPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USART1LPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USART6LPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADC1LPEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADC2LPEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADC3LPEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDIOLPEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI1LPEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI4LPEN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYSCFGLPEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM9LPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM10LPEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIM11LPEN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI5LPEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPI6LPEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDCR", offset: 0x70, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LSEON", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSERDY", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSEBYP", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTCSEL0", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTCSEL1", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTCEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BDRST", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CSR", offset: 0x74, width: Width::W32, reset: 0x0E00_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LSION", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSIRDY", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RMVF", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BORRSTF", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PADRSTF", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PORRSTF", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SFTRSTF", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WDGRSTF", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WWDGRSTF", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LPWRRSTF", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SSCGR", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MODPER", bit: 0, width: 13, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INCSTEP", bit: 13, width: 15, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPREADSEL", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSCGEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PLLI2SCFGR", offset: 0x84, width: Width::W32, reset: 0x2000_3000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PLLI2SNx", bit: 6, width: 9, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLI2SRx", bit: 28, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PLLSAICFGR", offset: 0x88, width: Width::W32, reset: 0x2400_3000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PLLSAIN", bit: 6, width: 9, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLSAIQ", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLSAIR", bit: 28, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DCKCFGR", offset: 0x8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PLLI2SDIVQ", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLSAIDIVQ", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLLSAIDIVR", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SAI1ASRC", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SAI1BSRC", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMPRE", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];