rigless 0.0.5

// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `GPIOA` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `MODER` at offset `0x0`, resets to `0xA800_0000`, read-write.
    Moder = 0,
    /// `OTYPER` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Otyper = 1,
    /// `OSPEEDR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Ospeedr = 2,
    /// `PUPDR` at offset `0xC`, resets to `0x6400_0000`, read-write.
    Pupdr = 3,
    /// `IDR` at offset `0x10`, resets to `0x0000_0000`, read-only.
    Idr = 4,
    /// `ODR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Odr = 5,
    /// `BSRR` at offset `0x18`, resets to `0x0000_0000`, write-only.
    Bsrr = 6,
    /// `LCKR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Lckr = 7,
    /// `AFRL` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Afrl = 8,
    /// `AFRH` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Afrh = 9,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 10] = [Self::Moder, Self::Otyper, Self::Ospeedr, Self::Pupdr, Self::Idr, Self::Odr, Self::Bsrr, Self::Lckr, Self::Afrl, Self::Afrh];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `MODER`.
pub mod moder {
    use super::FieldSpec;
    /// `MODER0`, bits 0..=1.
    pub const MODER0: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `MODER1`, bits 2..=3.
    pub const MODER1: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `MODER2`, bits 4..=5.
    pub const MODER2: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `MODER3`, bits 6..=7.
    pub const MODER3: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `MODER4`, bits 8..=9.
    pub const MODER4: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `MODER5`, bits 10..=11.
    pub const MODER5: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `MODER6`, bits 12..=13.
    pub const MODER6: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `MODER7`, bits 14..=15.
    pub const MODER7: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `MODER8`, bits 16..=17.
    pub const MODER8: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `MODER9`, bits 18..=19.
    pub const MODER9: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `MODER10`, bits 20..=21.
    pub const MODER10: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `MODER11`, bits 22..=23.
    pub const MODER11: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `MODER12`, bits 24..=25.
    pub const MODER12: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `MODER13`, bits 26..=27.
    pub const MODER13: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `MODER14`, bits 28..=29.
    pub const MODER14: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `MODER15`, bits 30..=31.
    pub const MODER15: &FieldSpec = &super::REGISTERS[0].fields[15];
}

/// The fields of `OTYPER`.
pub mod otyper {
    use super::FieldSpec;
    /// `OT0`, bit 0.
    pub const OT0: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `OT1`, bit 1.
    pub const OT1: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `OT2`, bit 2.
    pub const OT2: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `OT3`, bit 3.
    pub const OT3: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `OT4`, bit 4.
    pub const OT4: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `OT5`, bit 5.
    pub const OT5: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `OT6`, bit 6.
    pub const OT6: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `OT7`, bit 7.
    pub const OT7: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `OT8`, bit 8.
    pub const OT8: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `OT9`, bit 9.
    pub const OT9: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `OT10`, bit 10.
    pub const OT10: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `OT11`, bit 11.
    pub const OT11: &FieldSpec = &super::REGISTERS[1].fields[11];
    /// `OT12`, bit 12.
    pub const OT12: &FieldSpec = &super::REGISTERS[1].fields[12];
    /// `OT13`, bit 13.
    pub const OT13: &FieldSpec = &super::REGISTERS[1].fields[13];
    /// `OT14`, bit 14.
    pub const OT14: &FieldSpec = &super::REGISTERS[1].fields[14];
    /// `OT15`, bit 15.
    pub const OT15: &FieldSpec = &super::REGISTERS[1].fields[15];
}

/// The fields of `OSPEEDR`.
pub mod ospeedr {
    use super::FieldSpec;
    /// `OSPEEDR0`, bits 0..=1.
    pub const OSPEEDR0: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `OSPEEDR1`, bits 2..=3.
    pub const OSPEEDR1: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `OSPEEDR2`, bits 4..=5.
    pub const OSPEEDR2: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `OSPEEDR3`, bits 6..=7.
    pub const OSPEEDR3: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `OSPEEDR4`, bits 8..=9.
    pub const OSPEEDR4: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `OSPEEDR5`, bits 10..=11.
    pub const OSPEEDR5: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `OSPEEDR6`, bits 12..=13.
    pub const OSPEEDR6: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `OSPEEDR7`, bits 14..=15.
    pub const OSPEEDR7: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `OSPEEDR8`, bits 16..=17.
    pub const OSPEEDR8: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `OSPEEDR9`, bits 18..=19.
    pub const OSPEEDR9: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `OSPEEDR10`, bits 20..=21.
    pub const OSPEEDR10: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `OSPEEDR11`, bits 22..=23.
    pub const OSPEEDR11: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `OSPEEDR12`, bits 24..=25.
    pub const OSPEEDR12: &FieldSpec = &super::REGISTERS[2].fields[12];
    /// `OSPEEDR13`, bits 26..=27.
    pub const OSPEEDR13: &FieldSpec = &super::REGISTERS[2].fields[13];
    /// `OSPEEDR14`, bits 28..=29.
    pub const OSPEEDR14: &FieldSpec = &super::REGISTERS[2].fields[14];
    /// `OSPEEDR15`, bits 30..=31.
    pub const OSPEEDR15: &FieldSpec = &super::REGISTERS[2].fields[15];
}

/// The fields of `PUPDR`.
pub mod pupdr {
    use super::FieldSpec;
    /// `PUPDR0`, bits 0..=1.
    pub const PUPDR0: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `PUPDR1`, bits 2..=3.
    pub const PUPDR1: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `PUPDR2`, bits 4..=5.
    pub const PUPDR2: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `PUPDR3`, bits 6..=7.
    pub const PUPDR3: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `PUPDR4`, bits 8..=9.
    pub const PUPDR4: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `PUPDR5`, bits 10..=11.
    pub const PUPDR5: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `PUPDR6`, bits 12..=13.
    pub const PUPDR6: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `PUPDR7`, bits 14..=15.
    pub const PUPDR7: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `PUPDR8`, bits 16..=17.
    pub const PUPDR8: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `PUPDR9`, bits 18..=19.
    pub const PUPDR9: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `PUPDR10`, bits 20..=21.
    pub const PUPDR10: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `PUPDR11`, bits 22..=23.
    pub const PUPDR11: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `PUPDR12`, bits 24..=25.
    pub const PUPDR12: &FieldSpec = &super::REGISTERS[3].fields[12];
    /// `PUPDR13`, bits 26..=27.
    pub const PUPDR13: &FieldSpec = &super::REGISTERS[3].fields[13];
    /// `PUPDR14`, bits 28..=29.
    pub const PUPDR14: &FieldSpec = &super::REGISTERS[3].fields[14];
    /// `PUPDR15`, bits 30..=31.
    pub const PUPDR15: &FieldSpec = &super::REGISTERS[3].fields[15];
}

/// The fields of `IDR`.
pub mod idr {
    use super::FieldSpec;
    /// `IDR0`, bit 0.
    pub const IDR0: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `IDR1`, bit 1.
    pub const IDR1: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `IDR2`, bit 2.
    pub const IDR2: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `IDR3`, bit 3.
    pub const IDR3: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `IDR4`, bit 4.
    pub const IDR4: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `IDR5`, bit 5.
    pub const IDR5: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `IDR6`, bit 6.
    pub const IDR6: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `IDR7`, bit 7.
    pub const IDR7: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `IDR8`, bit 8.
    pub const IDR8: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `IDR9`, bit 9.
    pub const IDR9: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `IDR10`, bit 10.
    pub const IDR10: &FieldSpec = &super::REGISTERS[4].fields[10];
    /// `IDR11`, bit 11.
    pub const IDR11: &FieldSpec = &super::REGISTERS[4].fields[11];
    /// `IDR12`, bit 12.
    pub const IDR12: &FieldSpec = &super::REGISTERS[4].fields[12];
    /// `IDR13`, bit 13.
    pub const IDR13: &FieldSpec = &super::REGISTERS[4].fields[13];
    /// `IDR14`, bit 14.
    pub const IDR14: &FieldSpec = &super::REGISTERS[4].fields[14];
    /// `IDR15`, bit 15.
    pub const IDR15: &FieldSpec = &super::REGISTERS[4].fields[15];
}

/// The fields of `ODR`.
pub mod odr {
    use super::FieldSpec;
    /// `ODR0`, bit 0.
    pub const ODR0: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `ODR1`, bit 1.
    pub const ODR1: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `ODR2`, bit 2.
    pub const ODR2: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `ODR3`, bit 3.
    pub const ODR3: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `ODR4`, bit 4.
    pub const ODR4: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `ODR5`, bit 5.
    pub const ODR5: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `ODR6`, bit 6.
    pub const ODR6: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `ODR7`, bit 7.
    pub const ODR7: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `ODR8`, bit 8.
    pub const ODR8: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `ODR9`, bit 9.
    pub const ODR9: &FieldSpec = &super::REGISTERS[5].fields[9];
    /// `ODR10`, bit 10.
    pub const ODR10: &FieldSpec = &super::REGISTERS[5].fields[10];
    /// `ODR11`, bit 11.
    pub const ODR11: &FieldSpec = &super::REGISTERS[5].fields[11];
    /// `ODR12`, bit 12.
    pub const ODR12: &FieldSpec = &super::REGISTERS[5].fields[12];
    /// `ODR13`, bit 13.
    pub const ODR13: &FieldSpec = &super::REGISTERS[5].fields[13];
    /// `ODR14`, bit 14.
    pub const ODR14: &FieldSpec = &super::REGISTERS[5].fields[14];
    /// `ODR15`, bit 15.
    pub const ODR15: &FieldSpec = &super::REGISTERS[5].fields[15];
}

/// The fields of `BSRR`.
pub mod bsrr {
    use super::FieldSpec;
    /// `BS0`, bit 0.
    pub const BS0: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `BS1`, bit 1.
    pub const BS1: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `BS2`, bit 2.
    pub const BS2: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `BS3`, bit 3.
    pub const BS3: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `BS4`, bit 4.
    pub const BS4: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `BS5`, bit 5.
    pub const BS5: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `BS6`, bit 6.
    pub const BS6: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `BS7`, bit 7.
    pub const BS7: &FieldSpec = &super::REGISTERS[6].fields[7];
    /// `BS8`, bit 8.
    pub const BS8: &FieldSpec = &super::REGISTERS[6].fields[8];
    /// `BS9`, bit 9.
    pub const BS9: &FieldSpec = &super::REGISTERS[6].fields[9];
    /// `BS10`, bit 10.
    pub const BS10: &FieldSpec = &super::REGISTERS[6].fields[10];
    /// `BS11`, bit 11.
    pub const BS11: &FieldSpec = &super::REGISTERS[6].fields[11];
    /// `BS12`, bit 12.
    pub const BS12: &FieldSpec = &super::REGISTERS[6].fields[12];
    /// `BS13`, bit 13.
    pub const BS13: &FieldSpec = &super::REGISTERS[6].fields[13];
    /// `BS14`, bit 14.
    pub const BS14: &FieldSpec = &super::REGISTERS[6].fields[14];
    /// `BS15`, bit 15.
    pub const BS15: &FieldSpec = &super::REGISTERS[6].fields[15];
    /// `BR0`, bit 16.
    pub const BR0: &FieldSpec = &super::REGISTERS[6].fields[16];
    /// `BR1`, bit 17.
    pub const BR1: &FieldSpec = &super::REGISTERS[6].fields[17];
    /// `BR2`, bit 18.
    pub const BR2: &FieldSpec = &super::REGISTERS[6].fields[18];
    /// `BR3`, bit 19.
    pub const BR3: &FieldSpec = &super::REGISTERS[6].fields[19];
    /// `BR4`, bit 20.
    pub const BR4: &FieldSpec = &super::REGISTERS[6].fields[20];
    /// `BR5`, bit 21.
    pub const BR5: &FieldSpec = &super::REGISTERS[6].fields[21];
    /// `BR6`, bit 22.
    pub const BR6: &FieldSpec = &super::REGISTERS[6].fields[22];
    /// `BR7`, bit 23.
    pub const BR7: &FieldSpec = &super::REGISTERS[6].fields[23];
    /// `BR8`, bit 24.
    pub const BR8: &FieldSpec = &super::REGISTERS[6].fields[24];
    /// `BR9`, bit 25.
    pub const BR9: &FieldSpec = &super::REGISTERS[6].fields[25];
    /// `BR10`, bit 26.
    pub const BR10: &FieldSpec = &super::REGISTERS[6].fields[26];
    /// `BR11`, bit 27.
    pub const BR11: &FieldSpec = &super::REGISTERS[6].fields[27];
    /// `BR12`, bit 28.
    pub const BR12: &FieldSpec = &super::REGISTERS[6].fields[28];
    /// `BR13`, bit 29.
    pub const BR13: &FieldSpec = &super::REGISTERS[6].fields[29];
    /// `BR14`, bit 30.
    pub const BR14: &FieldSpec = &super::REGISTERS[6].fields[30];
    /// `BR15`, bit 31.
    pub const BR15: &FieldSpec = &super::REGISTERS[6].fields[31];
}

/// The fields of `LCKR`.
pub mod lckr {
    use super::FieldSpec;
    /// `LCK0`, bit 0.
    pub const LCK0: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `LCK1`, bit 1.
    pub const LCK1: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `LCK2`, bit 2.
    pub const LCK2: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `LCK3`, bit 3.
    pub const LCK3: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `LCK4`, bit 4.
    pub const LCK4: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `LCK5`, bit 5.
    pub const LCK5: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `LCK6`, bit 6.
    pub const LCK6: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `LCK7`, bit 7.
    pub const LCK7: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `LCK8`, bit 8.
    pub const LCK8: &FieldSpec = &super::REGISTERS[7].fields[8];
    /// `LCK9`, bit 9.
    pub const LCK9: &FieldSpec = &super::REGISTERS[7].fields[9];
    /// `LCK10`, bit 10.
    pub const LCK10: &FieldSpec = &super::REGISTERS[7].fields[10];
    /// `LCK11`, bit 11.
    pub const LCK11: &FieldSpec = &super::REGISTERS[7].fields[11];
    /// `LCK12`, bit 12.
    pub const LCK12: &FieldSpec = &super::REGISTERS[7].fields[12];
    /// `LCK13`, bit 13.
    pub const LCK13: &FieldSpec = &super::REGISTERS[7].fields[13];
    /// `LCK14`, bit 14.
    pub const LCK14: &FieldSpec = &super::REGISTERS[7].fields[14];
    /// `LCK15`, bit 15.
    pub const LCK15: &FieldSpec = &super::REGISTERS[7].fields[15];
    /// `LCKK`, bit 16.
    pub const LCKK: &FieldSpec = &super::REGISTERS[7].fields[16];
}

/// The fields of `AFRL`.
pub mod afrl {
    use super::FieldSpec;
    /// `AFRL0`, bits 0..=3.
    pub const AFRL0: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `AFRL1`, bits 4..=7.
    pub const AFRL1: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `AFRL2`, bits 8..=11.
    pub const AFRL2: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `AFRL3`, bits 12..=15.
    pub const AFRL3: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `AFRL4`, bits 16..=19.
    pub const AFRL4: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `AFRL5`, bits 20..=23.
    pub const AFRL5: &FieldSpec = &super::REGISTERS[8].fields[5];
    /// `AFRL6`, bits 24..=27.
    pub const AFRL6: &FieldSpec = &super::REGISTERS[8].fields[6];
    /// `AFRL7`, bits 28..=31.
    pub const AFRL7: &FieldSpec = &super::REGISTERS[8].fields[7];
}

/// The fields of `AFRH`.
pub mod afrh {
    use super::FieldSpec;
    /// `AFRH8`, bits 0..=3.
    pub const AFRH8: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `AFRH9`, bits 4..=7.
    pub const AFRH9: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `AFRH10`, bits 8..=11.
    pub const AFRH10: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `AFRH11`, bits 12..=15.
    pub const AFRH11: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `AFRH12`, bits 16..=19.
    pub const AFRH12: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `AFRH13`, bits 20..=23.
    pub const AFRH13: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `AFRH14`, bits 24..=27.
    pub const AFRH14: &FieldSpec = &super::REGISTERS[9].fields[6];
    /// `AFRH15`, bits 28..=31.
    pub const AFRH15: &FieldSpec = &super::REGISTERS[9].fields[7];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 10] = [
    RegisterSpec { name: "MODER", offset: 0x0, width: Width::W32, reset: 0xA800_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MODER0", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER1", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER2", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER3", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER4", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER5", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER6", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER7", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER8", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER9", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER10", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER11", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER12", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER13", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER14", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODER15", bit: 30, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OTYPER", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OT0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OT15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OSPEEDR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OSPEEDR0", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR1", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR2", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR3", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR4", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR5", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR6", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR7", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR8", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR9", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR10", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR11", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR12", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR13", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR14", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSPEEDR15", bit: 30, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PUPDR", offset: 0xC, width: Width::W32, reset: 0x6400_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PUPDR0", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR1", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR2", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR3", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR4", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR5", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR6", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR7", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR8", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR9", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR10", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR11", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR12", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR13", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR14", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PUPDR15", bit: 30, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IDR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IDR0", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR1", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR2", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR3", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR4", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR5", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR6", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR7", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR8", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR9", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR10", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR11", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR12", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR13", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR14", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDR15", bit: 15, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ODR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ODR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BSRR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BS0", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS1", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS2", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS3", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS4", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS5", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS6", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS7", bit: 7, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS8", bit: 8, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS9", bit: 9, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS10", bit: 10, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS11", bit: 11, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS12", bit: 12, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS13", bit: 13, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS14", bit: 14, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BS15", bit: 15, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR0", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR1", bit: 17, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR2", bit: 18, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR3", bit: 19, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR4", bit: 20, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR5", bit: 21, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR6", bit: 22, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR7", bit: 23, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR8", bit: 24, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR9", bit: 25, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR10", bit: 26, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR11", bit: 27, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR12", bit: 28, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR13", bit: 29, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR14", bit: 30, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BR15", bit: 31, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "LCKR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LCK0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCK15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LCKK", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AFRL", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AFRL0", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRL1", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRL2", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRL3", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRL4", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRL5", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRL6", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRL7", bit: 28, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AFRH", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AFRH8", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRH9", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRH10", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRH11", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRH12", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRH13", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRH14", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFRH15", bit: 28, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];