rigless 0.0.5

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model, and unit of virtual time in Rust; a fork of QEMU is built in and executes the instructions
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `PWR` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR` at offset `0x0`, resets to `0x0000_C000`, read-write.
    Cr = 0,
    /// `CSR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Csr = 1,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 2] = [Self::Cr, Self::Csr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `LPDS`, bit 0.
    pub const LPDS: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `PDDS`, bit 1.
    pub const PDDS: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `CWUF`, bit 2.
    pub const CWUF: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `CSBF`, bit 3.
    pub const CSBF: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `PVDE`, bit 4.
    pub const PVDE: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `PLS`, bits 5..=7.
    pub const PLS: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `DBP`, bit 8.
    pub const DBP: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `FPDS`, bit 9.
    pub const FPDS: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `LPLVDS`, bit 10.
    pub const LPLVDS: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `MRLVDS`, bit 11.
    pub const MRLVDS: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `ADCDC1`, bit 13.
    pub const ADCDC1: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `VOS`, bits 14..=15.
    pub const VOS: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `ODEN`, bit 16.
    pub const ODEN: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `ODSWEN`, bit 17.
    pub const ODSWEN: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `UDEN`, bits 18..=19.
    pub const UDEN: &FieldSpec = &super::REGISTERS[0].fields[14];
}

/// The fields of `CSR`.
pub mod csr {
    use super::FieldSpec;
    /// `WUF`, bit 0, read-only.
    pub const WUF: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `SBF`, bit 1, read-only.
    pub const SBF: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `PVDO`, bit 2, read-only.
    pub const PVDO: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `BRR`, bit 3, read-only.
    pub const BRR: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `EWUP`, bit 8.
    pub const EWUP: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `BRE`, bit 9.
    pub const BRE: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `VOSRDY`, bit 14.
    pub const VOSRDY: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `ODRDY`, bit 16, read-only.
    pub const ODRDY: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `ODSWRDY`, bit 17, read-only.
    pub const ODSWRDY: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `UDRDY`, bits 18..=19.
    pub const UDRDY: &FieldSpec = &super::REGISTERS[1].fields[9];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 2] = [
    RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_C000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LPDS", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PDDS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CWUF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSBF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PVDE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLS", bit: 5, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBP", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FPDS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LPLVDS", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MRLVDS", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADCDC1", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VOS", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODSWEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDEN", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CSR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WUF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PVDO", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BRR", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EWUP", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BRE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VOSRDY", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODRDY", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODSWRDY", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDRDY", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];