rigless 0.0.5

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model, and unit of virtual time in Rust; a fork of QEMU is built in and executes the instructions
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `DCMI` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr = 0,
    /// `SR` at offset `0x4`, resets to `0x0000_0000`, read-only.
    Sr = 1,
    /// `RIS` at offset `0x8`, resets to `0x0000_0000`, read-only.
    Ris = 2,
    /// `IER` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Ier = 3,
    /// `MIS` at offset `0x10`, resets to `0x0000_0000`, read-only.
    Mis = 4,
    /// `ICR` at offset `0x14`, resets to `0x0000_0000`, write-only.
    Icr = 5,
    /// `ESCR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Escr = 6,
    /// `ESUR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Esur = 7,
    /// `CWSTRT` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Cwstrt = 8,
    /// `CWSIZE` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Cwsize = 9,
    /// `DR` at offset `0x28`, resets to `0x0000_0000`, read-only.
    Dr = 10,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 11] = [Self::Cr, Self::Sr, Self::Ris, Self::Ier, Self::Mis, Self::Icr, Self::Escr, Self::Esur, Self::Cwstrt, Self::Cwsize, Self::Dr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `CAPTURE`, bit 0.
    pub const CAPTURE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `CM`, bit 1.
    pub const CM: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `CROP`, bit 2.
    pub const CROP: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `JPEG`, bit 3.
    pub const JPEG: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `ESS`, bit 4.
    pub const ESS: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `PCKPOL`, bit 5.
    pub const PCKPOL: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `HSPOL`, bit 6.
    pub const HSPOL: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `VSPOL`, bit 7.
    pub const VSPOL: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `FCRC`, bits 8..=9.
    pub const FCRC: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `EDM`, bits 10..=11.
    pub const EDM: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `ENABLE`, bit 14.
    pub const ENABLE: &FieldSpec = &super::REGISTERS[0].fields[10];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `HSYNC`, bit 0.
    pub const HSYNC: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `VSYNC`, bit 1.
    pub const VSYNC: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `FNE`, bit 2.
    pub const FNE: &FieldSpec = &super::REGISTERS[1].fields[2];
}

/// The fields of `RIS`.
pub mod ris {
    use super::FieldSpec;
    /// `FRAME_RIS`, bit 0.
    pub const FRAME_RIS: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `OVR_RIS`, bit 1.
    pub const OVR_RIS: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `ERR_RIS`, bit 2.
    pub const ERR_RIS: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `VSYNC_RIS`, bit 3.
    pub const VSYNC_RIS: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `LINE_RIS`, bit 4.
    pub const LINE_RIS: &FieldSpec = &super::REGISTERS[2].fields[4];
}

/// The fields of `IER`.
pub mod ier {
    use super::FieldSpec;
    /// `FRAME_IE`, bit 0.
    pub const FRAME_IE: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `OVR_IE`, bit 1.
    pub const OVR_IE: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `ERR_IE`, bit 2.
    pub const ERR_IE: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `VSYNC_IE`, bit 3.
    pub const VSYNC_IE: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `LINE_IE`, bit 4.
    pub const LINE_IE: &FieldSpec = &super::REGISTERS[3].fields[4];
}

/// The fields of `MIS`.
pub mod mis {
    use super::FieldSpec;
    /// `FRAME_MIS`, bit 0.
    pub const FRAME_MIS: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `OVR_MIS`, bit 1.
    pub const OVR_MIS: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `ERR_MIS`, bit 2.
    pub const ERR_MIS: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `VSYNC_MIS`, bit 3.
    pub const VSYNC_MIS: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `LINE_MIS`, bit 4.
    pub const LINE_MIS: &FieldSpec = &super::REGISTERS[4].fields[4];
}

/// The fields of `ICR`.
pub mod icr {
    use super::FieldSpec;
    /// `FRAME_ISC`, bit 0.
    pub const FRAME_ISC: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `OVR_ISC`, bit 1.
    pub const OVR_ISC: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `ERR_ISC`, bit 2.
    pub const ERR_ISC: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `VSYNC_ISC`, bit 3.
    pub const VSYNC_ISC: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `LINE_ISC`, bit 4.
    pub const LINE_ISC: &FieldSpec = &super::REGISTERS[5].fields[4];
}

/// The fields of `ESCR`.
pub mod escr {
    use super::FieldSpec;
    /// `FSC`, bits 0..=7.
    pub const FSC: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `LSC`, bits 8..=15.
    pub const LSC: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `LEC`, bits 16..=23.
    pub const LEC: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `FEC`, bits 24..=31.
    pub const FEC: &FieldSpec = &super::REGISTERS[6].fields[3];
}

/// The fields of `ESUR`.
pub mod esur {
    use super::FieldSpec;
    /// `FSU`, bits 0..=7.
    pub const FSU: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `LSU`, bits 8..=15.
    pub const LSU: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `LEU`, bits 16..=23.
    pub const LEU: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `FEU`, bits 24..=31.
    pub const FEU: &FieldSpec = &super::REGISTERS[7].fields[3];
}

/// The fields of `CWSTRT`.
pub mod cwstrt {
    use super::FieldSpec;
    /// `HOFFCNT`, bits 0..=13.
    pub const HOFFCNT: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `VST`, bits 16..=28.
    pub const VST: &FieldSpec = &super::REGISTERS[8].fields[1];
}

/// The fields of `CWSIZE`.
pub mod cwsize {
    use super::FieldSpec;
    /// `CAPCNT`, bits 0..=13.
    pub const CAPCNT: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `VLINE`, bits 16..=29.
    pub const VLINE: &FieldSpec = &super::REGISTERS[9].fields[1];
}

/// The fields of `DR`.
pub mod dr {
    use super::FieldSpec;
    /// `Byte0`, bits 0..=7.
    pub const BYTE0: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `Byte1`, bits 8..=15.
    pub const BYTE1: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `Byte2`, bits 16..=23.
    pub const BYTE2: &FieldSpec = &super::REGISTERS[10].fields[2];
    /// `Byte3`, bits 24..=31.
    pub const BYTE3: &FieldSpec = &super::REGISTERS[10].fields[3];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 11] = [
    RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CAPTURE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CM", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CROP", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JPEG", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ESS", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCKPOL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSPOL", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSPOL", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FCRC", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EDM", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ENABLE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HSYNC", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSYNC", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FNE", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RIS", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FRAME_RIS", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR_RIS", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERR_RIS", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSYNC_RIS", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LINE_RIS", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IER", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FRAME_IE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR_IE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERR_IE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSYNC_IE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LINE_IE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MIS", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FRAME_MIS", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR_MIS", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERR_MIS", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSYNC_MIS", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LINE_MIS", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ICR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FRAME_ISC", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR_ISC", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERR_ISC", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSYNC_ISC", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LINE_ISC", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ESCR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FSC", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSC", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LEC", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEC", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ESUR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FSU", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSU", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LEU", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEU", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CWSTRT", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HOFFCNT", bit: 0, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VST", bit: 16, width: 13, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CWSIZE", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CAPCNT", bit: 0, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VLINE", bit: 16, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "Byte0", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "Byte1", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "Byte2", bit: 16, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "Byte3", bit: 24, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];