rigless 0.0.5

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model, and unit of virtual time in Rust; a fork of QEMU is built in and executes the instructions
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `IWDG` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `KR` at offset `0x0`, resets to `0x0000_0000`, write-only.
    Kr = 0,
    /// `PR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Pr = 1,
    /// `RLR` at offset `0x8`, resets to `0x0000_0FFF`, read-write.
    Rlr = 2,
    /// `SR` at offset `0xC`, resets to `0x0000_0000`, read-only.
    Sr = 3,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 4] = [Self::Kr, Self::Pr, Self::Rlr, Self::Sr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `KR`.
pub mod kr {
    use super::FieldSpec;
    /// `KEY`, bits 0..=15.
    pub const KEY: &FieldSpec = &super::REGISTERS[0].fields[0];
}

/// The fields of `PR`.
pub mod pr {
    use super::FieldSpec;
    /// `PR`, bits 0..=2.
    pub const PR: &FieldSpec = &super::REGISTERS[1].fields[0];
}

/// The fields of `RLR`.
pub mod rlr {
    use super::FieldSpec;
    /// `RL`, bits 0..=11.
    pub const RL: &FieldSpec = &super::REGISTERS[2].fields[0];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `PVU`, bit 0.
    pub const PVU: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `RVU`, bit 1.
    pub const RVU: &FieldSpec = &super::REGISTERS[3].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 4] = [
    RegisterSpec { name: "KR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "KEY", bit: 0, width: 16, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PR", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RLR", offset: 0x8, width: Width::W32, reset: 0x0000_0FFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RL", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PVU", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RVU", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];