rigless 0.0.5

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model, and unit of virtual time in Rust; a fork of QEMU is built in and executes the instructions
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `ADC1` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `SR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Sr = 0,
    /// `CR1` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cr1 = 1,
    /// `CR2` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Cr2 = 2,
    /// `SMPR1` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Smpr1 = 3,
    /// `SMPR2` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Smpr2 = 4,
    /// `JOFR1` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Jofr1 = 5,
    /// `JOFR2` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Jofr2 = 6,
    /// `JOFR3` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Jofr3 = 7,
    /// `JOFR4` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Jofr4 = 8,
    /// `HTR` at offset `0x24`, resets to `0x0000_0FFF`, read-write.
    Htr = 9,
    /// `LTR` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Ltr = 10,
    /// `SQR1` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Sqr1 = 11,
    /// `SQR2` at offset `0x30`, resets to `0x0000_0000`, read-write.
    Sqr2 = 12,
    /// `SQR3` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Sqr3 = 13,
    /// `JSQR` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Jsqr = 14,
    /// `JDR1` at offset `0x3C`, resets to `0x0000_0000`, read-only.
    Jdr1 = 15,
    /// `JDR2` at offset `0x40`, resets to `0x0000_0000`, read-only.
    Jdr2 = 16,
    /// `JDR3` at offset `0x44`, resets to `0x0000_0000`, read-only.
    Jdr3 = 17,
    /// `JDR4` at offset `0x48`, resets to `0x0000_0000`, read-only.
    Jdr4 = 18,
    /// `DR` at offset `0x4C`, resets to `0x0000_0000`, read-only.
    Dr = 19,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 20] = [Self::Sr, Self::Cr1, Self::Cr2, Self::Smpr1, Self::Smpr2, Self::Jofr1, Self::Jofr2, Self::Jofr3, Self::Jofr4, Self::Htr, Self::Ltr, Self::Sqr1, Self::Sqr2, Self::Sqr3, Self::Jsqr, Self::Jdr1, Self::Jdr2, Self::Jdr3, Self::Jdr4, Self::Dr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `AWD`, bit 0.
    pub const AWD: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `EOC`, bit 1.
    pub const EOC: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `JEOC`, bit 2.
    pub const JEOC: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `JSTRT`, bit 3.
    pub const JSTRT: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `STRT`, bit 4.
    pub const STRT: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `OVR`, bit 5.
    pub const OVR: &FieldSpec = &super::REGISTERS[0].fields[5];
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `AWDCH`, bits 0..=4.
    pub const AWDCH: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `EOCIE`, bit 5.
    pub const EOCIE: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `AWDIE`, bit 6.
    pub const AWDIE: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `JEOCIE`, bit 7.
    pub const JEOCIE: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `SCAN`, bit 8.
    pub const SCAN: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `AWDSGL`, bit 9.
    pub const AWDSGL: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `JAUTO`, bit 10.
    pub const JAUTO: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `DISCEN`, bit 11.
    pub const DISCEN: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `JDISCEN`, bit 12.
    pub const JDISCEN: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `DISCNUM`, bits 13..=15.
    pub const DISCNUM: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `JAWDEN`, bit 22.
    pub const JAWDEN: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `AWDEN`, bit 23.
    pub const AWDEN: &FieldSpec = &super::REGISTERS[1].fields[11];
    /// `RES`, bits 24..=25.
    pub const RES: &FieldSpec = &super::REGISTERS[1].fields[12];
    /// `OVRIE`, bit 26.
    pub const OVRIE: &FieldSpec = &super::REGISTERS[1].fields[13];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `ADON`, bit 0.
    pub const ADON: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `CONT`, bit 1.
    pub const CONT: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `DMA`, bit 8.
    pub const DMA: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `DDS`, bit 9.
    pub const DDS: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `EOCS`, bit 10.
    pub const EOCS: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `ALIGN`, bit 11.
    pub const ALIGN: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `JEXTSEL`, bits 16..=19.
    pub const JEXTSEL: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `JEXTEN`, bits 20..=21.
    pub const JEXTEN: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `JSWSTART`, bit 22.
    pub const JSWSTART: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `EXTSEL`, bits 24..=27.
    pub const EXTSEL: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `EXTEN`, bits 28..=29.
    pub const EXTEN: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `SWSTART`, bit 30.
    pub const SWSTART: &FieldSpec = &super::REGISTERS[2].fields[11];
}

/// The fields of `SMPR1`.
pub mod smpr1 {
    use super::FieldSpec;
    /// `SMPx_x`, bits 0..=31.
    pub const SMPX_X: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `SMPR2`.
pub mod smpr2 {
    use super::FieldSpec;
    /// `SMPx_x`, bits 0..=31.
    pub const SMPX_X: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `JOFR1`.
pub mod jofr1 {
    use super::FieldSpec;
    /// `JOFFSET1`, bits 0..=11.
    pub const JOFFSET1: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `JOFR2`.
pub mod jofr2 {
    use super::FieldSpec;
    /// `JOFFSET2`, bits 0..=11.
    pub const JOFFSET2: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `JOFR3`.
pub mod jofr3 {
    use super::FieldSpec;
    /// `JOFFSET3`, bits 0..=11.
    pub const JOFFSET3: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `JOFR4`.
pub mod jofr4 {
    use super::FieldSpec;
    /// `JOFFSET4`, bits 0..=11.
    pub const JOFFSET4: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `HTR`.
pub mod htr {
    use super::FieldSpec;
    /// `HT`, bits 0..=11.
    pub const HT: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `LTR`.
pub mod ltr {
    use super::FieldSpec;
    /// `LT`, bits 0..=11.
    pub const LT: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `SQR1`.
pub mod sqr1 {
    use super::FieldSpec;
    /// `SQ13`, bits 0..=4.
    pub const SQ13: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `SQ14`, bits 5..=9.
    pub const SQ14: &FieldSpec = &super::REGISTERS[11].fields[1];
    /// `SQ15`, bits 10..=14.
    pub const SQ15: &FieldSpec = &super::REGISTERS[11].fields[2];
    /// `SQ16`, bits 15..=19.
    pub const SQ16: &FieldSpec = &super::REGISTERS[11].fields[3];
    /// `L`, bits 20..=23.
    pub const L: &FieldSpec = &super::REGISTERS[11].fields[4];
}

/// The fields of `SQR2`.
pub mod sqr2 {
    use super::FieldSpec;
    /// `SQ7`, bits 0..=4.
    pub const SQ7: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `SQ8`, bits 5..=9.
    pub const SQ8: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `SQ9`, bits 10..=14.
    pub const SQ9: &FieldSpec = &super::REGISTERS[12].fields[2];
    /// `SQ10`, bits 15..=19.
    pub const SQ10: &FieldSpec = &super::REGISTERS[12].fields[3];
    /// `SQ11`, bits 20..=24.
    pub const SQ11: &FieldSpec = &super::REGISTERS[12].fields[4];
    /// `SQ12`, bits 25..=29.
    pub const SQ12: &FieldSpec = &super::REGISTERS[12].fields[5];
}

/// The fields of `SQR3`.
pub mod sqr3 {
    use super::FieldSpec;
    /// `SQ1`, bits 0..=4.
    pub const SQ1: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `SQ2`, bits 5..=9.
    pub const SQ2: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `SQ3`, bits 10..=14.
    pub const SQ3: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `SQ4`, bits 15..=19.
    pub const SQ4: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `SQ5`, bits 20..=24.
    pub const SQ5: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `SQ6`, bits 25..=29.
    pub const SQ6: &FieldSpec = &super::REGISTERS[13].fields[5];
}

/// The fields of `JSQR`.
pub mod jsqr {
    use super::FieldSpec;
    /// `JSQ1`, bits 0..=4.
    pub const JSQ1: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `JSQ2`, bits 5..=9.
    pub const JSQ2: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `JSQ3`, bits 10..=14.
    pub const JSQ3: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `JSQ4`, bits 15..=19.
    pub const JSQ4: &FieldSpec = &super::REGISTERS[14].fields[3];
    /// `JL`, bits 20..=21.
    pub const JL: &FieldSpec = &super::REGISTERS[14].fields[4];
}

/// The fields of `JDR1`.
pub mod jdr1 {
    use super::FieldSpec;
    /// `JDATA`, bits 0..=15.
    pub const JDATA: &FieldSpec = &super::REGISTERS[15].fields[0];
}

/// The fields of `JDR2`.
pub mod jdr2 {
    use super::FieldSpec;
    /// `JDATA`, bits 0..=15.
    pub const JDATA: &FieldSpec = &super::REGISTERS[16].fields[0];
}

/// The fields of `JDR3`.
pub mod jdr3 {
    use super::FieldSpec;
    /// `JDATA`, bits 0..=15.
    pub const JDATA: &FieldSpec = &super::REGISTERS[17].fields[0];
}

/// The fields of `JDR4`.
pub mod jdr4 {
    use super::FieldSpec;
    /// `JDATA`, bits 0..=15.
    pub const JDATA: &FieldSpec = &super::REGISTERS[18].fields[0];
}

/// The fields of `DR`.
pub mod dr {
    use super::FieldSpec;
    /// `DATA`, bits 0..=15.
    pub const DATA: &FieldSpec = &super::REGISTERS[19].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 20] = [
    RegisterSpec { name: "SR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AWD", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOC", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOC", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSTRT", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STRT", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR1", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AWDCH", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOCIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCAN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDSGL", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JAUTO", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DISCEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JDISCEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DISCNUM", bit: 13, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JAWDEN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDEN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RES", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVRIE", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADON", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CONT", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMA", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DDS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOCS", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALIGN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTSEL", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTEN", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSWSTART", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTSEL", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTEN", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWSTART", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SMPR1", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SMPx_x", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SMPR2", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SMPx_x", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JOFR1", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JOFFSET1", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JOFR2", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JOFFSET2", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JOFR3", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JOFFSET3", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JOFR4", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JOFFSET4", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HTR", offset: 0x24, width: Width::W32, reset: 0x0000_0FFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HT", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "LTR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LT", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SQR1", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SQ13", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ14", bit: 5, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ15", bit: 10, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ16", bit: 15, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "L", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SQR2", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SQ7", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ8", bit: 5, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ9", bit: 10, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ10", bit: 15, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ11", bit: 20, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ12", bit: 25, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SQR3", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SQ1", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ2", bit: 5, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ3", bit: 10, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ4", bit: 15, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ5", bit: 20, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ6", bit: 25, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JSQR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JSQ1", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSQ2", bit: 5, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSQ3", bit: 10, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSQ4", bit: 15, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JL", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JDR1", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JDR2", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JDR3", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JDR4", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];