rigless 0.0.5

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model, and unit of virtual time in Rust; a fork of QEMU is built in and executes the instructions
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
//! Registers of `DMA2D` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name; a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `DMA2D_CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Dma2dCr = 0,
    /// `DMA2D_ISR` at offset `0x4`, resets to `0x0000_0000`, read-only.
    Dma2dIsr = 1,
    /// `DMA2D_IFCR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Dma2dIfcr = 2,
    /// `DMA2D_FGMAR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Dma2dFgmar = 3,
    /// `DMA2D_FGOR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Dma2dFgor = 4,
    /// `DMA2D_BGMAR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Dma2dBgmar = 5,
    /// `DMA2D_BGOR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Dma2dBgor = 6,
    /// `DMA2D_FGPFCCR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Dma2dFgpfccr = 7,
    /// `DMA2D_FGCOLR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Dma2dFgcolr = 8,
    /// `DMA2D_BGPFCCR` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Dma2dBgpfccr = 9,
    /// `DMA2D_BGCOLR` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Dma2dBgcolr = 10,
    /// `DMA2D_FGCMAR` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Dma2dFgcmar = 11,
    /// `DMA2D_BGCMAR` at offset `0x30`, resets to `0x0000_0000`, read-write.
    Dma2dBgcmar = 12,
    /// `DMA2D_OPFCCR` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Dma2dOpfccr = 13,
    /// `DMA2D_OCOLR` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Dma2dOcolr = 14,
    /// `DMA2D_OMAR` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    Dma2dOmar = 15,
    /// `DMA2D_OOR` at offset `0x40`, resets to `0x0000_0000`, read-write.
    Dma2dOor = 16,
    /// `DMA2D_NLR` at offset `0x44`, resets to `0x0000_0000`, read-write.
    Dma2dNlr = 17,
    /// `DMA2D_LWR` at offset `0x48`, resets to `0x0000_0000`, read-write.
    Dma2dLwr = 18,
    /// `DMA2D_AMTCR` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    Dma2dAmtcr = 19,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 20] = [Self::Dma2dCr, Self::Dma2dIsr, Self::Dma2dIfcr, Self::Dma2dFgmar, Self::Dma2dFgor, Self::Dma2dBgmar, Self::Dma2dBgor, Self::Dma2dFgpfccr, Self::Dma2dFgcolr, Self::Dma2dBgpfccr, Self::Dma2dBgcolr, Self::Dma2dFgcmar, Self::Dma2dBgcmar, Self::Dma2dOpfccr, Self::Dma2dOcolr, Self::Dma2dOmar, Self::Dma2dOor, Self::Dma2dNlr, Self::Dma2dLwr, Self::Dma2dAmtcr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `DMA2D_CR`.
pub mod dma2d_cr {
    use super::FieldSpec;
    /// `START`, bit 0.
    pub const START: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `SUSP`, bit 1.
    pub const SUSP: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `ABORT`, bit 2.
    pub const ABORT: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `TEIE`, bit 8.
    pub const TEIE: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `TCIE`, bit 9.
    pub const TCIE: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `TWIE`, bit 10.
    pub const TWIE: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `CAEIE`, bit 11.
    pub const CAEIE: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `CTCIE`, bit 12.
    pub const CTCIE: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `CEIE`, bit 13.
    pub const CEIE: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `MODE`, bits 16..=17.
    pub const MODE: &FieldSpec = &super::REGISTERS[0].fields[9];
}

/// The fields of `DMA2D_ISR`.
pub mod dma2d_isr {
    use super::FieldSpec;
    /// `TEIF`, bit 0.
    pub const TEIF: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `TCIF`, bit 1.
    pub const TCIF: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `TWIF`, bit 2.
    pub const TWIF: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `CAEIF`, bit 3.
    pub const CAEIF: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `CTCIF`, bit 4.
    pub const CTCIF: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `CEIF`, bit 5.
    pub const CEIF: &FieldSpec = &super::REGISTERS[1].fields[5];
}

/// The fields of `DMA2D_IFCR`.
pub mod dma2d_ifcr {
    use super::FieldSpec;
    /// `CTEIF`, bit 0.
    pub const CTEIF: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `CTCIF`, bit 1.
    pub const CTCIF: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `CTWIF`, bit 2.
    pub const CTWIF: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `CAECIF`, bit 3.
    pub const CAECIF: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `CCTCIF`, bit 4.
    pub const CCTCIF: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `CCEIF`, bit 5.
    pub const CCEIF: &FieldSpec = &super::REGISTERS[2].fields[5];
}

/// The fields of `DMA2D_FGMAR`.
pub mod dma2d_fgmar {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `DMA2D_FGOR`.
pub mod dma2d_fgor {
    use super::FieldSpec;
    /// `LO`, bits 0..=13.
    pub const LO: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `DMA2D_BGMAR`.
pub mod dma2d_bgmar {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `DMA2D_BGOR`.
pub mod dma2d_bgor {
    use super::FieldSpec;
    /// `LO`, bits 0..=13.
    pub const LO: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `DMA2D_FGPFCCR`.
pub mod dma2d_fgpfccr {
    use super::FieldSpec;
    /// `CM`, bits 0..=3.
    pub const CM: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `CCM`, bit 4.
    pub const CCM: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `START`, bit 5.
    pub const START: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `CS`, bits 8..=15.
    pub const CS: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `AM`, bits 16..=17.
    pub const AM: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `CSS`, bits 18..=19.
    pub const CSS: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `AI`, bit 20.
    pub const AI: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `RBS`, bit 21.
    pub const RBS: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `ALPHA`, bits 24..=31.
    pub const ALPHA: &FieldSpec = &super::REGISTERS[7].fields[8];
}

/// The fields of `DMA2D_FGCOLR`.
pub mod dma2d_fgcolr {
    use super::FieldSpec;
    /// `BLUE`, bits 0..=7.
    pub const BLUE: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `GREEN`, bits 8..=15.
    pub const GREEN: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `RED`, bits 16..=23.
    pub const RED: &FieldSpec = &super::REGISTERS[8].fields[2];
}

/// The fields of `DMA2D_BGPFCCR`.
pub mod dma2d_bgpfccr {
    use super::FieldSpec;
    /// `CM`, bits 0..=3.
    pub const CM: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `CCM`, bit 4.
    pub const CCM: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `START`, bit 5.
    pub const START: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `CS`, bits 8..=15.
    pub const CS: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `AM`, bits 16..=17.
    pub const AM: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `AI`, bit 20.
    pub const AI: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `RBS`, bit 21.
    pub const RBS: &FieldSpec = &super::REGISTERS[9].fields[6];
    /// `ALPHA`, bits 24..=31.
    pub const ALPHA: &FieldSpec = &super::REGISTERS[9].fields[7];
}

/// The fields of `DMA2D_BGCOLR`.
pub mod dma2d_bgcolr {
    use super::FieldSpec;
    /// `BLUE`, bits 0..=7.
    pub const BLUE: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `GREEN`, bits 8..=15.
    pub const GREEN: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `RED`, bits 16..=23.
    pub const RED: &FieldSpec = &super::REGISTERS[10].fields[2];
}

/// The fields of `DMA2D_FGCMAR`.
pub mod dma2d_fgcmar {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `DMA2D_BGCMAR`.
pub mod dma2d_bgcmar {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `DMA2D_OPFCCR`.
pub mod dma2d_opfccr {
    use super::FieldSpec;
    /// `CM`, bits 0..=2.
    pub const CM: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `AI`, bit 20.
    pub const AI: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `RBS`, bit 21.
    pub const RBS: &FieldSpec = &super::REGISTERS[13].fields[2];
}

/// The fields of `DMA2D_OCOLR`.
pub mod dma2d_ocolr {
    use super::FieldSpec;
    /// `BLUE`, bits 0..=7.
    pub const BLUE: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `GREEN`, bits 8..=15.
    pub const GREEN: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `RED`, bits 16..=23.
    pub const RED: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `ALPHA`, bits 24..=31.
    pub const ALPHA: &FieldSpec = &super::REGISTERS[14].fields[3];
}

/// The fields of `DMA2D_OMAR`.
pub mod dma2d_omar {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[15].fields[0];
}

/// The fields of `DMA2D_OOR`.
pub mod dma2d_oor {
    use super::FieldSpec;
    /// `LO`, bits 0..=13.
    pub const LO: &FieldSpec = &super::REGISTERS[16].fields[0];
}

/// The fields of `DMA2D_NLR`.
pub mod dma2d_nlr {
    use super::FieldSpec;
    /// `NL`, bits 0..=15.
    pub const NL: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `PL`, bits 16..=29.
    pub const PL: &FieldSpec = &super::REGISTERS[17].fields[1];
}

/// The fields of `DMA2D_LWR`.
pub mod dma2d_lwr {
    use super::FieldSpec;
    /// `LW`, bits 0..=15.
    pub const LW: &FieldSpec = &super::REGISTERS[18].fields[0];
}

/// The fields of `DMA2D_AMTCR`.
pub mod dma2d_amtcr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `DT`, bits 8..=15.
    pub const DT: &FieldSpec = &super::REGISTERS[19].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 20] = [
    RegisterSpec { name: "DMA2D_CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "START", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SUSP", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ABORT", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TWIE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAEIE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CEIE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_ISR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TEIF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TWIF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAEIF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CEIF", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_IFCR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CTEIF", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTWIF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAECIF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCTCIF", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCEIF", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_FGMAR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_FGOR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LO", bit: 0, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_BGMAR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_BGOR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LO", bit: 0, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_FGPFCCR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CM", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCM", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "START", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CS", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AM", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSS", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AI", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBS", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALPHA", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_FGCOLR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BLUE", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GREEN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RED", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_BGPFCCR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CM", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCM", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "START", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CS", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AM", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AI", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBS", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALPHA", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_BGCOLR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BLUE", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GREEN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RED", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_FGCMAR", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_BGCMAR", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_OPFCCR", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CM", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AI", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBS", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_OCOLR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BLUE", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GREEN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RED", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALPHA", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_OMAR", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_OOR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LO", bit: 0, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_NLR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NL", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 16, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_LWR", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LW", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMA2D_AMTCR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DT", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];