sdmmc-core 0.5.0

SD/MMC core data structures and algorithms
Documentation 
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use crate::lib_bitfield;

use super::{ExtCsd, ExtCsdIndex};

mod data;

pub use data::*;

lib_bitfield! {
    /// Represents the `WR_REL_SET` field of the [ExtCsd] register.
    WriteReliabilitySetting: u8,
    mask: 0x1f,
    default: 0x0,
    {
        /// Write data reliability for partition 4.
        wr_data_rel_4: WriteDataReliability, 4;
        /// Write data reliability for partition 3.
        wr_data_rel_3: WriteDataReliability, 3;
        /// Write data reliability for partition 2.
        wr_data_rel_2: WriteDataReliability, 2;
        /// Write data reliability for partition 1.
        wr_data_rel_1: WriteDataReliability, 1;
        /// Write data reliability for the user area.
        wr_data_rel_usr: WriteDataReliability, 0;
    }
}

impl WriteReliabilitySetting {
    /// Converts an inner representation into a [WriteReliabilitySetting].
    pub const fn from_inner(val: u8) -> Self {
        Self(val & Self::MASK)
    }
}

impl ExtCsd {
    /// Gets the `WR_REL_SET` field of the [ExtCsd] register.
    pub const fn wr_rel_set(&self) -> WriteReliabilitySetting {
        WriteReliabilitySetting::from_inner(self.0[ExtCsdIndex::WrRelSet.into_inner()])
    }

    /// Sets the `WR_REL_SET` field of the [ExtCsd] register.
    pub fn set_wr_rel_set(&mut self, val: WriteReliabilitySetting) {
        self.0[ExtCsdIndex::WrRelSet.into_inner()] = val.into_inner();
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_wr_rel_set() {
        let mut ext_csd = ExtCsd::new();

        assert_eq!(ext_csd.wr_rel_set(), WriteReliabilitySetting::new());

        (0..=u8::MAX)
            .map(WriteReliabilitySetting::from_inner)
            .for_each(|wr_rel_set| {
                ext_csd.set_wr_rel_set(wr_rel_set);
                assert_eq!(ext_csd.wr_rel_set(), wr_rel_set);
            });
    }
}