sdmmc-core 0.5.0

SD/MMC core data structures and algorithms
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

use crate::lib_bitfield;

use super::{ExtCsd, ExtCsdIndex};

lib_bitfield! {
    /// Represents the `CACHE_FLUSH_POLICY` field of the [ExtCsd] register.
    CacheFlushPolicy: u8,
    mask: 0x1,
    default: 0,
    {
        /// Indicates whether the FIFO policy is used for cache flushing.
        fifo: 0;
    }
}

impl ExtCsd {
    /// Gets the `CACHE_FLUSH_POLICY` field of the [ExtCsd] register.
    pub const fn cache_flush_policy(&self) -> CacheFlushPolicy {
        CacheFlushPolicy::from_inner(self.0[ExtCsdIndex::CacheFlushPolicy.into_inner()])
    }

    /// Sets the `CACHE_FLUSH_POLICY` field of the [ExtCsd] register.
    pub(crate) fn set_cache_flush_policy(&mut self, val: CacheFlushPolicy) {
        self.0[ExtCsdIndex::CacheFlushPolicy.into_inner()] = val.into_inner();
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_cache_flush_policy() {
        let mut ext_csd = ExtCsd::new();

        assert_eq!(ext_csd.cache_flush_policy(), CacheFlushPolicy::new());

        (0..=u8::MAX)
            .map(CacheFlushPolicy::from_inner)
            .for_each(|policy| {
                ext_csd.set_cache_flush_policy(policy);
                assert_eq!(ext_csd.cache_flush_policy(), policy);
            });
    }
}