sdmmc-core 0.5.0

SD/MMC core data structures and algorithms
Documentation 
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use crate::lib_bitfield;
use crate::result::Result;

use super::{ExtCsd, ExtCsdIndex};

mod drive_strength;
mod timing;

pub use drive_strength::*;
pub use timing::*;

lib_bitfield! {
    /// Represents the `HS_TIMING` field of the [ExtCsd].
    HsTiming: u8,
    mask: 0xff,
    default: 0,
    {
        /// Indicates the selected driver strength for the card.
        selected_driver_strength: SelectedDriverStrength, 7, 4;
        /// Indicates the selected timing interface for the card.
        timing_interface: TimingInterface, 3, 0;
    }
}

impl ExtCsd {
    /// Gets the `HS_TIMING` field of the [ExtCsd] register.
    pub const fn hs_timing(&self) -> Result<HsTiming> {
        HsTiming::try_from_inner(self.0[ExtCsdIndex::HsTiming.into_inner()])
    }

    /// Sets the `HS_TIMING` field of the [ExtCsd] register.
    pub fn set_hs_timing(&mut self, val: HsTiming) {
        self.0[ExtCsdIndex::HsTiming.into_inner()] = val.into_inner();
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_hs_timing() {
        let mut ext_csd = ExtCsd::new();

        assert_eq!(ext_csd.hs_timing(), Ok(HsTiming::new()));

        (0..=u8::MAX).for_each(|raw_hs| {
            // set a potentially invalid HsTiming
            ext_csd.set_hs_timing(HsTiming(raw_hs));

            match HsTiming::try_from_inner(raw_hs) {
                Ok(hs) => assert_eq!(ext_csd.hs_timing(), Ok(hs)),
                Err(err) => assert_eq!(ext_csd.hs_timing(), Err(err)),
            }
        });
    }
}