sdmmc-core 0.5.0

use crate::lib_bitfield;
use crate::result::Result;

use super::{ExtCsd, ExtCsdIndex};

mod en_rel_wr;
mod en_rpmb_rel_wr;
mod hs_ctrl_rel;

pub use en_rel_wr::*;
pub use en_rpmb_rel_wr::*;
pub use hs_ctrl_rel::*;

lib_bitfield! {
    /// Represents the `WR_REL_PARAM` field of the [ExtCsd] register.
    WriteReliabilityParameter: u8,
    mask: 0b10101,
    default: 0,
    {
        /// Indicates support for enhanced RPMB reliable write.
        en_rpmb_rel_wr: EnhancedRpmbReliableWrite, 4;
        /// Indicates support for enhanced reliable write.
        en_rel_wr: EnhancedReliableWrite, 2;
        /// Indicates support for host controlled data reliability.
        hs_ctrl_rel: HostControlledDataReliability, 0;
    }
}

impl WriteReliabilityParameter {
    /// Converts an inner representation into a [WriteReliabilityParameter].
    pub const fn from_inner(val: u8) -> Self {
        Self(val & Self::MASK)
    }
}

impl ExtCsd {
    /// Gets the `WR_REL_PARAM` field of the [ExtCsd] register.
    pub const fn wr_rel_param(&self) -> WriteReliabilityParameter {
        WriteReliabilityParameter::from_inner(self.0[ExtCsdIndex::WrRelParam.into_inner()])
    }

    /// Sets the `WR_REL_PARAM` field of the [ExtCsd] register.
    pub fn set_wr_rel_param(&mut self, val: WriteReliabilityParameter) {
        self.0[ExtCsdIndex::WrRelParam.into_inner()] = val.into_inner();
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_wr_rel_param() {
        let mut ext_csd = ExtCsd::new();

        assert_eq!(ext_csd.wr_rel_param(), WriteReliabilityParameter::new());

        (0..=u8::MAX)
            .map(WriteReliabilityParameter::from_inner)
            .for_each(|wr_rel_param| {
                ext_csd.set_wr_rel_param(wr_rel_param);
                assert_eq!(ext_csd.wr_rel_param(), wr_rel_param);
            });
    }
}