sdmmc-core 0.5.0

SD/MMC core data structures and algorithms
Documentation
//! Types to represent the `FLUSH_CACHE` field of the [ExtCsd] register.

use crate::lib_bitfield;
use crate::result::Result;

mod barrier;
mod flush;

pub use barrier::*;
pub use flush::*;

use super::{ExtCsd, ExtCsdIndex};

lib_bitfield! {
    /// Represents the `FLUSH_CACHE` field of the [ExtCsd] register.
    ///
    /// Controls timing when data will be flushed to nonvolatile storage.
    FlushCache: u8,
    mask: 0x3,
    default: 0,
    {
        /// Controls setting a memory barrier for cache flushing.
        barrier: Barrier, 1;
        /// Controls flushing data to nonvolatile memory.
        flush: Flush, 0;
    }
}

impl ExtCsd {
    /// Gets the `FLUSH_CACHE` field of the [ExtCsd] register.
    pub const fn flush_cache(&self) -> Result<FlushCache> {
        FlushCache::try_from_inner(self.0[ExtCsdIndex::FlushCache.into_inner()])
    }

    /// Sets the `FLUSH_CACHE` field of the [ExtCsd] register.
    pub fn set_flush_cache(&mut self, val: FlushCache) {
        self.0[ExtCsdIndex::FlushCache.into_inner()] = val.into_inner();
    }
}