sdmmc-core 0.5.0

SD/MMC core data structures and algorithms
Documentation 
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use crate::lib_bitfield;
use crate::result::Result;

use super::{ExtCsd, ExtCsdIndex, PowerClassCode};

lib_bitfield! {
    /// Represents the `POWER_CLASS` field of the [ExtCsd] register.
    PowerClass: u8,
    mask: 0xf,
    default: 0,
    {
        /// Indicates the power class code for the device.
        power_class_code: PowerClassCode, 3, 0;
    }
}

impl ExtCsd {
    /// Gets the `POWER_CLASS` field of the [ExtCsd] register.
    pub const fn power_class(&self) -> Result<PowerClass> {
        PowerClass::try_from_inner(self.0[ExtCsdIndex::PowerClass.into_inner()])
    }

    /// Sets the `POWER_CLASS` field of the [ExtCsd] register.
    pub fn set_power_class(&mut self, val: PowerClass) {
        self.0[ExtCsdIndex::PowerClass.into_inner()] = val.into_inner();
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_power_class() {
        let mut ext_csd = ExtCsd::new();

        assert_eq!(ext_csd.power_class(), Ok(PowerClass::new()));

        (0..=u8::MAX).for_each(|raw_power| {
            // set a potentially invalid PowerClass
            ext_csd.set_power_class(PowerClass(raw_power));

            match PowerClass::try_from_inner(raw_power) {
                Ok(power) => assert_eq!(ext_csd.power_class(), Ok(power)),
                Err(err) => assert_eq!(ext_csd.power_class(), Err(err)),
            }
        });
    }
}