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use crate::lib_bitfield;
use crate::result::Result;
use super::{ExtCsd, ExtCsdIndex};
lib_bitfield! {
/// Represents the `DRIVER_STRENGTH` field of the [ExtCsd] register.
DriverStrength: u8,
mask: 0x1f,
default: 0,
{
/// Indicates support for `Type 4` driver strength.
type4: 4;
/// Indicates support for `Type 3` driver strength.
type3: 3;
/// Indicates support for `Type 2` driver strength.
type2: 2;
/// Indicates support for `Type 1` driver strength.
type1: 1;
/// Indicates support for `Type 0` driver strength.
type0: 0;
}
}
impl ExtCsd {
/// Gets the `DRIVER_STRENGTH` field of the [ExtCsd] register.
pub const fn driver_strength(&self) -> DriverStrength {
DriverStrength::from_inner(self.0[ExtCsdIndex::DriverStrength.into_inner()])
}
/// Sets the `DRIVER_STRENGTH` field of the [ExtCsd] register.
pub(crate) fn set_driver_strength(&mut self, val: DriverStrength) {
self.0[ExtCsdIndex::DriverStrength.into_inner()] = val.into_inner();
}
}
#[cfg(test)]
mod tests {
use super::*;
#[test]
fn test_driver_strength() {
let mut ext_csd = ExtCsd::new();
assert_eq!(ext_csd.driver_strength(), DriverStrength::new());
(0..=u8::MAX)
.map(DriverStrength::from_inner)
.for_each(|driver| {
ext_csd.set_driver_strength(driver);
assert_eq!(ext_csd.driver_strength(), driver);
});
}
}