sdmmc-core 0.5.0

use crate::lib_bitfield;

use super::{ExtCsd, ExtCsdIndex};

lib_bitfield! {
    /// Represents the `SUPPORTED_MODES` field of the [ExtCsd] register.
    SupportedModes: u8,
    mask: 0x3,
    default: 0,
    {
        /// Indicates support for the `Vendor Specific Mode` (VSM).
        vsm: 1;
        /// Indicates support for the FFU operation mode.
        ffu: 0;
    }
}

impl ExtCsd {
    /// Gets the `SUPPORTED_MODES` field of the [ExtCsd] register.
    pub const fn supported_modes(&self) -> SupportedModes {
        SupportedModes::from_inner(self.0[ExtCsdIndex::SupportedModes.into_inner()])
    }

    /// Sets the `SUPPORTED_MODES` field of the [ExtCsd] register.
    pub(crate) fn set_supported_modes(&mut self, val: SupportedModes) {
        self.0[ExtCsdIndex::SupportedModes.into_inner()] = val.into_inner();
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_supported_modes() {
        let mut ext_csd = ExtCsd::new();

        assert_eq!(ext_csd.supported_modes(), SupportedModes::new());

        (0..u8::MAX)
            .map(SupportedModes::from_inner)
            .for_each(|feature| {
                ext_csd.set_supported_modes(feature);
                assert_eq!(ext_csd.supported_modes(), feature);
            });
    }
}