rk3399-pac 0.1.4

Peripheral Access Crate (PAC) for the RK3399 SoC from Rockchip
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

#[doc = "Register `DENALI_PHY_199` reader"]
pub type R = crate::R<DenaliPhy199Spec>;
#[doc = "Register `DENALI_PHY_199` writer"]
pub type W = crate::W<DenaliPhy199Spec>;
#[doc = "Field `PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1` reader - Falling edge read DQS slave delay setting for DQ2 for slice 1."]
pub type PhyRddqsDq2FallSlaveDelay1R = crate::FieldReader<u16>;
#[doc = "Field `PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1` writer - Falling edge read DQS slave delay setting for DQ2 for slice 1."]
pub type PhyRddqsDq2FallSlaveDelay1W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1` reader - Rising edge read DQS slave delay setting for DQ3 for slice 1."]
pub type PhyRddqsDq3RiseSlaveDelay1R = crate::FieldReader<u16>;
#[doc = "Field `PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1` writer - Rising edge read DQS slave delay setting for DQ3 for slice 1."]
pub type PhyRddqsDq3RiseSlaveDelay1W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
    #[doc = "Bits 0:9 - Falling edge read DQS slave delay setting for DQ2 for slice 1."]
    #[inline(always)]
    pub fn phy_rddqs_dq2_fall_slave_delay_1(&self) -> PhyRddqsDq2FallSlaveDelay1R {
        PhyRddqsDq2FallSlaveDelay1R::new((self.bits & 0x03ff) as u16)
    }
    #[doc = "Bits 16:25 - Rising edge read DQS slave delay setting for DQ3 for slice 1."]
    #[inline(always)]
    pub fn phy_rddqs_dq3_rise_slave_delay_1(&self) -> PhyRddqsDq3RiseSlaveDelay1R {
        PhyRddqsDq3RiseSlaveDelay1R::new(((self.bits >> 16) & 0x03ff) as u16)
    }
}
impl W {
    #[doc = "Bits 0:9 - Falling edge read DQS slave delay setting for DQ2 for slice 1."]
    #[inline(always)]
    #[must_use]
    pub fn phy_rddqs_dq2_fall_slave_delay_1(
        &mut self,
    ) -> PhyRddqsDq2FallSlaveDelay1W<DenaliPhy199Spec> {
        PhyRddqsDq2FallSlaveDelay1W::new(self, 0)
    }
    #[doc = "Bits 16:25 - Rising edge read DQS slave delay setting for DQ3 for slice 1."]
    #[inline(always)]
    #[must_use]
    pub fn phy_rddqs_dq3_rise_slave_delay_1(
        &mut self,
    ) -> PhyRddqsDq3RiseSlaveDelay1W<DenaliPhy199Spec> {
        PhyRddqsDq3RiseSlaveDelay1W::new(self, 16)
    }
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`denali_phy_199::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`denali_phy_199::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DenaliPhy199Spec;
impl crate::RegisterSpec for DenaliPhy199Spec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`denali_phy_199::R`](R) reader structure"]
impl crate::Readable for DenaliPhy199Spec {}
#[doc = "`write(|w| ..)` method takes [`denali_phy_199::W`](W) writer structure"]
impl crate::Writable for DenaliPhy199Spec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DENALI_PHY_199 to value 0"]
impl crate::Resettable for DenaliPhy199Spec {
    const RESET_VALUE: u32 = 0;
}