rk3399-pac 0.1.4

Peripheral Access Crate (PAC) for the RK3399 SoC from Rockchip
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55

#[doc = "Register `DENALI_CTL_60` reader"]
pub type R = crate::R<DenaliCtl60Spec>;
#[doc = "Register `DENALI_CTL_60` writer"]
pub type W = crate::W<DenaliCtl60Spec>;
#[doc = "Field `TXSNR_F0` reader - DRAM TXSNR value for frequency copy 0 in cycles."]
pub type TxsnrF0R = crate::FieldReader<u16>;
#[doc = "Field `TXSNR_F0` writer - DRAM TXSNR value for frequency copy 0 in cycles."]
pub type TxsnrF0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `TXSR_F1` reader - DRAM TXSR value for frequency copy 1 in cycles."]
pub type TxsrF1R = crate::FieldReader<u16>;
#[doc = "Field `TXSR_F1` writer - DRAM TXSR value for frequency copy 1 in cycles."]
pub type TxsrF1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
    #[doc = "Bits 0:15 - DRAM TXSNR value for frequency copy 0 in cycles."]
    #[inline(always)]
    pub fn txsnr_f0(&self) -> TxsnrF0R {
        TxsnrF0R::new((self.bits & 0xffff) as u16)
    }
    #[doc = "Bits 16:31 - DRAM TXSR value for frequency copy 1 in cycles."]
    #[inline(always)]
    pub fn txsr_f1(&self) -> TxsrF1R {
        TxsrF1R::new(((self.bits >> 16) & 0xffff) as u16)
    }
}
impl W {
    #[doc = "Bits 0:15 - DRAM TXSNR value for frequency copy 0 in cycles."]
    #[inline(always)]
    #[must_use]
    pub fn txsnr_f0(&mut self) -> TxsnrF0W<DenaliCtl60Spec> {
        TxsnrF0W::new(self, 0)
    }
    #[doc = "Bits 16:31 - DRAM TXSR value for frequency copy 1 in cycles."]
    #[inline(always)]
    #[must_use]
    pub fn txsr_f1(&mut self) -> TxsrF1W<DenaliCtl60Spec> {
        TxsrF1W::new(self, 16)
    }
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`denali_ctl_60::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`denali_ctl_60::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DenaliCtl60Spec;
impl crate::RegisterSpec for DenaliCtl60Spec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`denali_ctl_60::R`](R) reader structure"]
impl crate::Readable for DenaliCtl60Spec {}
#[doc = "`write(|w| ..)` method takes [`denali_ctl_60::W`](W) writer structure"]
impl crate::Writable for DenaliCtl60Spec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DENALI_CTL_60 to value 0"]
impl crate::Resettable for DenaliCtl60Spec {
    const RESET_VALUE: u32 = 0;
}