rk3399-pac 0.1.4

Peripheral Access Crate (PAC) for the RK3399 SoC from Rockchip
Documentation 
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#[doc = "Register `DDR_PI_REG_98` reader"]
pub type R = crate::R<DdrPiReg98Spec>;
#[doc = "Register `DDR_PI_REG_98` writer"]
pub type W = crate::W<DdrPiReg98Spec>;
#[doc = "Field `PI_TDFI_CALVL_RESP` reader - Defines the DFI tCALVL_RESP timing parameter (in DFI clocks), the\n\nmaximum cycles between a dfi_calvl_req assertion and a\n\ndfi_calvl_en assertion."]
pub type PiTdfiCalvlRespR = crate::FieldReader<u32>;
#[doc = "Field `PI_TDFI_CALVL_RESP` writer - Defines the DFI tCALVL_RESP timing parameter (in DFI clocks), the\n\nmaximum cycles between a dfi_calvl_req assertion and a\n\ndfi_calvl_en assertion."]
pub type PiTdfiCalvlRespW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
    #[doc = "Bits 0:31 - Defines the DFI tCALVL_RESP timing parameter (in DFI clocks), the\n\nmaximum cycles between a dfi_calvl_req assertion and a\n\ndfi_calvl_en assertion."]
    #[inline(always)]
    pub fn pi_tdfi_calvl_resp(&self) -> PiTdfiCalvlRespR {
        PiTdfiCalvlRespR::new(self.bits)
    }
}
impl W {
    #[doc = "Bits 0:31 - Defines the DFI tCALVL_RESP timing parameter (in DFI clocks), the\n\nmaximum cycles between a dfi_calvl_req assertion and a\n\ndfi_calvl_en assertion."]
    #[inline(always)]
    #[must_use]
    pub fn pi_tdfi_calvl_resp(&mut self) -> PiTdfiCalvlRespW<DdrPiReg98Spec> {
        PiTdfiCalvlRespW::new(self, 0)
    }
}
#[doc = "DDR PHY Independent Register 98\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ddr_pi_reg_98::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ddr_pi_reg_98::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DdrPiReg98Spec;
impl crate::RegisterSpec for DdrPiReg98Spec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`ddr_pi_reg_98::R`](R) reader structure"]
impl crate::Readable for DdrPiReg98Spec {}
#[doc = "`write(|w| ..)` method takes [`ddr_pi_reg_98::W`](W) writer structure"]
impl crate::Writable for DdrPiReg98Spec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DDR_PI_REG_98 to value 0"]
impl crate::Resettable for DdrPiReg98Spec {
    const RESET_VALUE: u32 = 0;
}