rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `TIM9` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR1` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr1 = 0,
    /// `CR2` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cr2 = 1,
    /// `SMCR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Smcr = 2,
    /// `DIER` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Dier = 3,
    /// `SR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Sr = 4,
    /// `EGR` at offset `0x14`, resets to `0x0000_0000`, write-only.
    Egr = 5,
    /// `CCMR1_Input` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Ccmr1Input = 6,
    /// `CCMR1_Output` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Ccmr1Output = 7,
    /// `CCER` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Ccer = 8,
    /// `CNT` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Cnt = 9,
    /// `PSC` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Psc = 10,
    /// `ARR` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Arr = 11,
    /// `CCR1` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Ccr1 = 12,
    /// `CCR2` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Ccr2 = 13,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 14] = [Self::Cr1, Self::Cr2, Self::Smcr, Self::Dier, Self::Sr, Self::Egr, Self::Ccmr1Input, Self::Ccmr1Output, Self::Ccer, Self::Cnt, Self::Psc, Self::Arr, Self::Ccr1, Self::Ccr2];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `CEN`, bit 0.
    pub const CEN: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `UDIS`, bit 1.
    pub const UDIS: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `URS`, bit 2.
    pub const URS: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `OPM`, bit 3.
    pub const OPM: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `ARPE`, bit 7.
    pub const ARPE: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `CKD`, bits 8..=9.
    pub const CKD: &FieldSpec = &super::REGISTERS[0].fields[5];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `MMS`, bits 4..=6.
    pub const MMS: &FieldSpec = &super::REGISTERS[1].fields[0];
}

/// The fields of `SMCR`.
pub mod smcr {
    use super::FieldSpec;
    /// `SMS`, bits 0..=2.
    pub const SMS: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `TS`, bits 4..=6.
    pub const TS: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `MSM`, bit 7.
    pub const MSM: &FieldSpec = &super::REGISTERS[2].fields[2];
}

/// The fields of `DIER`.
pub mod dier {
    use super::FieldSpec;
    /// `UIE`, bit 0.
    pub const UIE: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `CC1IE`, bit 1.
    pub const CC1IE: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `CC2IE`, bit 2.
    pub const CC2IE: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `TIE`, bit 6.
    pub const TIE: &FieldSpec = &super::REGISTERS[3].fields[3];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `UIF`, bit 0.
    pub const UIF: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `CC1IF`, bit 1.
    pub const CC1IF: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `CC2IF`, bit 2.
    pub const CC2IF: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `TIF`, bit 6.
    pub const TIF: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `CC1OF`, bit 9.
    pub const CC1OF: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `CC2OF`, bit 10.
    pub const CC2OF: &FieldSpec = &super::REGISTERS[4].fields[5];
}

/// The fields of `EGR`.
pub mod egr {
    use super::FieldSpec;
    /// `UG`, bit 0.
    pub const UG: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `CC1G`, bit 1.
    pub const CC1G: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `CC2G`, bit 2.
    pub const CC2G: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `TG`, bit 6.
    pub const TG: &FieldSpec = &super::REGISTERS[5].fields[3];
}

/// The fields of `CCMR1_Input`.
pub mod ccmr1_input {
    use super::FieldSpec;
    /// `CC1S`, bits 0..=1.
    pub const CC1S: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `ICPCS`, bits 2..=3.
    pub const ICPCS: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `IC1F`, bits 4..=6.
    pub const IC1F: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `CC2S`, bits 8..=9.
    pub const CC2S: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `IC2PCS`, bits 10..=11.
    pub const IC2PCS: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `IC2F`, bits 12..=14.
    pub const IC2F: &FieldSpec = &super::REGISTERS[6].fields[5];
}

/// The fields of `CCMR1_Output`.
pub mod ccmr1_output {
    use super::FieldSpec;
    /// `CC1S`, bits 0..=1.
    pub const CC1S: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `OC1FE`, bit 2.
    pub const OC1FE: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `OC1PE`, bit 3.
    pub const OC1PE: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `OC1M`, bits 4..=6.
    pub const OC1M: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `CC2S`, bits 8..=9.
    pub const CC2S: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `OC2FE`, bit 10.
    pub const OC2FE: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `OC2PE`, bit 11.
    pub const OC2PE: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `OC2M`, bits 12..=14.
    pub const OC2M: &FieldSpec = &super::REGISTERS[7].fields[7];
}

/// The fields of `CCER`.
pub mod ccer {
    use super::FieldSpec;
    /// `CC1E`, bit 0.
    pub const CC1E: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `CC1P`, bit 1.
    pub const CC1P: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `CC1NP`, bit 3.
    pub const CC1NP: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `CC2E`, bit 4.
    pub const CC2E: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `CC2P`, bit 5.
    pub const CC2P: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `CC2NP`, bit 7.
    pub const CC2NP: &FieldSpec = &super::REGISTERS[8].fields[5];
}

/// The fields of `CNT`.
pub mod cnt {
    use super::FieldSpec;
    /// `CNT`, bits 0..=15.
    pub const CNT: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `PSC`.
pub mod psc {
    use super::FieldSpec;
    /// `PSC`, bits 0..=15.
    pub const PSC: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `ARR`.
pub mod arr {
    use super::FieldSpec;
    /// `ARR`, bits 0..=15.
    pub const ARR: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `CCR1`.
pub mod ccr1 {
    use super::FieldSpec;
    /// `CCR1`, bits 0..=15.
    pub const CCR1: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `CCR2`.
pub mod ccr2 {
    use super::FieldSpec;
    /// `CCR2`, bits 0..=15.
    pub const CCR2: &FieldSpec = &super::REGISTERS[13].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 14] = [
    RegisterSpec { name: "CR1", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDIS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "URS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OPM", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARPE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKD", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MMS", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SMCR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SMS", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TS", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSM", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DIER", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1IE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2IE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UIF", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1IF", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2IF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIF", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1OF", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2OF", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EGR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UG", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1G", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2G", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TG", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCMR1_Input", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC1S", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ICPCS", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC1F", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2S", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC2PCS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC2F", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCMR1_Output", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC1S", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC1FE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC1PE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC1M", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2S", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC2FE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC2PE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC2M", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCER", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC1E", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1P", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1NP", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2E", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2P", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2NP", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CNT", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CNT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PSC", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PSC", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ARR", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ARR", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCR1", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCR1", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCR2", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCR2", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];