rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `DAC` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr = 0,
    /// `SWTRIGR` at offset `0x4`, resets to `0x0000_0000`, write-only.
    Swtrigr = 1,
    /// `DHR12R1` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Dhr12r1 = 2,
    /// `DHR12L1` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Dhr12l1 = 3,
    /// `DHR8R1` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Dhr8r1 = 4,
    /// `DHR12R2` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Dhr12r2 = 5,
    /// `DHR12L2` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Dhr12l2 = 6,
    /// `DHR8R2` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Dhr8r2 = 7,
    /// `DHR12RD` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Dhr12rd = 8,
    /// `DHR12LD` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Dhr12ld = 9,
    /// `DHR8RD` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Dhr8rd = 10,
    /// `DOR1` at offset `0x2C`, resets to `0x0000_0000`, read-only.
    Dor1 = 11,
    /// `DOR2` at offset `0x30`, resets to `0x0000_0000`, read-only.
    Dor2 = 12,
    /// `SR` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Sr = 13,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 14] = [Self::Cr, Self::Swtrigr, Self::Dhr12r1, Self::Dhr12l1, Self::Dhr8r1, Self::Dhr12r2, Self::Dhr12l2, Self::Dhr8r2, Self::Dhr12rd, Self::Dhr12ld, Self::Dhr8rd, Self::Dor1, Self::Dor2, Self::Sr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `EN1`, bit 0.
    pub const EN1: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `BOFF1`, bit 1.
    pub const BOFF1: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `TEN1`, bit 2.
    pub const TEN1: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `TSEL1`, bits 3..=5.
    pub const TSEL1: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `WAVE1`, bits 6..=7.
    pub const WAVE1: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `MAMP1`, bits 8..=11.
    pub const MAMP1: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `DMAEN1`, bit 12.
    pub const DMAEN1: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `DMAUDRIE1`, bit 13.
    pub const DMAUDRIE1: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `EN2`, bit 16.
    pub const EN2: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `BOFF2`, bit 17.
    pub const BOFF2: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `TEN2`, bit 18.
    pub const TEN2: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `TSEL2`, bits 19..=21.
    pub const TSEL2: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `WAVE2`, bits 22..=23.
    pub const WAVE2: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `MAMP2`, bits 24..=27.
    pub const MAMP2: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `DMAEN2`, bit 28.
    pub const DMAEN2: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `DMAUDRIE2`, bit 29.
    pub const DMAUDRIE2: &FieldSpec = &super::REGISTERS[0].fields[15];
}

/// The fields of `SWTRIGR`.
pub mod swtrigr {
    use super::FieldSpec;
    /// `SWTRIG1`, bit 0.
    pub const SWTRIG1: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `SWTRIG2`, bit 1.
    pub const SWTRIG2: &FieldSpec = &super::REGISTERS[1].fields[1];
}

/// The fields of `DHR12R1`.
pub mod dhr12r1 {
    use super::FieldSpec;
    /// `DACC1DHR`, bits 0..=11.
    pub const DACC1DHR: &FieldSpec = &super::REGISTERS[2].fields[0];
}

/// The fields of `DHR12L1`.
pub mod dhr12l1 {
    use super::FieldSpec;
    /// `DACC1DHR`, bits 4..=15.
    pub const DACC1DHR: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `DHR8R1`.
pub mod dhr8r1 {
    use super::FieldSpec;
    /// `DACC1DHR`, bits 0..=7.
    pub const DACC1DHR: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `DHR12R2`.
pub mod dhr12r2 {
    use super::FieldSpec;
    /// `DACC2DHR`, bits 0..=11.
    pub const DACC2DHR: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `DHR12L2`.
pub mod dhr12l2 {
    use super::FieldSpec;
    /// `DACC2DHR`, bits 4..=15.
    pub const DACC2DHR: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `DHR8R2`.
pub mod dhr8r2 {
    use super::FieldSpec;
    /// `DACC2DHR`, bits 0..=7.
    pub const DACC2DHR: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `DHR12RD`.
pub mod dhr12rd {
    use super::FieldSpec;
    /// `DACC1DHR`, bits 0..=11.
    pub const DACC1DHR: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `DACC2DHR`, bits 16..=27.
    pub const DACC2DHR: &FieldSpec = &super::REGISTERS[8].fields[1];
}

/// The fields of `DHR12LD`.
pub mod dhr12ld {
    use super::FieldSpec;
    /// `DACC1DHR`, bits 4..=15.
    pub const DACC1DHR: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `DACC2DHR`, bits 20..=31.
    pub const DACC2DHR: &FieldSpec = &super::REGISTERS[9].fields[1];
}

/// The fields of `DHR8RD`.
pub mod dhr8rd {
    use super::FieldSpec;
    /// `DACC1DHR`, bits 0..=7.
    pub const DACC1DHR: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `DACC2DHR`, bits 8..=15.
    pub const DACC2DHR: &FieldSpec = &super::REGISTERS[10].fields[1];
}

/// The fields of `DOR1`.
pub mod dor1 {
    use super::FieldSpec;
    /// `DACC1DOR`, bits 0..=11.
    pub const DACC1DOR: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `DOR2`.
pub mod dor2 {
    use super::FieldSpec;
    /// `DACC2DOR`, bits 0..=11.
    pub const DACC2DOR: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `DMAUDR1`, bit 13.
    pub const DMAUDR1: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `DMAUDR2`, bit 29.
    pub const DMAUDR2: &FieldSpec = &super::REGISTERS[13].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 14] = [
    RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOFF1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEN1", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSEL1", bit: 3, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAVE1", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MAMP1", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAEN1", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAUDRIE1", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EN2", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOFF2", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEN2", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSEL2", bit: 19, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAVE2", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MAMP2", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAEN2", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAUDRIE2", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SWTRIGR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SWTRIG1", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWTRIG2", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DHR12R1", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DACC1DHR", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DHR12L1", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DACC1DHR", bit: 4, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DHR8R1", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DACC1DHR", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DHR12R2", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DACC2DHR", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DHR12L2", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DACC2DHR", bit: 4, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DHR8R2", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DACC2DHR", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DHR12RD", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DACC1DHR", bit: 0, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DACC2DHR", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DHR12LD", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DACC1DHR", bit: 4, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DACC2DHR", bit: 20, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DHR8RD", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DACC1DHR", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DACC2DHR", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DOR1", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DACC1DOR", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DOR2", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DACC2DOR", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMAUDR1", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAUDR2", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];