// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `RTC` and the instances derived from it.
use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};
/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
/// `TR` at offset `0x0`, resets to `0x0000_0000`, read-write.
Tr = 0,
/// `DR` at offset `0x4`, resets to `0x0000_2101`, read-write.
Dr = 1,
/// `CR` at offset `0x8`, resets to `0x0000_0000`, read-write.
Cr = 2,
/// `ISR` at offset `0xC`, resets to `0x0000_0007`, read-write.
Isr = 3,
/// `PRER` at offset `0x10`, resets to `0x007F_00FF`, read-write.
Prer = 4,
/// `WUTR` at offset `0x14`, resets to `0x0000_FFFF`, read-write.
Wutr = 5,
/// `CALIBR` at offset `0x18`, resets to `0x0000_0000`, read-write.
Calibr = 6,
/// `ALRMAR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
Alrmar = 7,
/// `ALRMBR` at offset `0x20`, resets to `0x0000_0000`, read-write.
Alrmbr = 8,
/// `WPR` at offset `0x24`, resets to `0x0000_0000`, write-only.
Wpr = 9,
/// `SSR` at offset `0x28`, resets to `0x0000_0000`, read-only.
Ssr = 10,
/// `SHIFTR` at offset `0x2C`, resets to `0x0000_0000`, write-only.
Shiftr = 11,
/// `TSTR` at offset `0x30`, resets to `0x0000_0000`, read-only.
Tstr = 12,
/// `TSDR` at offset `0x34`, resets to `0x0000_0000`, read-only.
Tsdr = 13,
/// `TSSSR` at offset `0x38`, resets to `0x0000_0000`, read-only.
Tsssr = 14,
/// `CALR` at offset `0x3C`, resets to `0x0000_0000`, read-write.
Calr = 15,
/// `TAFCR` at offset `0x40`, resets to `0x0000_0000`, read-write.
Tafcr = 16,
/// `ALRMASSR` at offset `0x44`, resets to `0x0000_0000`, read-write.
Alrmassr = 17,
/// `ALRMBSSR` at offset `0x48`, resets to `0x0000_0000`, read-write.
Alrmbssr = 18,
/// `BKP0R` at offset `0x50`, resets to `0x0000_0000`, read-write.
Bkp0r = 19,
/// `BKP1R` at offset `0x54`, resets to `0x0000_0000`, read-write.
Bkp1r = 20,
/// `BKP2R` at offset `0x58`, resets to `0x0000_0000`, read-write.
Bkp2r = 21,
/// `BKP3R` at offset `0x5C`, resets to `0x0000_0000`, read-write.
Bkp3r = 22,
/// `BKP4R` at offset `0x60`, resets to `0x0000_0000`, read-write.
Bkp4r = 23,
/// `BKP5R` at offset `0x64`, resets to `0x0000_0000`, read-write.
Bkp5r = 24,
/// `BKP6R` at offset `0x68`, resets to `0x0000_0000`, read-write.
Bkp6r = 25,
/// `BKP7R` at offset `0x6C`, resets to `0x0000_0000`, read-write.
Bkp7r = 26,
/// `BKP8R` at offset `0x70`, resets to `0x0000_0000`, read-write.
Bkp8r = 27,
/// `BKP9R` at offset `0x74`, resets to `0x0000_0000`, read-write.
Bkp9r = 28,
/// `BKP10R` at offset `0x78`, resets to `0x0000_0000`, read-write.
Bkp10r = 29,
/// `BKP11R` at offset `0x7C`, resets to `0x0000_0000`, read-write.
Bkp11r = 30,
/// `BKP12R` at offset `0x80`, resets to `0x0000_0000`, read-write.
Bkp12r = 31,
/// `BKP13R` at offset `0x84`, resets to `0x0000_0000`, read-write.
Bkp13r = 32,
/// `BKP14R` at offset `0x88`, resets to `0x0000_0000`, read-write.
Bkp14r = 33,
/// `BKP15R` at offset `0x8C`, resets to `0x0000_0000`, read-write.
Bkp15r = 34,
/// `BKP16R` at offset `0x90`, resets to `0x0000_0000`, read-write.
Bkp16r = 35,
/// `BKP17R` at offset `0x94`, resets to `0x0000_0000`, read-write.
Bkp17r = 36,
/// `BKP18R` at offset `0x98`, resets to `0x0000_0000`, read-write.
Bkp18r = 37,
/// `BKP19R` at offset `0x9C`, resets to `0x0000_0000`, read-write.
Bkp19r = 38,
}
impl Register {
/// Every register, in table order.
pub const ALL: [Self; 39] = [Self::Tr, Self::Dr, Self::Cr, Self::Isr, Self::Prer, Self::Wutr, Self::Calibr, Self::Alrmar, Self::Alrmbr, Self::Wpr, Self::Ssr, Self::Shiftr, Self::Tstr, Self::Tsdr, Self::Tsssr, Self::Calr, Self::Tafcr, Self::Alrmassr, Self::Alrmbssr, Self::Bkp0r, Self::Bkp1r, Self::Bkp2r, Self::Bkp3r, Self::Bkp4r, Self::Bkp5r, Self::Bkp6r, Self::Bkp7r, Self::Bkp8r, Self::Bkp9r, Self::Bkp10r, Self::Bkp11r, Self::Bkp12r, Self::Bkp13r, Self::Bkp14r, Self::Bkp15r, Self::Bkp16r, Self::Bkp17r, Self::Bkp18r, Self::Bkp19r];
}
impl Layout for Register {
const REGISTERS: &'static [RegisterSpec] = ®ISTERS;
fn from_index(index: usize) -> Option<Self> {
Self::ALL.get(index).copied()
}
fn index(self) -> usize {
self as usize
}
}
/// The fields of `TR`.
pub mod tr {
use super::FieldSpec;
/// `SU`, bits 0..=3.
pub const SU: &FieldSpec = &super::REGISTERS[0].fields[0];
/// `ST`, bits 4..=6.
pub const ST: &FieldSpec = &super::REGISTERS[0].fields[1];
/// `MNU`, bits 8..=11.
pub const MNU: &FieldSpec = &super::REGISTERS[0].fields[2];
/// `MNT`, bits 12..=14.
pub const MNT: &FieldSpec = &super::REGISTERS[0].fields[3];
/// `HU`, bits 16..=19.
pub const HU: &FieldSpec = &super::REGISTERS[0].fields[4];
/// `HT`, bits 20..=21.
pub const HT: &FieldSpec = &super::REGISTERS[0].fields[5];
/// `PM`, bit 22.
pub const PM: &FieldSpec = &super::REGISTERS[0].fields[6];
}
/// The fields of `DR`.
pub mod dr {
use super::FieldSpec;
/// `DU`, bits 0..=3.
pub const DU: &FieldSpec = &super::REGISTERS[1].fields[0];
/// `DT`, bits 4..=5.
pub const DT: &FieldSpec = &super::REGISTERS[1].fields[1];
/// `MU`, bits 8..=11.
pub const MU: &FieldSpec = &super::REGISTERS[1].fields[2];
/// `MT`, bit 12.
pub const MT: &FieldSpec = &super::REGISTERS[1].fields[3];
/// `WDU`, bits 13..=15.
pub const WDU: &FieldSpec = &super::REGISTERS[1].fields[4];
/// `YU`, bits 16..=19.
pub const YU: &FieldSpec = &super::REGISTERS[1].fields[5];
/// `YT`, bits 20..=23.
pub const YT: &FieldSpec = &super::REGISTERS[1].fields[6];
}
/// The fields of `CR`.
pub mod cr {
use super::FieldSpec;
/// `WCKSEL`, bits 0..=2.
pub const WCKSEL: &FieldSpec = &super::REGISTERS[2].fields[0];
/// `TSEDGE`, bit 3.
pub const TSEDGE: &FieldSpec = &super::REGISTERS[2].fields[1];
/// `REFCKON`, bit 4.
pub const REFCKON: &FieldSpec = &super::REGISTERS[2].fields[2];
/// `FMT`, bit 6.
pub const FMT: &FieldSpec = &super::REGISTERS[2].fields[3];
/// `DCE`, bit 7.
pub const DCE: &FieldSpec = &super::REGISTERS[2].fields[4];
/// `ALRAE`, bit 8.
pub const ALRAE: &FieldSpec = &super::REGISTERS[2].fields[5];
/// `ALRBE`, bit 9.
pub const ALRBE: &FieldSpec = &super::REGISTERS[2].fields[6];
/// `WUTE`, bit 10.
pub const WUTE: &FieldSpec = &super::REGISTERS[2].fields[7];
/// `TSE`, bit 11.
pub const TSE: &FieldSpec = &super::REGISTERS[2].fields[8];
/// `ALRAIE`, bit 12.
pub const ALRAIE: &FieldSpec = &super::REGISTERS[2].fields[9];
/// `ALRBIE`, bit 13.
pub const ALRBIE: &FieldSpec = &super::REGISTERS[2].fields[10];
/// `WUTIE`, bit 14.
pub const WUTIE: &FieldSpec = &super::REGISTERS[2].fields[11];
/// `TSIE`, bit 15.
pub const TSIE: &FieldSpec = &super::REGISTERS[2].fields[12];
/// `ADD1H`, bit 16.
pub const ADD1H: &FieldSpec = &super::REGISTERS[2].fields[13];
/// `SUB1H`, bit 17.
pub const SUB1H: &FieldSpec = &super::REGISTERS[2].fields[14];
/// `BKP`, bit 18.
pub const BKP: &FieldSpec = &super::REGISTERS[2].fields[15];
/// `POL`, bit 20.
pub const POL: &FieldSpec = &super::REGISTERS[2].fields[16];
/// `OSEL`, bits 21..=22.
pub const OSEL: &FieldSpec = &super::REGISTERS[2].fields[17];
/// `COE`, bit 23.
pub const COE: &FieldSpec = &super::REGISTERS[2].fields[18];
}
/// The fields of `ISR`.
pub mod isr {
use super::FieldSpec;
/// `ALRAWF`, bit 0, read-only.
pub const ALRAWF: &FieldSpec = &super::REGISTERS[3].fields[0];
/// `ALRBWF`, bit 1, read-only.
pub const ALRBWF: &FieldSpec = &super::REGISTERS[3].fields[1];
/// `WUTWF`, bit 2, read-only.
pub const WUTWF: &FieldSpec = &super::REGISTERS[3].fields[2];
/// `SHPF`, bit 3.
pub const SHPF: &FieldSpec = &super::REGISTERS[3].fields[3];
/// `INITS`, bit 4, read-only.
pub const INITS: &FieldSpec = &super::REGISTERS[3].fields[4];
/// `RSF`, bit 5.
pub const RSF: &FieldSpec = &super::REGISTERS[3].fields[5];
/// `INITF`, bit 6, read-only.
pub const INITF: &FieldSpec = &super::REGISTERS[3].fields[6];
/// `INIT`, bit 7.
pub const INIT: &FieldSpec = &super::REGISTERS[3].fields[7];
/// `ALRAF`, bit 8.
pub const ALRAF: &FieldSpec = &super::REGISTERS[3].fields[8];
/// `ALRBF`, bit 9.
pub const ALRBF: &FieldSpec = &super::REGISTERS[3].fields[9];
/// `WUTF`, bit 10.
pub const WUTF: &FieldSpec = &super::REGISTERS[3].fields[10];
/// `TSF`, bit 11.
pub const TSF: &FieldSpec = &super::REGISTERS[3].fields[11];
/// `TSOVF`, bit 12.
pub const TSOVF: &FieldSpec = &super::REGISTERS[3].fields[12];
/// `TAMP1F`, bit 13.
pub const TAMP1F: &FieldSpec = &super::REGISTERS[3].fields[13];
/// `TAMP2F`, bit 14.
pub const TAMP2F: &FieldSpec = &super::REGISTERS[3].fields[14];
/// `RECALPF`, bit 16, read-only.
pub const RECALPF: &FieldSpec = &super::REGISTERS[3].fields[15];
}
/// The fields of `PRER`.
pub mod prer {
use super::FieldSpec;
/// `PREDIV_S`, bits 0..=14.
pub const PREDIV_S: &FieldSpec = &super::REGISTERS[4].fields[0];
/// `PREDIV_A`, bits 16..=22.
pub const PREDIV_A: &FieldSpec = &super::REGISTERS[4].fields[1];
}
/// The fields of `WUTR`.
pub mod wutr {
use super::FieldSpec;
/// `WUT`, bits 0..=15.
pub const WUT: &FieldSpec = &super::REGISTERS[5].fields[0];
}
/// The fields of `CALIBR`.
pub mod calibr {
use super::FieldSpec;
/// `DC`, bits 0..=4.
pub const DC: &FieldSpec = &super::REGISTERS[6].fields[0];
/// `DCS`, bit 7.
pub const DCS: &FieldSpec = &super::REGISTERS[6].fields[1];
}
/// The fields of `ALRMAR`.
pub mod alrmar {
use super::FieldSpec;
/// `SU`, bits 0..=3.
pub const SU: &FieldSpec = &super::REGISTERS[7].fields[0];
/// `ST`, bits 4..=6.
pub const ST: &FieldSpec = &super::REGISTERS[7].fields[1];
/// `MSK1`, bit 7.
pub const MSK1: &FieldSpec = &super::REGISTERS[7].fields[2];
/// `MNU`, bits 8..=11.
pub const MNU: &FieldSpec = &super::REGISTERS[7].fields[3];
/// `MNT`, bits 12..=14.
pub const MNT: &FieldSpec = &super::REGISTERS[7].fields[4];
/// `MSK2`, bit 15.
pub const MSK2: &FieldSpec = &super::REGISTERS[7].fields[5];
/// `HU`, bits 16..=19.
pub const HU: &FieldSpec = &super::REGISTERS[7].fields[6];
/// `HT`, bits 20..=21.
pub const HT: &FieldSpec = &super::REGISTERS[7].fields[7];
/// `PM`, bit 22.
pub const PM: &FieldSpec = &super::REGISTERS[7].fields[8];
/// `MSK3`, bit 23.
pub const MSK3: &FieldSpec = &super::REGISTERS[7].fields[9];
/// `DU`, bits 24..=27.
pub const DU: &FieldSpec = &super::REGISTERS[7].fields[10];
/// `DT`, bits 28..=29.
pub const DT: &FieldSpec = &super::REGISTERS[7].fields[11];
/// `WDSEL`, bit 30.
pub const WDSEL: &FieldSpec = &super::REGISTERS[7].fields[12];
/// `MSK4`, bit 31.
pub const MSK4: &FieldSpec = &super::REGISTERS[7].fields[13];
}
/// The fields of `ALRMBR`.
pub mod alrmbr {
use super::FieldSpec;
/// `SU`, bits 0..=3.
pub const SU: &FieldSpec = &super::REGISTERS[8].fields[0];
/// `ST`, bits 4..=6.
pub const ST: &FieldSpec = &super::REGISTERS[8].fields[1];
/// `MSK1`, bit 7.
pub const MSK1: &FieldSpec = &super::REGISTERS[8].fields[2];
/// `MNU`, bits 8..=11.
pub const MNU: &FieldSpec = &super::REGISTERS[8].fields[3];
/// `MNT`, bits 12..=14.
pub const MNT: &FieldSpec = &super::REGISTERS[8].fields[4];
/// `MSK2`, bit 15.
pub const MSK2: &FieldSpec = &super::REGISTERS[8].fields[5];
/// `HU`, bits 16..=19.
pub const HU: &FieldSpec = &super::REGISTERS[8].fields[6];
/// `HT`, bits 20..=21.
pub const HT: &FieldSpec = &super::REGISTERS[8].fields[7];
/// `PM`, bit 22.
pub const PM: &FieldSpec = &super::REGISTERS[8].fields[8];
/// `MSK3`, bit 23.
pub const MSK3: &FieldSpec = &super::REGISTERS[8].fields[9];
/// `DU`, bits 24..=27.
pub const DU: &FieldSpec = &super::REGISTERS[8].fields[10];
/// `DT`, bits 28..=29.
pub const DT: &FieldSpec = &super::REGISTERS[8].fields[11];
/// `WDSEL`, bit 30.
pub const WDSEL: &FieldSpec = &super::REGISTERS[8].fields[12];
/// `MSK4`, bit 31.
pub const MSK4: &FieldSpec = &super::REGISTERS[8].fields[13];
}
/// The fields of `WPR`.
pub mod wpr {
use super::FieldSpec;
/// `KEY`, bits 0..=7.
pub const KEY: &FieldSpec = &super::REGISTERS[9].fields[0];
}
/// The fields of `SSR`.
pub mod ssr {
use super::FieldSpec;
/// `SS`, bits 0..=15.
pub const SS: &FieldSpec = &super::REGISTERS[10].fields[0];
}
/// The fields of `SHIFTR`.
pub mod shiftr {
use super::FieldSpec;
/// `SUBFS`, bits 0..=14.
pub const SUBFS: &FieldSpec = &super::REGISTERS[11].fields[0];
/// `ADD1S`, bit 31.
pub const ADD1S: &FieldSpec = &super::REGISTERS[11].fields[1];
}
/// The fields of `TSTR`.
pub mod tstr {
use super::FieldSpec;
/// `TAMP1E`, bit 0.
pub const TAMP1E: &FieldSpec = &super::REGISTERS[12].fields[0];
/// `TAMP1TRG`, bit 1.
pub const TAMP1TRG: &FieldSpec = &super::REGISTERS[12].fields[1];
/// `TAMPIE`, bit 2.
pub const TAMPIE: &FieldSpec = &super::REGISTERS[12].fields[2];
/// `TAMP1INSEL`, bit 16.
pub const TAMP1INSEL: &FieldSpec = &super::REGISTERS[12].fields[3];
/// `TSINSEL`, bit 17.
pub const TSINSEL: &FieldSpec = &super::REGISTERS[12].fields[4];
/// `ALARMOUTTYPE`, bit 18.
pub const ALARMOUTTYPE: &FieldSpec = &super::REGISTERS[12].fields[5];
}
/// The fields of `TSDR`.
pub mod tsdr {
use super::FieldSpec;
/// `DU`, bits 0..=3.
pub const DU: &FieldSpec = &super::REGISTERS[13].fields[0];
/// `DT`, bits 4..=5.
pub const DT: &FieldSpec = &super::REGISTERS[13].fields[1];
/// `MU`, bits 8..=11.
pub const MU: &FieldSpec = &super::REGISTERS[13].fields[2];
/// `MT`, bit 12.
pub const MT: &FieldSpec = &super::REGISTERS[13].fields[3];
/// `WDU`, bits 13..=15.
pub const WDU: &FieldSpec = &super::REGISTERS[13].fields[4];
}
/// The fields of `TSSSR`.
pub mod tsssr {
use super::FieldSpec;
/// `SS`, bits 0..=15.
pub const SS: &FieldSpec = &super::REGISTERS[14].fields[0];
}
/// The fields of `CALR`.
pub mod calr {
use super::FieldSpec;
/// `CALM`, bits 0..=8.
pub const CALM: &FieldSpec = &super::REGISTERS[15].fields[0];
/// `CALW16`, bit 13.
pub const CALW16: &FieldSpec = &super::REGISTERS[15].fields[1];
/// `CALW8`, bit 14.
pub const CALW8: &FieldSpec = &super::REGISTERS[15].fields[2];
/// `CALP`, bit 15.
pub const CALP: &FieldSpec = &super::REGISTERS[15].fields[3];
}
/// The fields of `TAFCR`.
pub mod tafcr {
use super::FieldSpec;
/// `TAMP1E`, bit 0.
pub const TAMP1E: &FieldSpec = &super::REGISTERS[16].fields[0];
/// `TAMP1TRG`, bit 1.
pub const TAMP1TRG: &FieldSpec = &super::REGISTERS[16].fields[1];
/// `TAMPIE`, bit 2.
pub const TAMPIE: &FieldSpec = &super::REGISTERS[16].fields[2];
/// `TAMP2E`, bit 3.
pub const TAMP2E: &FieldSpec = &super::REGISTERS[16].fields[3];
/// `TAMP2TRG`, bit 4.
pub const TAMP2TRG: &FieldSpec = &super::REGISTERS[16].fields[4];
/// `TAMPTS`, bit 7.
pub const TAMPTS: &FieldSpec = &super::REGISTERS[16].fields[5];
/// `TAMPFREQ`, bits 8..=10.
pub const TAMPFREQ: &FieldSpec = &super::REGISTERS[16].fields[6];
/// `TAMPFLT`, bits 11..=12.
pub const TAMPFLT: &FieldSpec = &super::REGISTERS[16].fields[7];
/// `TAMPPRCH`, bits 13..=14.
pub const TAMPPRCH: &FieldSpec = &super::REGISTERS[16].fields[8];
/// `TAMPPUDIS`, bit 15.
pub const TAMPPUDIS: &FieldSpec = &super::REGISTERS[16].fields[9];
/// `TAMP1INSEL`, bit 16.
pub const TAMP1INSEL: &FieldSpec = &super::REGISTERS[16].fields[10];
/// `TSINSEL`, bit 17.
pub const TSINSEL: &FieldSpec = &super::REGISTERS[16].fields[11];
/// `ALARMOUTTYPE`, bit 18.
pub const ALARMOUTTYPE: &FieldSpec = &super::REGISTERS[16].fields[12];
}
/// The fields of `ALRMASSR`.
pub mod alrmassr {
use super::FieldSpec;
/// `SS`, bits 0..=14.
pub const SS: &FieldSpec = &super::REGISTERS[17].fields[0];
/// `MASKSS`, bits 24..=27.
pub const MASKSS: &FieldSpec = &super::REGISTERS[17].fields[1];
}
/// The fields of `ALRMBSSR`.
pub mod alrmbssr {
use super::FieldSpec;
/// `SS`, bits 0..=14.
pub const SS: &FieldSpec = &super::REGISTERS[18].fields[0];
/// `MASKSS`, bits 24..=27.
pub const MASKSS: &FieldSpec = &super::REGISTERS[18].fields[1];
}
/// The fields of `BKP0R`.
pub mod bkp0r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[19].fields[0];
}
/// The fields of `BKP1R`.
pub mod bkp1r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[20].fields[0];
}
/// The fields of `BKP2R`.
pub mod bkp2r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[21].fields[0];
}
/// The fields of `BKP3R`.
pub mod bkp3r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[22].fields[0];
}
/// The fields of `BKP4R`.
pub mod bkp4r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[23].fields[0];
}
/// The fields of `BKP5R`.
pub mod bkp5r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[24].fields[0];
}
/// The fields of `BKP6R`.
pub mod bkp6r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[25].fields[0];
}
/// The fields of `BKP7R`.
pub mod bkp7r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[26].fields[0];
}
/// The fields of `BKP8R`.
pub mod bkp8r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[27].fields[0];
}
/// The fields of `BKP9R`.
pub mod bkp9r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[28].fields[0];
}
/// The fields of `BKP10R`.
pub mod bkp10r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[29].fields[0];
}
/// The fields of `BKP11R`.
pub mod bkp11r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[30].fields[0];
}
/// The fields of `BKP12R`.
pub mod bkp12r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[31].fields[0];
}
/// The fields of `BKP13R`.
pub mod bkp13r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[32].fields[0];
}
/// The fields of `BKP14R`.
pub mod bkp14r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[33].fields[0];
}
/// The fields of `BKP15R`.
pub mod bkp15r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[34].fields[0];
}
/// The fields of `BKP16R`.
pub mod bkp16r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[35].fields[0];
}
/// The fields of `BKP17R`.
pub mod bkp17r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[36].fields[0];
}
/// The fields of `BKP18R`.
pub mod bkp18r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[37].fields[0];
}
/// The fields of `BKP19R`.
pub mod bkp19r {
use super::FieldSpec;
/// `BKP`, bits 0..=31.
pub const BKP: &FieldSpec = &super::REGISTERS[38].fields[0];
}
/// The register table.
pub static REGISTERS: [RegisterSpec; 39] = [
RegisterSpec { name: "TR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SU", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ST", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MNU", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MNT", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HU", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HT", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PM", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DR", offset: 0x4, width: Width::W32, reset: 0x0000_2101, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DU", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DT", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MU", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MT", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WDU", bit: 13, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "YU", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "YT", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WCKSEL", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TSEDGE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "REFCKON", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FMT", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DCE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALRAE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALRBE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WUTE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TSE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALRAIE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALRBIE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WUTIE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TSIE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADD1H", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SUB1H", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BKP", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "POL", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OSEL", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "COE", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "ISR", offset: 0xC, width: Width::W32, reset: 0x0000_0007, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "ALRAWF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALRBWF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WUTWF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SHPF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "INITS", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RSF", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "INITF", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "INIT", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALRAF", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALRBF", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WUTF", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TSF", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TSOVF", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMP1F", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMP2F", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RECALPF", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PRER", offset: 0x10, width: Width::W32, reset: 0x007F_00FF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PREDIV_S", bit: 0, width: 15, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PREDIV_A", bit: 16, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "WUTR", offset: 0x14, width: Width::W32, reset: 0x0000_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WUT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CALIBR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DC", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DCS", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "ALRMAR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SU", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ST", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MSK1", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MNU", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MNT", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MSK2", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HU", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HT", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PM", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MSK3", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DU", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DT", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WDSEL", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MSK4", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "ALRMBR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SU", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ST", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MSK1", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MNU", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MNT", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MSK2", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HU", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HT", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PM", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MSK3", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DU", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DT", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WDSEL", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MSK4", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "WPR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "KEY", bit: 0, width: 8, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "SSR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SS", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "SHIFTR", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SUBFS", bit: 0, width: 15, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADD1S", bit: 31, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "TSTR", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TAMP1E", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMP1TRG", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMPIE", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMP1INSEL", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TSINSEL", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALARMOUTTYPE", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "TSDR", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DU", bit: 0, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DT", bit: 4, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MU", bit: 8, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MT", bit: 12, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WDU", bit: 13, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "TSSSR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SS", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CALR", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CALM", bit: 0, width: 9, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CALW16", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CALW8", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CALP", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "TAFCR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TAMP1E", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMP1TRG", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMPIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMP2E", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMP2TRG", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMPTS", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMPFREQ", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMPFLT", bit: 11, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMPPRCH", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMPPUDIS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TAMP1INSEL", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TSINSEL", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ALARMOUTTYPE", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "ALRMASSR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SS", bit: 0, width: 15, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MASKSS", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "ALRMBSSR", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SS", bit: 0, width: 15, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MASKSS", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP0R", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP1R", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP2R", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP3R", offset: 0x5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP4R", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP5R", offset: 0x64, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP6R", offset: 0x68, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP7R", offset: 0x6C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP8R", offset: 0x70, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP9R", offset: 0x74, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP10R", offset: 0x78, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP11R", offset: 0x7C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP12R", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP13R", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP14R", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP15R", offset: 0x8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP16R", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP17R", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP18R", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BKP19R", offset: 0x9C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BKP", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
];