rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `FLASH` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `ACR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Acr = 0,
    /// `KEYR` at offset `0x4`, resets to `0x0000_0000`, write-only.
    Keyr = 1,
    /// `OPTKEYR` at offset `0x8`, resets to `0x0000_0000`, write-only.
    Optkeyr = 2,
    /// `SR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Sr = 3,
    /// `CR` at offset `0x10`, resets to `0x8000_0000`, read-write.
    Cr = 4,
    /// `OPTCR` at offset `0x14`, resets to `0x0FFF_AAED`, read-write.
    Optcr = 5,
    /// `OPTCR1` at offset `0x18`, resets to `0x0FFF_0000`, read-write.
    Optcr1 = 6,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 7] = [Self::Acr, Self::Keyr, Self::Optkeyr, Self::Sr, Self::Cr, Self::Optcr, Self::Optcr1];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `ACR`.
pub mod acr {
    use super::FieldSpec;
    /// `LATENCY`, bits 0..=2.
    pub const LATENCY: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `PRFTEN`, bit 8.
    pub const PRFTEN: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `ICEN`, bit 9.
    pub const ICEN: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `DCEN`, bit 10.
    pub const DCEN: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `ICRST`, bit 11, write-only.
    pub const ICRST: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `DCRST`, bit 12.
    pub const DCRST: &FieldSpec = &super::REGISTERS[0].fields[5];
}

/// The fields of `KEYR`.
pub mod keyr {
    use super::FieldSpec;
    /// `KEY`, bits 0..=31.
    pub const KEY: &FieldSpec = &super::REGISTERS[1].fields[0];
}

/// The fields of `OPTKEYR`.
pub mod optkeyr {
    use super::FieldSpec;
    /// `OPTKEY`, bits 0..=31.
    pub const OPTKEY: &FieldSpec = &super::REGISTERS[2].fields[0];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `EOP`, bit 0.
    pub const EOP: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `OPERR`, bit 1.
    pub const OPERR: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `WRPERR`, bit 4.
    pub const WRPERR: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `PGAERR`, bit 5.
    pub const PGAERR: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `PGPERR`, bit 6.
    pub const PGPERR: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `PGSERR`, bit 7.
    pub const PGSERR: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `BSY`, bit 16, read-only.
    pub const BSY: &FieldSpec = &super::REGISTERS[3].fields[6];
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `PG`, bit 0.
    pub const PG: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `SER`, bit 1.
    pub const SER: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `MER`, bit 2.
    pub const MER: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `SNB`, bits 3..=7.
    pub const SNB: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `PSIZE`, bits 8..=9.
    pub const PSIZE: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `MER1`, bit 15.
    pub const MER1: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `STRT`, bit 16.
    pub const STRT: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `EOPIE`, bit 24.
    pub const EOPIE: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `ERRIE`, bit 25.
    pub const ERRIE: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `LOCK`, bit 31.
    pub const LOCK: &FieldSpec = &super::REGISTERS[4].fields[9];
}

/// The fields of `OPTCR`.
pub mod optcr {
    use super::FieldSpec;
    /// `OPTLOCK`, bit 0.
    pub const OPTLOCK: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `OPTSTRT`, bit 1.
    pub const OPTSTRT: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `BOR_LEV`, bits 2..=3.
    pub const BOR_LEV: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `BFB2`, bit 4.
    pub const BFB2: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `WDG_SW`, bit 5.
    pub const WDG_SW: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `nRST_STOP`, bit 6.
    pub const NRST_STOP: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `nRST_STDBY`, bit 7.
    pub const NRST_STDBY: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `RDP`, bits 8..=15.
    pub const RDP: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `nWRP`, bits 16..=27.
    pub const NWRP: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `DB1M`, bit 30.
    pub const DB1M: &FieldSpec = &super::REGISTERS[5].fields[9];
    /// `SPRMOD`, bit 31.
    pub const SPRMOD: &FieldSpec = &super::REGISTERS[5].fields[10];
}

/// The fields of `OPTCR1`.
pub mod optcr1 {
    use super::FieldSpec;
    /// `nWRP`, bits 16..=27.
    pub const NWRP: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 7] = [
    RegisterSpec { name: "ACR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LATENCY", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRFTEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ICEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ICRST", bit: 11, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCRST", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "KEYR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "KEY", bit: 0, width: 32, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OPTKEYR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OPTKEY", bit: 0, width: 32, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EOP", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OPERR", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WRPERR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PGAERR", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PGPERR", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PGSERR", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BSY", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR", offset: 0x10, width: Width::W32, reset: 0x8000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PG", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SER", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MER", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SNB", bit: 3, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PSIZE", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MER1", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STRT", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOPIE", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERRIE", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OPTCR", offset: 0x14, width: Width::W32, reset: 0x0FFF_AAED, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OPTLOCK", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OPTSTRT", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOR_LEV", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BFB2", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WDG_SW", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "nRST_STOP", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "nRST_STDBY", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDP", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "nWRP", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DB1M", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPRMOD", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OPTCR1", offset: 0x18, width: Width::W32, reset: 0x0FFF_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "nWRP", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];