rigless 0.3.0

// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `TIM5` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR1` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr1 = 0,
    /// `CR2` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cr2 = 1,
    /// `SMCR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Smcr = 2,
    /// `DIER` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Dier = 3,
    /// `SR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Sr = 4,
    /// `EGR` at offset `0x14`, resets to `0x0000_0000`, write-only.
    Egr = 5,
    /// `CCMR1_Input` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Ccmr1Input = 6,
    /// `CCMR1_Output` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Ccmr1Output = 7,
    /// `CCMR2_Input` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Ccmr2Input = 8,
    /// `CCMR2_Output` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Ccmr2Output = 9,
    /// `CCER` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Ccer = 10,
    /// `CNT` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Cnt = 11,
    /// `PSC` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Psc = 12,
    /// `ARR` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Arr = 13,
    /// `CCR1` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Ccr1 = 14,
    /// `CCR2` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Ccr2 = 15,
    /// `CCR3` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    Ccr3 = 16,
    /// `CCR4` at offset `0x40`, resets to `0x0000_0000`, read-write.
    Ccr4 = 17,
    /// `DCR` at offset `0x48`, resets to `0x0000_0000`, read-write.
    Dcr = 18,
    /// `DMAR` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    Dmar = 19,
    /// `OR` at offset `0x50`, resets to `0x0000_0000`, read-write.
    Or = 20,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 21] = [Self::Cr1, Self::Cr2, Self::Smcr, Self::Dier, Self::Sr, Self::Egr, Self::Ccmr1Input, Self::Ccmr1Output, Self::Ccmr2Input, Self::Ccmr2Output, Self::Ccer, Self::Cnt, Self::Psc, Self::Arr, Self::Ccr1, Self::Ccr2, Self::Ccr3, Self::Ccr4, Self::Dcr, Self::Dmar, Self::Or];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `CEN`, bit 0.
    pub const CEN: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `UDIS`, bit 1.
    pub const UDIS: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `URS`, bit 2.
    pub const URS: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `OPM`, bit 3.
    pub const OPM: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `DIR`, bit 4.
    pub const DIR: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `CMS`, bits 5..=6.
    pub const CMS: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `ARPE`, bit 7.
    pub const ARPE: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `CKD`, bits 8..=9.
    pub const CKD: &FieldSpec = &super::REGISTERS[0].fields[7];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `CCDS`, bit 3.
    pub const CCDS: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `MMS`, bits 4..=6.
    pub const MMS: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `TI1S`, bit 7.
    pub const TI1S: &FieldSpec = &super::REGISTERS[1].fields[2];
}

/// The fields of `SMCR`.
pub mod smcr {
    use super::FieldSpec;
    /// `SMS`, bits 0..=2.
    pub const SMS: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `TS`, bits 4..=6.
    pub const TS: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `MSM`, bit 7.
    pub const MSM: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `ETF`, bits 8..=11.
    pub const ETF: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `ETPS`, bits 12..=13.
    pub const ETPS: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `ECE`, bit 14.
    pub const ECE: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `ETP`, bit 15.
    pub const ETP: &FieldSpec = &super::REGISTERS[2].fields[6];
}

/// The fields of `DIER`.
pub mod dier {
    use super::FieldSpec;
    /// `UIE`, bit 0.
    pub const UIE: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `CC1IE`, bit 1.
    pub const CC1IE: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `CC2IE`, bit 2.
    pub const CC2IE: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `CC3IE`, bit 3.
    pub const CC3IE: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `CC4IE`, bit 4.
    pub const CC4IE: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `TIE`, bit 6.
    pub const TIE: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `UDE`, bit 8.
    pub const UDE: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `CC1DE`, bit 9.
    pub const CC1DE: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `CC2DE`, bit 10.
    pub const CC2DE: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `CC3DE`, bit 11.
    pub const CC3DE: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `CC4DE`, bit 12.
    pub const CC4DE: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `TDE`, bit 14.
    pub const TDE: &FieldSpec = &super::REGISTERS[3].fields[11];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `UIF`, bit 0.
    pub const UIF: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `CC1IF`, bit 1.
    pub const CC1IF: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `CC2IF`, bit 2.
    pub const CC2IF: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `CC3IF`, bit 3.
    pub const CC3IF: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `CC4IF`, bit 4.
    pub const CC4IF: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `TIF`, bit 6.
    pub const TIF: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `CC1OF`, bit 9.
    pub const CC1OF: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `CC2OF`, bit 10.
    pub const CC2OF: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `CC3OF`, bit 11.
    pub const CC3OF: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `CC4OF`, bit 12.
    pub const CC4OF: &FieldSpec = &super::REGISTERS[4].fields[9];
}

/// The fields of `EGR`.
pub mod egr {
    use super::FieldSpec;
    /// `UG`, bit 0.
    pub const UG: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `CC1G`, bit 1.
    pub const CC1G: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `CC2G`, bit 2.
    pub const CC2G: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `CC3G`, bit 3.
    pub const CC3G: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `CC4G`, bit 4.
    pub const CC4G: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `TG`, bit 6.
    pub const TG: &FieldSpec = &super::REGISTERS[5].fields[5];
}

/// The fields of `CCMR1_Input`.
pub mod ccmr1_input {
    use super::FieldSpec;
    /// `CC1S`, bits 0..=1.
    pub const CC1S: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `ICPCS`, bits 2..=3.
    pub const ICPCS: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `IC1F`, bits 4..=7.
    pub const IC1F: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `CC2S`, bits 8..=9.
    pub const CC2S: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `IC2PCS`, bits 10..=11.
    pub const IC2PCS: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `IC2F`, bits 12..=15.
    pub const IC2F: &FieldSpec = &super::REGISTERS[6].fields[5];
}

/// The fields of `CCMR1_Output`.
pub mod ccmr1_output {
    use super::FieldSpec;
    /// `CC1S`, bits 0..=1.
    pub const CC1S: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `OC1FE`, bit 2.
    pub const OC1FE: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `OC1PE`, bit 3.
    pub const OC1PE: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `OC1M`, bits 4..=6.
    pub const OC1M: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `OC1CE`, bit 7.
    pub const OC1CE: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `CC2S`, bits 8..=9.
    pub const CC2S: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `OC2FE`, bit 10.
    pub const OC2FE: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `OC2PE`, bit 11.
    pub const OC2PE: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `OC2M`, bits 12..=14.
    pub const OC2M: &FieldSpec = &super::REGISTERS[7].fields[8];
    /// `OC2CE`, bit 15.
    pub const OC2CE: &FieldSpec = &super::REGISTERS[7].fields[9];
}

/// The fields of `CCMR2_Input`.
pub mod ccmr2_input {
    use super::FieldSpec;
    /// `CC3S`, bits 0..=1.
    pub const CC3S: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `IC3PSC`, bits 2..=3.
    pub const IC3PSC: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `IC3F`, bits 4..=7.
    pub const IC3F: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `CC4S`, bits 8..=9.
    pub const CC4S: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `IC4PSC`, bits 10..=11.
    pub const IC4PSC: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `IC4F`, bits 12..=15.
    pub const IC4F: &FieldSpec = &super::REGISTERS[8].fields[5];
}

/// The fields of `CCMR2_Output`.
pub mod ccmr2_output {
    use super::FieldSpec;
    /// `CC3S`, bits 0..=1.
    pub const CC3S: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `OC3FE`, bit 2.
    pub const OC3FE: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `OC3PE`, bit 3.
    pub const OC3PE: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `OC3M`, bits 4..=6.
    pub const OC3M: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `OC3CE`, bit 7.
    pub const OC3CE: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `CC4S`, bits 8..=9.
    pub const CC4S: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `OC4FE`, bit 10.
    pub const OC4FE: &FieldSpec = &super::REGISTERS[9].fields[6];
    /// `OC4PE`, bit 11.
    pub const OC4PE: &FieldSpec = &super::REGISTERS[9].fields[7];
    /// `OC4M`, bits 12..=14.
    pub const OC4M: &FieldSpec = &super::REGISTERS[9].fields[8];
    /// `OC4CE`, bit 15.
    pub const OC4CE: &FieldSpec = &super::REGISTERS[9].fields[9];
}

/// The fields of `CCER`.
pub mod ccer {
    use super::FieldSpec;
    /// `CC1E`, bit 0.
    pub const CC1E: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `CC1P`, bit 1.
    pub const CC1P: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `CC1NP`, bit 3.
    pub const CC1NP: &FieldSpec = &super::REGISTERS[10].fields[2];
    /// `CC2E`, bit 4.
    pub const CC2E: &FieldSpec = &super::REGISTERS[10].fields[3];
    /// `CC2P`, bit 5.
    pub const CC2P: &FieldSpec = &super::REGISTERS[10].fields[4];
    /// `CC2NP`, bit 7.
    pub const CC2NP: &FieldSpec = &super::REGISTERS[10].fields[5];
    /// `CC3E`, bit 8.
    pub const CC3E: &FieldSpec = &super::REGISTERS[10].fields[6];
    /// `CC3P`, bit 9.
    pub const CC3P: &FieldSpec = &super::REGISTERS[10].fields[7];
    /// `CC3NP`, bit 11.
    pub const CC3NP: &FieldSpec = &super::REGISTERS[10].fields[8];
    /// `CC4E`, bit 12.
    pub const CC4E: &FieldSpec = &super::REGISTERS[10].fields[9];
    /// `CC4P`, bit 13.
    pub const CC4P: &FieldSpec = &super::REGISTERS[10].fields[10];
    /// `CC4NP`, bit 15.
    pub const CC4NP: &FieldSpec = &super::REGISTERS[10].fields[11];
}

/// The fields of `CNT`.
pub mod cnt {
    use super::FieldSpec;
    /// `CNT_L`, bits 0..=15.
    pub const CNT_L: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `CNT_H`, bits 16..=31.
    pub const CNT_H: &FieldSpec = &super::REGISTERS[11].fields[1];
}

/// The fields of `PSC`.
pub mod psc {
    use super::FieldSpec;
    /// `PSC`, bits 0..=15.
    pub const PSC: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `ARR`.
pub mod arr {
    use super::FieldSpec;
    /// `ARR_L`, bits 0..=15.
    pub const ARR_L: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `ARR_H`, bits 16..=31.
    pub const ARR_H: &FieldSpec = &super::REGISTERS[13].fields[1];
}

/// The fields of `CCR1`.
pub mod ccr1 {
    use super::FieldSpec;
    /// `CCR1_L`, bits 0..=15.
    pub const CCR1_L: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `CCR1_H`, bits 16..=31.
    pub const CCR1_H: &FieldSpec = &super::REGISTERS[14].fields[1];
}

/// The fields of `CCR2`.
pub mod ccr2 {
    use super::FieldSpec;
    /// `CCR2_L`, bits 0..=15.
    pub const CCR2_L: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `CCR2_H`, bits 16..=31.
    pub const CCR2_H: &FieldSpec = &super::REGISTERS[15].fields[1];
}

/// The fields of `CCR3`.
pub mod ccr3 {
    use super::FieldSpec;
    /// `CCR3_L`, bits 0..=15.
    pub const CCR3_L: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `CCR3_H`, bits 16..=31.
    pub const CCR3_H: &FieldSpec = &super::REGISTERS[16].fields[1];
}

/// The fields of `CCR4`.
pub mod ccr4 {
    use super::FieldSpec;
    /// `CCR4_L`, bits 0..=15.
    pub const CCR4_L: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `CCR4_H`, bits 16..=31.
    pub const CCR4_H: &FieldSpec = &super::REGISTERS[17].fields[1];
}

/// The fields of `DCR`.
pub mod dcr {
    use super::FieldSpec;
    /// `DBA`, bits 0..=4.
    pub const DBA: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `DBL`, bits 8..=12.
    pub const DBL: &FieldSpec = &super::REGISTERS[18].fields[1];
}

/// The fields of `DMAR`.
pub mod dmar {
    use super::FieldSpec;
    /// `DMAB`, bits 0..=15.
    pub const DMAB: &FieldSpec = &super::REGISTERS[19].fields[0];
}

/// The fields of `OR`.
pub mod or {
    use super::FieldSpec;
    /// `IT4_RMP`, bits 6..=7.
    pub const IT4_RMP: &FieldSpec = &super::REGISTERS[20].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 21] = [
    RegisterSpec { name: "CR1", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDIS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "URS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OPM", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMS", bit: 5, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARPE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKD", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCDS", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MMS", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TI1S", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SMCR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SMS", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TS", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSM", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETF", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETPS", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETP", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DIER", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1IE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2IE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC3IE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC4IE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1DE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2DE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC3DE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC4DE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UIF", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1IF", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2IF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC3IF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC4IF", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIF", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1OF", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2OF", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC3OF", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC4OF", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EGR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UG", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1G", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2G", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC3G", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC4G", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TG", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCMR1_Input", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC1S", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ICPCS", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC1F", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2S", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC2PCS", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC2F", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCMR1_Output", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC1S", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC1FE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC1PE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC1M", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC1CE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2S", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC2FE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC2PE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC2M", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC2CE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCMR2_Input", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC3S", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC3PSC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC3F", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC4S", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC4PSC", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC4F", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCMR2_Output", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC3S", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC3FE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC3PE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC3M", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC3CE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC4S", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC4FE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC4PE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC4M", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC4CE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCER", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC1E", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1P", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1NP", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2E", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2P", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC2NP", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC3E", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC3P", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC3NP", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC4E", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC4P", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC4NP", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CNT", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CNT_L", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNT_H", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PSC", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PSC", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ARR", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ARR_L", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARR_H", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCR1", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCR1_L", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCR1_H", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCR2", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCR2_L", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCR2_H", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCR3", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCR3_L", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCR3_H", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCR4", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCR4_L", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCR4_H", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DCR", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DBA", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBL", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMAR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMAB", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OR", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IT4_RMP", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];