rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `Ethernet_DMA` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `DMABMR` at offset `0x0`, resets to `0x0000_2101`, read-write.
    Dmabmr = 0,
    /// `DMATPDR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Dmatpdr = 1,
    /// `DMARPDR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Dmarpdr = 2,
    /// `DMARDLAR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Dmardlar = 3,
    /// `DMATDLAR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Dmatdlar = 4,
    /// `DMASR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Dmasr = 5,
    /// `DMAOMR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Dmaomr = 6,
    /// `DMAIER` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Dmaier = 7,
    /// `DMAMFBOCR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Dmamfbocr = 8,
    /// `DMARSWTR` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Dmarswtr = 9,
    /// `DMACHTDR` at offset `0x48`, resets to `0x0000_0000`, read-only.
    Dmachtdr = 10,
    /// `DMACHRDR` at offset `0x4C`, resets to `0x0000_0000`, read-only.
    Dmachrdr = 11,
    /// `DMACHTBAR` at offset `0x50`, resets to `0x0000_0000`, read-only.
    Dmachtbar = 12,
    /// `DMACHRBAR` at offset `0x54`, resets to `0x0000_0000`, read-only.
    Dmachrbar = 13,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 14] = [Self::Dmabmr, Self::Dmatpdr, Self::Dmarpdr, Self::Dmardlar, Self::Dmatdlar, Self::Dmasr, Self::Dmaomr, Self::Dmaier, Self::Dmamfbocr, Self::Dmarswtr, Self::Dmachtdr, Self::Dmachrdr, Self::Dmachtbar, Self::Dmachrbar];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `DMABMR`.
pub mod dmabmr {
    use super::FieldSpec;
    /// `SR`, bit 0.
    pub const SR: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `DA`, bit 1.
    pub const DA: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `DSL`, bits 2..=6.
    pub const DSL: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `EDFE`, bit 7.
    pub const EDFE: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `PBL`, bits 8..=13.
    pub const PBL: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `RTPR`, bits 14..=15.
    pub const RTPR: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `FB`, bit 16.
    pub const FB: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `RDP`, bits 17..=22.
    pub const RDP: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `USP`, bit 23.
    pub const USP: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `FPM`, bit 24.
    pub const FPM: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `AAB`, bit 25.
    pub const AAB: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `MB`, bit 26.
    pub const MB: &FieldSpec = &super::REGISTERS[0].fields[11];
}

/// The fields of `DMATPDR`.
pub mod dmatpdr {
    use super::FieldSpec;
    /// `TPD`, bits 0..=31.
    pub const TPD: &FieldSpec = &super::REGISTERS[1].fields[0];
}

/// The fields of `DMARPDR`.
pub mod dmarpdr {
    use super::FieldSpec;
    /// `RPD`, bits 0..=31.
    pub const RPD: &FieldSpec = &super::REGISTERS[2].fields[0];
}

/// The fields of `DMARDLAR`.
pub mod dmardlar {
    use super::FieldSpec;
    /// `SRL`, bits 0..=31.
    pub const SRL: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `DMATDLAR`.
pub mod dmatdlar {
    use super::FieldSpec;
    /// `STL`, bits 0..=31.
    pub const STL: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `DMASR`.
pub mod dmasr {
    use super::FieldSpec;
    /// `TS`, bit 0.
    pub const TS: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `TPSS`, bit 1.
    pub const TPSS: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `TBUS`, bit 2.
    pub const TBUS: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `TJTS`, bit 3.
    pub const TJTS: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `ROS`, bit 4.
    pub const ROS: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `TUS`, bit 5.
    pub const TUS: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `RS`, bit 6.
    pub const RS: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `RBUS`, bit 7.
    pub const RBUS: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `RPSS`, bit 8.
    pub const RPSS: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `PWTS`, bit 9.
    pub const PWTS: &FieldSpec = &super::REGISTERS[5].fields[9];
    /// `ETS`, bit 10.
    pub const ETS: &FieldSpec = &super::REGISTERS[5].fields[10];
    /// `FBES`, bit 13.
    pub const FBES: &FieldSpec = &super::REGISTERS[5].fields[11];
    /// `ERS`, bit 14.
    pub const ERS: &FieldSpec = &super::REGISTERS[5].fields[12];
    /// `AIS`, bit 15.
    pub const AIS: &FieldSpec = &super::REGISTERS[5].fields[13];
    /// `NIS`, bit 16.
    pub const NIS: &FieldSpec = &super::REGISTERS[5].fields[14];
    /// `RPS`, bits 17..=19, read-only.
    pub const RPS: &FieldSpec = &super::REGISTERS[5].fields[15];
    /// `TPS`, bits 20..=22, read-only.
    pub const TPS: &FieldSpec = &super::REGISTERS[5].fields[16];
    /// `EBS`, bits 23..=25, read-only.
    pub const EBS: &FieldSpec = &super::REGISTERS[5].fields[17];
    /// `MMCS`, bit 27, read-only.
    pub const MMCS: &FieldSpec = &super::REGISTERS[5].fields[18];
    /// `PMTS`, bit 28, read-only.
    pub const PMTS: &FieldSpec = &super::REGISTERS[5].fields[19];
    /// `TSTS`, bit 29, read-only.
    pub const TSTS: &FieldSpec = &super::REGISTERS[5].fields[20];
}

/// The fields of `DMAOMR`.
pub mod dmaomr {
    use super::FieldSpec;
    /// `SR`, bit 1.
    pub const SR: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `OSF`, bit 2.
    pub const OSF: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `RTC`, bits 3..=4.
    pub const RTC: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `FUGF`, bit 6.
    pub const FUGF: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `FEF`, bit 7.
    pub const FEF: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `ST`, bit 13.
    pub const ST: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `TTC`, bits 14..=16.
    pub const TTC: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `FTF`, bit 20.
    pub const FTF: &FieldSpec = &super::REGISTERS[6].fields[7];
    /// `TSF`, bit 21.
    pub const TSF: &FieldSpec = &super::REGISTERS[6].fields[8];
    /// `DFRF`, bit 24.
    pub const DFRF: &FieldSpec = &super::REGISTERS[6].fields[9];
    /// `RSF`, bit 25.
    pub const RSF: &FieldSpec = &super::REGISTERS[6].fields[10];
    /// `DTCEFD`, bit 26.
    pub const DTCEFD: &FieldSpec = &super::REGISTERS[6].fields[11];
}

/// The fields of `DMAIER`.
pub mod dmaier {
    use super::FieldSpec;
    /// `TIE`, bit 0.
    pub const TIE: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `TPSIE`, bit 1.
    pub const TPSIE: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `TBUIE`, bit 2.
    pub const TBUIE: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `TJTIE`, bit 3.
    pub const TJTIE: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `ROIE`, bit 4.
    pub const ROIE: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `TUIE`, bit 5.
    pub const TUIE: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `RIE`, bit 6.
    pub const RIE: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `RBUIE`, bit 7.
    pub const RBUIE: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `RPSIE`, bit 8.
    pub const RPSIE: &FieldSpec = &super::REGISTERS[7].fields[8];
    /// `RWTIE`, bit 9.
    pub const RWTIE: &FieldSpec = &super::REGISTERS[7].fields[9];
    /// `ETIE`, bit 10.
    pub const ETIE: &FieldSpec = &super::REGISTERS[7].fields[10];
    /// `FBEIE`, bit 13.
    pub const FBEIE: &FieldSpec = &super::REGISTERS[7].fields[11];
    /// `ERIE`, bit 14.
    pub const ERIE: &FieldSpec = &super::REGISTERS[7].fields[12];
    /// `AISE`, bit 15.
    pub const AISE: &FieldSpec = &super::REGISTERS[7].fields[13];
    /// `NISE`, bit 16.
    pub const NISE: &FieldSpec = &super::REGISTERS[7].fields[14];
}

/// The fields of `DMAMFBOCR`.
pub mod dmamfbocr {
    use super::FieldSpec;
    /// `MFC`, bits 0..=15.
    pub const MFC: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `OMFC`, bit 16.
    pub const OMFC: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `MFA`, bits 17..=27.
    pub const MFA: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `OFOC`, bit 28.
    pub const OFOC: &FieldSpec = &super::REGISTERS[8].fields[3];
}

/// The fields of `DMARSWTR`.
pub mod dmarswtr {
    use super::FieldSpec;
    /// `RSWTC`, bits 0..=7.
    pub const RSWTC: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `DMACHTDR`.
pub mod dmachtdr {
    use super::FieldSpec;
    /// `HTDAP`, bits 0..=31.
    pub const HTDAP: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `DMACHRDR`.
pub mod dmachrdr {
    use super::FieldSpec;
    /// `HRDAP`, bits 0..=31.
    pub const HRDAP: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `DMACHTBAR`.
pub mod dmachtbar {
    use super::FieldSpec;
    /// `HTBAP`, bits 0..=31.
    pub const HTBAP: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `DMACHRBAR`.
pub mod dmachrbar {
    use super::FieldSpec;
    /// `HRBAP`, bits 0..=31.
    pub const HRBAP: &FieldSpec = &super::REGISTERS[13].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 14] = [
    RegisterSpec { name: "DMABMR", offset: 0x0, width: Width::W32, reset: 0x0000_2101, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SR", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DA", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DSL", bit: 2, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EDFE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBL", bit: 8, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTPR", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FB", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDP", bit: 17, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USP", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FPM", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AAB", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MB", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMATPDR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TPD", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMARPDR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RPD", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMARDLAR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SRL", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMATDLAR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "STL", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMASR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TS", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TPSS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBUS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TJTS", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROS", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TUS", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RS", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBUS", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RPSS", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWTS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETS", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FBES", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERS", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AIS", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NIS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RPS", bit: 17, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TPS", bit: 20, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EBS", bit: 23, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MMCS", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PMTS", bit: 28, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSTS", bit: 29, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMAOMR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SR", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTC", bit: 3, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FUGF", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEF", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ST", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TTC", bit: 14, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FTF", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSF", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DFRF", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSF", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DTCEFD", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMAIER", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TPSIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBUIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TJTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TUIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBUIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RPSIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWTIE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ETIE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FBEIE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ERIE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AISE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NISE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMAMFBOCR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MFC", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OMFC", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MFA", bit: 17, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFOC", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMARSWTR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RSWTC", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACHTDR", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HTDAP", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACHRDR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HRDAP", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACHTBAR", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HTBAP", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMACHRBAR", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HRBAP", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];