rigless 0.3.0

// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `EXTI` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `IMR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Imr = 0,
    /// `EMR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Emr = 1,
    /// `RTSR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Rtsr = 2,
    /// `FTSR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Ftsr = 3,
    /// `SWIER` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Swier = 4,
    /// `PR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Pr = 5,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 6] = [Self::Imr, Self::Emr, Self::Rtsr, Self::Ftsr, Self::Swier, Self::Pr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `IMR`.
pub mod imr {
    use super::FieldSpec;
    /// `MR0`, bit 0.
    pub const MR0: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `MR1`, bit 1.
    pub const MR1: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `MR2`, bit 2.
    pub const MR2: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `MR3`, bit 3.
    pub const MR3: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `MR4`, bit 4.
    pub const MR4: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `MR5`, bit 5.
    pub const MR5: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `MR6`, bit 6.
    pub const MR6: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `MR7`, bit 7.
    pub const MR7: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `MR8`, bit 8.
    pub const MR8: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `MR9`, bit 9.
    pub const MR9: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `MR10`, bit 10.
    pub const MR10: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `MR11`, bit 11.
    pub const MR11: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `MR12`, bit 12.
    pub const MR12: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `MR13`, bit 13.
    pub const MR13: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `MR14`, bit 14.
    pub const MR14: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `MR15`, bit 15.
    pub const MR15: &FieldSpec = &super::REGISTERS[0].fields[15];
    /// `MR16`, bit 16.
    pub const MR16: &FieldSpec = &super::REGISTERS[0].fields[16];
    /// `MR17`, bit 17.
    pub const MR17: &FieldSpec = &super::REGISTERS[0].fields[17];
    /// `MR18`, bit 18.
    pub const MR18: &FieldSpec = &super::REGISTERS[0].fields[18];
    /// `MR19`, bit 19.
    pub const MR19: &FieldSpec = &super::REGISTERS[0].fields[19];
    /// `MR20`, bit 20.
    pub const MR20: &FieldSpec = &super::REGISTERS[0].fields[20];
    /// `MR21`, bit 21.
    pub const MR21: &FieldSpec = &super::REGISTERS[0].fields[21];
    /// `MR22`, bit 22.
    pub const MR22: &FieldSpec = &super::REGISTERS[0].fields[22];
}

/// The fields of `EMR`.
pub mod emr {
    use super::FieldSpec;
    /// `MR0`, bit 0.
    pub const MR0: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `MR1`, bit 1.
    pub const MR1: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `MR2`, bit 2.
    pub const MR2: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `MR3`, bit 3.
    pub const MR3: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `MR4`, bit 4.
    pub const MR4: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `MR5`, bit 5.
    pub const MR5: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `MR6`, bit 6.
    pub const MR6: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `MR7`, bit 7.
    pub const MR7: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `MR8`, bit 8.
    pub const MR8: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `MR9`, bit 9.
    pub const MR9: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `MR10`, bit 10.
    pub const MR10: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `MR11`, bit 11.
    pub const MR11: &FieldSpec = &super::REGISTERS[1].fields[11];
    /// `MR12`, bit 12.
    pub const MR12: &FieldSpec = &super::REGISTERS[1].fields[12];
    /// `MR13`, bit 13.
    pub const MR13: &FieldSpec = &super::REGISTERS[1].fields[13];
    /// `MR14`, bit 14.
    pub const MR14: &FieldSpec = &super::REGISTERS[1].fields[14];
    /// `MR15`, bit 15.
    pub const MR15: &FieldSpec = &super::REGISTERS[1].fields[15];
    /// `MR16`, bit 16.
    pub const MR16: &FieldSpec = &super::REGISTERS[1].fields[16];
    /// `MR17`, bit 17.
    pub const MR17: &FieldSpec = &super::REGISTERS[1].fields[17];
    /// `MR18`, bit 18.
    pub const MR18: &FieldSpec = &super::REGISTERS[1].fields[18];
    /// `MR19`, bit 19.
    pub const MR19: &FieldSpec = &super::REGISTERS[1].fields[19];
    /// `MR20`, bit 20.
    pub const MR20: &FieldSpec = &super::REGISTERS[1].fields[20];
    /// `MR21`, bit 21.
    pub const MR21: &FieldSpec = &super::REGISTERS[1].fields[21];
    /// `MR22`, bit 22.
    pub const MR22: &FieldSpec = &super::REGISTERS[1].fields[22];
}

/// The fields of `RTSR`.
pub mod rtsr {
    use super::FieldSpec;
    /// `TR0`, bit 0.
    pub const TR0: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `TR1`, bit 1.
    pub const TR1: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `TR2`, bit 2.
    pub const TR2: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `TR3`, bit 3.
    pub const TR3: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `TR4`, bit 4.
    pub const TR4: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `TR5`, bit 5.
    pub const TR5: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `TR6`, bit 6.
    pub const TR6: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `TR7`, bit 7.
    pub const TR7: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `TR8`, bit 8.
    pub const TR8: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `TR9`, bit 9.
    pub const TR9: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `TR10`, bit 10.
    pub const TR10: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `TR11`, bit 11.
    pub const TR11: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `TR12`, bit 12.
    pub const TR12: &FieldSpec = &super::REGISTERS[2].fields[12];
    /// `TR13`, bit 13.
    pub const TR13: &FieldSpec = &super::REGISTERS[2].fields[13];
    /// `TR14`, bit 14.
    pub const TR14: &FieldSpec = &super::REGISTERS[2].fields[14];
    /// `TR15`, bit 15.
    pub const TR15: &FieldSpec = &super::REGISTERS[2].fields[15];
    /// `TR16`, bit 16.
    pub const TR16: &FieldSpec = &super::REGISTERS[2].fields[16];
    /// `TR17`, bit 17.
    pub const TR17: &FieldSpec = &super::REGISTERS[2].fields[17];
    /// `TR18`, bit 18.
    pub const TR18: &FieldSpec = &super::REGISTERS[2].fields[18];
    /// `TR19`, bit 19.
    pub const TR19: &FieldSpec = &super::REGISTERS[2].fields[19];
    /// `TR20`, bit 20.
    pub const TR20: &FieldSpec = &super::REGISTERS[2].fields[20];
    /// `TR21`, bit 21.
    pub const TR21: &FieldSpec = &super::REGISTERS[2].fields[21];
    /// `TR22`, bit 22.
    pub const TR22: &FieldSpec = &super::REGISTERS[2].fields[22];
}

/// The fields of `FTSR`.
pub mod ftsr {
    use super::FieldSpec;
    /// `TR0`, bit 0.
    pub const TR0: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `TR1`, bit 1.
    pub const TR1: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `TR2`, bit 2.
    pub const TR2: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `TR3`, bit 3.
    pub const TR3: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `TR4`, bit 4.
    pub const TR4: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `TR5`, bit 5.
    pub const TR5: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `TR6`, bit 6.
    pub const TR6: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `TR7`, bit 7.
    pub const TR7: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `TR8`, bit 8.
    pub const TR8: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `TR9`, bit 9.
    pub const TR9: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `TR10`, bit 10.
    pub const TR10: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `TR11`, bit 11.
    pub const TR11: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `TR12`, bit 12.
    pub const TR12: &FieldSpec = &super::REGISTERS[3].fields[12];
    /// `TR13`, bit 13.
    pub const TR13: &FieldSpec = &super::REGISTERS[3].fields[13];
    /// `TR14`, bit 14.
    pub const TR14: &FieldSpec = &super::REGISTERS[3].fields[14];
    /// `TR15`, bit 15.
    pub const TR15: &FieldSpec = &super::REGISTERS[3].fields[15];
    /// `TR16`, bit 16.
    pub const TR16: &FieldSpec = &super::REGISTERS[3].fields[16];
    /// `TR17`, bit 17.
    pub const TR17: &FieldSpec = &super::REGISTERS[3].fields[17];
    /// `TR18`, bit 18.
    pub const TR18: &FieldSpec = &super::REGISTERS[3].fields[18];
    /// `TR19`, bit 19.
    pub const TR19: &FieldSpec = &super::REGISTERS[3].fields[19];
    /// `TR20`, bit 20.
    pub const TR20: &FieldSpec = &super::REGISTERS[3].fields[20];
    /// `TR21`, bit 21.
    pub const TR21: &FieldSpec = &super::REGISTERS[3].fields[21];
    /// `TR22`, bit 22.
    pub const TR22: &FieldSpec = &super::REGISTERS[3].fields[22];
}

/// The fields of `SWIER`.
pub mod swier {
    use super::FieldSpec;
    /// `SWIER0`, bit 0.
    pub const SWIER0: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `SWIER1`, bit 1.
    pub const SWIER1: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `SWIER2`, bit 2.
    pub const SWIER2: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `SWIER3`, bit 3.
    pub const SWIER3: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `SWIER4`, bit 4.
    pub const SWIER4: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `SWIER5`, bit 5.
    pub const SWIER5: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `SWIER6`, bit 6.
    pub const SWIER6: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `SWIER7`, bit 7.
    pub const SWIER7: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `SWIER8`, bit 8.
    pub const SWIER8: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `SWIER9`, bit 9.
    pub const SWIER9: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `SWIER10`, bit 10.
    pub const SWIER10: &FieldSpec = &super::REGISTERS[4].fields[10];
    /// `SWIER11`, bit 11.
    pub const SWIER11: &FieldSpec = &super::REGISTERS[4].fields[11];
    /// `SWIER12`, bit 12.
    pub const SWIER12: &FieldSpec = &super::REGISTERS[4].fields[12];
    /// `SWIER13`, bit 13.
    pub const SWIER13: &FieldSpec = &super::REGISTERS[4].fields[13];
    /// `SWIER14`, bit 14.
    pub const SWIER14: &FieldSpec = &super::REGISTERS[4].fields[14];
    /// `SWIER15`, bit 15.
    pub const SWIER15: &FieldSpec = &super::REGISTERS[4].fields[15];
    /// `SWIER16`, bit 16.
    pub const SWIER16: &FieldSpec = &super::REGISTERS[4].fields[16];
    /// `SWIER17`, bit 17.
    pub const SWIER17: &FieldSpec = &super::REGISTERS[4].fields[17];
    /// `SWIER18`, bit 18.
    pub const SWIER18: &FieldSpec = &super::REGISTERS[4].fields[18];
    /// `SWIER19`, bit 19.
    pub const SWIER19: &FieldSpec = &super::REGISTERS[4].fields[19];
    /// `SWIER20`, bit 20.
    pub const SWIER20: &FieldSpec = &super::REGISTERS[4].fields[20];
    /// `SWIER21`, bit 21.
    pub const SWIER21: &FieldSpec = &super::REGISTERS[4].fields[21];
    /// `SWIER22`, bit 22.
    pub const SWIER22: &FieldSpec = &super::REGISTERS[4].fields[22];
}

/// The fields of `PR`.
pub mod pr {
    use super::FieldSpec;
    /// `PR0`, bit 0.
    pub const PR0: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `PR1`, bit 1.
    pub const PR1: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `PR2`, bit 2.
    pub const PR2: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `PR3`, bit 3.
    pub const PR3: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `PR4`, bit 4.
    pub const PR4: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `PR5`, bit 5.
    pub const PR5: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `PR6`, bit 6.
    pub const PR6: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `PR7`, bit 7.
    pub const PR7: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `PR8`, bit 8.
    pub const PR8: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `PR9`, bit 9.
    pub const PR9: &FieldSpec = &super::REGISTERS[5].fields[9];
    /// `PR10`, bit 10.
    pub const PR10: &FieldSpec = &super::REGISTERS[5].fields[10];
    /// `PR11`, bit 11.
    pub const PR11: &FieldSpec = &super::REGISTERS[5].fields[11];
    /// `PR12`, bit 12.
    pub const PR12: &FieldSpec = &super::REGISTERS[5].fields[12];
    /// `PR13`, bit 13.
    pub const PR13: &FieldSpec = &super::REGISTERS[5].fields[13];
    /// `PR14`, bit 14.
    pub const PR14: &FieldSpec = &super::REGISTERS[5].fields[14];
    /// `PR15`, bit 15.
    pub const PR15: &FieldSpec = &super::REGISTERS[5].fields[15];
    /// `PR16`, bit 16.
    pub const PR16: &FieldSpec = &super::REGISTERS[5].fields[16];
    /// `PR17`, bit 17.
    pub const PR17: &FieldSpec = &super::REGISTERS[5].fields[17];
    /// `PR18`, bit 18.
    pub const PR18: &FieldSpec = &super::REGISTERS[5].fields[18];
    /// `PR19`, bit 19.
    pub const PR19: &FieldSpec = &super::REGISTERS[5].fields[19];
    /// `PR20`, bit 20.
    pub const PR20: &FieldSpec = &super::REGISTERS[5].fields[20];
    /// `PR21`, bit 21.
    pub const PR21: &FieldSpec = &super::REGISTERS[5].fields[21];
    /// `PR22`, bit 22.
    pub const PR22: &FieldSpec = &super::REGISTERS[5].fields[22];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 6] = [
    RegisterSpec { name: "IMR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR22", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EMR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MR22", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RTSR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR22", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FTSR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TR22", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SWIER", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SWIER0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWIER22", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PR0", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR1", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR2", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR3", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR4", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR5", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR6", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR7", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR8", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR9", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR10", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR11", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR12", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR13", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR14", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR15", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR16", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR17", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR18", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR19", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR20", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR21", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PR22", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];