rigless 0.3.0

// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `FMC` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `BCR1` at offset `0x0`, resets to `0x0000_30D0`, read-write.
    Bcr1 = 0,
    /// `BTR1` at offset `0x4`, resets to `0xFFFF_FFFF`, read-write.
    Btr1 = 1,
    /// `BCR2` at offset `0x8`, resets to `0x0000_30D0`, read-write.
    Bcr2 = 2,
    /// `BTR2` at offset `0xC`, resets to `0xFFFF_FFFF`, read-write.
    Btr2 = 3,
    /// `BCR3` at offset `0x10`, resets to `0x0000_30D0`, read-write.
    Bcr3 = 4,
    /// `BTR3` at offset `0x14`, resets to `0xFFFF_FFFF`, read-write.
    Btr3 = 5,
    /// `BCR4` at offset `0x18`, resets to `0x0000_30D0`, read-write.
    Bcr4 = 6,
    /// `BTR4` at offset `0x1C`, resets to `0xFFFF_FFFF`, read-write.
    Btr4 = 7,
    /// `PCR2` at offset `0x60`, resets to `0x0000_0018`, read-write.
    Pcr2 = 8,
    /// `SR2` at offset `0x64`, resets to `0x0000_0040`, read-write.
    Sr2 = 9,
    /// `PMEM2` at offset `0x68`, resets to `0xFCFC_FCFC`, read-write.
    Pmem2 = 10,
    /// `PATT2` at offset `0x6C`, resets to `0xFCFC_FCFC`, read-write.
    Patt2 = 11,
    /// `ECCR2` at offset `0x74`, resets to `0x0000_0000`, read-only.
    Eccr2 = 12,
    /// `PCR3` at offset `0x80`, resets to `0x0000_0018`, read-write.
    Pcr3 = 13,
    /// `SR3` at offset `0x84`, resets to `0x0000_0040`, read-write.
    Sr3 = 14,
    /// `PMEM3` at offset `0x88`, resets to `0xFCFC_FCFC`, read-write.
    Pmem3 = 15,
    /// `PATT3` at offset `0x8C`, resets to `0xFCFC_FCFC`, read-write.
    Patt3 = 16,
    /// `ECCR3` at offset `0x94`, resets to `0x0000_0000`, read-only.
    Eccr3 = 17,
    /// `PCR4` at offset `0xA0`, resets to `0x0000_0018`, read-write.
    Pcr4 = 18,
    /// `SR4` at offset `0xA4`, resets to `0x0000_0040`, read-write.
    Sr4 = 19,
    /// `PMEM4` at offset `0xA8`, resets to `0xFCFC_FCFC`, read-write.
    Pmem4 = 20,
    /// `PATT4` at offset `0xAC`, resets to `0xFCFC_FCFC`, read-write.
    Patt4 = 21,
    /// `PIO4` at offset `0xB0`, resets to `0xFCFC_FCFC`, read-write.
    Pio4 = 22,
    /// `BWTR1` at offset `0x104`, resets to `0x0FFF_FFFF`, read-write.
    Bwtr1 = 23,
    /// `BWTR3` at offset `0x104`, resets to `0x0FFF_FFFF`, read-write.
    Bwtr3 = 24,
    /// `BWTR2` at offset `0x10C`, resets to `0x0FFF_FFFF`, read-write.
    Bwtr2 = 25,
    /// `BWTR4` at offset `0x10C`, resets to `0x0FFF_FFFF`, read-write.
    Bwtr4 = 26,
    /// `SDCR1` at offset `0x140`, resets to `0x0000_02D0`, read-write.
    Sdcr1 = 27,
    /// `SDCR2` at offset `0x144`, resets to `0x0000_02D0`, read-write.
    Sdcr2 = 28,
    /// `SDTR1` at offset `0x148`, resets to `0x0FFF_FFFF`, read-write.
    Sdtr1 = 29,
    /// `SDTR2` at offset `0x14C`, resets to `0x0FFF_FFFF`, read-write.
    Sdtr2 = 30,
    /// `SDCMR` at offset `0x150`, resets to `0x0000_0000`, read-write.
    Sdcmr = 31,
    /// `SDRTR` at offset `0x154`, resets to `0x0000_0000`, read-write.
    Sdrtr = 32,
    /// `SDSR` at offset `0x158`, resets to `0x0000_0000`, read-only.
    Sdsr = 33,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 34] = [Self::Bcr1, Self::Btr1, Self::Bcr2, Self::Btr2, Self::Bcr3, Self::Btr3, Self::Bcr4, Self::Btr4, Self::Pcr2, Self::Sr2, Self::Pmem2, Self::Patt2, Self::Eccr2, Self::Pcr3, Self::Sr3, Self::Pmem3, Self::Patt3, Self::Eccr3, Self::Pcr4, Self::Sr4, Self::Pmem4, Self::Patt4, Self::Pio4, Self::Bwtr1, Self::Bwtr3, Self::Bwtr2, Self::Bwtr4, Self::Sdcr1, Self::Sdcr2, Self::Sdtr1, Self::Sdtr2, Self::Sdcmr, Self::Sdrtr, Self::Sdsr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `BCR1`.
pub mod bcr1 {
    use super::FieldSpec;
    /// `MBKEN`, bit 0.
    pub const MBKEN: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `MUXEN`, bit 1.
    pub const MUXEN: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `MTYP`, bits 2..=3.
    pub const MTYP: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `MWID`, bits 4..=5.
    pub const MWID: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `FACCEN`, bit 6.
    pub const FACCEN: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `BURSTEN`, bit 8.
    pub const BURSTEN: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `WAITPOL`, bit 9.
    pub const WAITPOL: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `WRAPMOD`, bit 10.
    pub const WRAPMOD: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `WAITCFG`, bit 11.
    pub const WAITCFG: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `WREN`, bit 12.
    pub const WREN: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `WAITEN`, bit 13.
    pub const WAITEN: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `EXTMOD`, bit 14.
    pub const EXTMOD: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `ASYNCWAIT`, bit 15.
    pub const ASYNCWAIT: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `CPSIZE`, bits 16..=18.
    pub const CPSIZE: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `CBURSTRW`, bit 19.
    pub const CBURSTRW: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `CCLKEN`, bit 20.
    pub const CCLKEN: &FieldSpec = &super::REGISTERS[0].fields[15];
}

/// The fields of `BTR1`.
pub mod btr1 {
    use super::FieldSpec;
    /// `ADDSET`, bits 0..=3.
    pub const ADDSET: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `ADDHLD`, bits 4..=7.
    pub const ADDHLD: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `DATAST`, bits 8..=15.
    pub const DATAST: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `BUSTURN`, bits 16..=19.
    pub const BUSTURN: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `CLKDIV`, bits 20..=23.
    pub const CLKDIV: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `DATLAT`, bits 24..=27.
    pub const DATLAT: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `ACCMOD`, bits 28..=29.
    pub const ACCMOD: &FieldSpec = &super::REGISTERS[1].fields[6];
}

/// The fields of `BCR2`.
pub mod bcr2 {
    use super::FieldSpec;
    /// `MBKEN`, bit 0.
    pub const MBKEN: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `MUXEN`, bit 1.
    pub const MUXEN: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `MTYP`, bits 2..=3.
    pub const MTYP: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `MWID`, bits 4..=5.
    pub const MWID: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `FACCEN`, bit 6.
    pub const FACCEN: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `BURSTEN`, bit 8.
    pub const BURSTEN: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `WAITPOL`, bit 9.
    pub const WAITPOL: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `WRAPMOD`, bit 10.
    pub const WRAPMOD: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `WAITCFG`, bit 11.
    pub const WAITCFG: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `WREN`, bit 12.
    pub const WREN: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `WAITEN`, bit 13.
    pub const WAITEN: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `EXTMOD`, bit 14.
    pub const EXTMOD: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `ASYNCWAIT`, bit 15.
    pub const ASYNCWAIT: &FieldSpec = &super::REGISTERS[2].fields[12];
    /// `CPSIZE`, bits 16..=18.
    pub const CPSIZE: &FieldSpec = &super::REGISTERS[2].fields[13];
    /// `CBURSTRW`, bit 19.
    pub const CBURSTRW: &FieldSpec = &super::REGISTERS[2].fields[14];
}

/// The fields of `BTR2`.
pub mod btr2 {
    use super::FieldSpec;
    /// `ADDSET`, bits 0..=3.
    pub const ADDSET: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `ADDHLD`, bits 4..=7.
    pub const ADDHLD: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `DATAST`, bits 8..=15.
    pub const DATAST: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `BUSTURN`, bits 16..=19.
    pub const BUSTURN: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `CLKDIV`, bits 20..=23.
    pub const CLKDIV: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `DATLAT`, bits 24..=27.
    pub const DATLAT: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `ACCMOD`, bits 28..=29.
    pub const ACCMOD: &FieldSpec = &super::REGISTERS[3].fields[6];
}

/// The fields of `BCR3`.
pub mod bcr3 {
    use super::FieldSpec;
    /// `MBKEN`, bit 0.
    pub const MBKEN: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `MUXEN`, bit 1.
    pub const MUXEN: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `MTYP`, bits 2..=3.
    pub const MTYP: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `MWID`, bits 4..=5.
    pub const MWID: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `FACCEN`, bit 6.
    pub const FACCEN: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `BURSTEN`, bit 8.
    pub const BURSTEN: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `WAITPOL`, bit 9.
    pub const WAITPOL: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `WRAPMOD`, bit 10.
    pub const WRAPMOD: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `WAITCFG`, bit 11.
    pub const WAITCFG: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `WREN`, bit 12.
    pub const WREN: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `WAITEN`, bit 13.
    pub const WAITEN: &FieldSpec = &super::REGISTERS[4].fields[10];
    /// `EXTMOD`, bit 14.
    pub const EXTMOD: &FieldSpec = &super::REGISTERS[4].fields[11];
    /// `ASYNCWAIT`, bit 15.
    pub const ASYNCWAIT: &FieldSpec = &super::REGISTERS[4].fields[12];
    /// `CPSIZE`, bits 16..=18.
    pub const CPSIZE: &FieldSpec = &super::REGISTERS[4].fields[13];
    /// `CBURSTRW`, bit 19.
    pub const CBURSTRW: &FieldSpec = &super::REGISTERS[4].fields[14];
}

/// The fields of `BTR3`.
pub mod btr3 {
    use super::FieldSpec;
    /// `ADDSET`, bits 0..=3.
    pub const ADDSET: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `ADDHLD`, bits 4..=7.
    pub const ADDHLD: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `DATAST`, bits 8..=15.
    pub const DATAST: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `BUSTURN`, bits 16..=19.
    pub const BUSTURN: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `CLKDIV`, bits 20..=23.
    pub const CLKDIV: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `DATLAT`, bits 24..=27.
    pub const DATLAT: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `ACCMOD`, bits 28..=29.
    pub const ACCMOD: &FieldSpec = &super::REGISTERS[5].fields[6];
}

/// The fields of `BCR4`.
pub mod bcr4 {
    use super::FieldSpec;
    /// `MBKEN`, bit 0.
    pub const MBKEN: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `MUXEN`, bit 1.
    pub const MUXEN: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `MTYP`, bits 2..=3.
    pub const MTYP: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `MWID`, bits 4..=5.
    pub const MWID: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `FACCEN`, bit 6.
    pub const FACCEN: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `BURSTEN`, bit 8.
    pub const BURSTEN: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `WAITPOL`, bit 9.
    pub const WAITPOL: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `WRAPMOD`, bit 10.
    pub const WRAPMOD: &FieldSpec = &super::REGISTERS[6].fields[7];
    /// `WAITCFG`, bit 11.
    pub const WAITCFG: &FieldSpec = &super::REGISTERS[6].fields[8];
    /// `WREN`, bit 12.
    pub const WREN: &FieldSpec = &super::REGISTERS[6].fields[9];
    /// `WAITEN`, bit 13.
    pub const WAITEN: &FieldSpec = &super::REGISTERS[6].fields[10];
    /// `EXTMOD`, bit 14.
    pub const EXTMOD: &FieldSpec = &super::REGISTERS[6].fields[11];
    /// `ASYNCWAIT`, bit 15.
    pub const ASYNCWAIT: &FieldSpec = &super::REGISTERS[6].fields[12];
    /// `CPSIZE`, bits 16..=18.
    pub const CPSIZE: &FieldSpec = &super::REGISTERS[6].fields[13];
    /// `CBURSTRW`, bit 19.
    pub const CBURSTRW: &FieldSpec = &super::REGISTERS[6].fields[14];
}

/// The fields of `BTR4`.
pub mod btr4 {
    use super::FieldSpec;
    /// `ADDSET`, bits 0..=3.
    pub const ADDSET: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `ADDHLD`, bits 4..=7.
    pub const ADDHLD: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `DATAST`, bits 8..=15.
    pub const DATAST: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `BUSTURN`, bits 16..=19.
    pub const BUSTURN: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `CLKDIV`, bits 20..=23.
    pub const CLKDIV: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `DATLAT`, bits 24..=27.
    pub const DATLAT: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `ACCMOD`, bits 28..=29.
    pub const ACCMOD: &FieldSpec = &super::REGISTERS[7].fields[6];
}

/// The fields of `PCR2`.
pub mod pcr2 {
    use super::FieldSpec;
    /// `PWAITEN`, bit 1.
    pub const PWAITEN: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `PBKEN`, bit 2.
    pub const PBKEN: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `PTYP`, bit 3.
    pub const PTYP: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `PWID`, bits 4..=5.
    pub const PWID: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `ECCEN`, bit 6.
    pub const ECCEN: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `TCLR`, bits 9..=12.
    pub const TCLR: &FieldSpec = &super::REGISTERS[8].fields[5];
    /// `TAR`, bits 13..=16.
    pub const TAR: &FieldSpec = &super::REGISTERS[8].fields[6];
    /// `ECCPS`, bits 17..=19.
    pub const ECCPS: &FieldSpec = &super::REGISTERS[8].fields[7];
}

/// The fields of `SR2`.
pub mod sr2 {
    use super::FieldSpec;
    /// `IRS`, bit 0.
    pub const IRS: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `ILS`, bit 1.
    pub const ILS: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `IFS`, bit 2.
    pub const IFS: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `IREN`, bit 3.
    pub const IREN: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `ILEN`, bit 4.
    pub const ILEN: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `IFEN`, bit 5.
    pub const IFEN: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `FEMPT`, bit 6, read-only.
    pub const FEMPT: &FieldSpec = &super::REGISTERS[9].fields[6];
}

/// The fields of `PMEM2`.
pub mod pmem2 {
    use super::FieldSpec;
    /// `MEMSETx`, bits 0..=7.
    pub const MEMSETX: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `MEMWAITx`, bits 8..=15.
    pub const MEMWAITX: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `MEMHOLDx`, bits 16..=23.
    pub const MEMHOLDX: &FieldSpec = &super::REGISTERS[10].fields[2];
    /// `MEMHIZx`, bits 24..=31.
    pub const MEMHIZX: &FieldSpec = &super::REGISTERS[10].fields[3];
}

/// The fields of `PATT2`.
pub mod patt2 {
    use super::FieldSpec;
    /// `ATTSETx`, bits 0..=7.
    pub const ATTSETX: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `ATTWAITx`, bits 8..=15.
    pub const ATTWAITX: &FieldSpec = &super::REGISTERS[11].fields[1];
    /// `ATTHOLDx`, bits 16..=23.
    pub const ATTHOLDX: &FieldSpec = &super::REGISTERS[11].fields[2];
    /// `ATTHIZx`, bits 24..=31.
    pub const ATTHIZX: &FieldSpec = &super::REGISTERS[11].fields[3];
}

/// The fields of `ECCR2`.
pub mod eccr2 {
    use super::FieldSpec;
    /// `ECCx`, bits 0..=31.
    pub const ECCX: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `PCR3`.
pub mod pcr3 {
    use super::FieldSpec;
    /// `PWAITEN`, bit 1.
    pub const PWAITEN: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `PBKEN`, bit 2.
    pub const PBKEN: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `PTYP`, bit 3.
    pub const PTYP: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `PWID`, bits 4..=5.
    pub const PWID: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `ECCEN`, bit 6.
    pub const ECCEN: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `TCLR`, bits 9..=12.
    pub const TCLR: &FieldSpec = &super::REGISTERS[13].fields[5];
    /// `TAR`, bits 13..=16.
    pub const TAR: &FieldSpec = &super::REGISTERS[13].fields[6];
    /// `ECCPS`, bits 17..=19.
    pub const ECCPS: &FieldSpec = &super::REGISTERS[13].fields[7];
}

/// The fields of `SR3`.
pub mod sr3 {
    use super::FieldSpec;
    /// `IRS`, bit 0.
    pub const IRS: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `ILS`, bit 1.
    pub const ILS: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `IFS`, bit 2.
    pub const IFS: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `IREN`, bit 3.
    pub const IREN: &FieldSpec = &super::REGISTERS[14].fields[3];
    /// `ILEN`, bit 4.
    pub const ILEN: &FieldSpec = &super::REGISTERS[14].fields[4];
    /// `IFEN`, bit 5.
    pub const IFEN: &FieldSpec = &super::REGISTERS[14].fields[5];
    /// `FEMPT`, bit 6, read-only.
    pub const FEMPT: &FieldSpec = &super::REGISTERS[14].fields[6];
}

/// The fields of `PMEM3`.
pub mod pmem3 {
    use super::FieldSpec;
    /// `MEMSETx`, bits 0..=7.
    pub const MEMSETX: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `MEMWAITx`, bits 8..=15.
    pub const MEMWAITX: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `MEMHOLDx`, bits 16..=23.
    pub const MEMHOLDX: &FieldSpec = &super::REGISTERS[15].fields[2];
    /// `MEMHIZx`, bits 24..=31.
    pub const MEMHIZX: &FieldSpec = &super::REGISTERS[15].fields[3];
}

/// The fields of `PATT3`.
pub mod patt3 {
    use super::FieldSpec;
    /// `ATTSETx`, bits 0..=7.
    pub const ATTSETX: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `ATTWAITx`, bits 8..=15.
    pub const ATTWAITX: &FieldSpec = &super::REGISTERS[16].fields[1];
    /// `ATTHOLDx`, bits 16..=23.
    pub const ATTHOLDX: &FieldSpec = &super::REGISTERS[16].fields[2];
    /// `ATTHIZx`, bits 24..=31.
    pub const ATTHIZX: &FieldSpec = &super::REGISTERS[16].fields[3];
}

/// The fields of `ECCR3`.
pub mod eccr3 {
    use super::FieldSpec;
    /// `ECCx`, bits 0..=31.
    pub const ECCX: &FieldSpec = &super::REGISTERS[17].fields[0];
}

/// The fields of `PCR4`.
pub mod pcr4 {
    use super::FieldSpec;
    /// `PWAITEN`, bit 1.
    pub const PWAITEN: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `PBKEN`, bit 2.
    pub const PBKEN: &FieldSpec = &super::REGISTERS[18].fields[1];
    /// `PTYP`, bit 3.
    pub const PTYP: &FieldSpec = &super::REGISTERS[18].fields[2];
    /// `PWID`, bits 4..=5.
    pub const PWID: &FieldSpec = &super::REGISTERS[18].fields[3];
    /// `ECCEN`, bit 6.
    pub const ECCEN: &FieldSpec = &super::REGISTERS[18].fields[4];
    /// `TCLR`, bits 9..=12.
    pub const TCLR: &FieldSpec = &super::REGISTERS[18].fields[5];
    /// `TAR`, bits 13..=16.
    pub const TAR: &FieldSpec = &super::REGISTERS[18].fields[6];
    /// `ECCPS`, bits 17..=19.
    pub const ECCPS: &FieldSpec = &super::REGISTERS[18].fields[7];
}

/// The fields of `SR4`.
pub mod sr4 {
    use super::FieldSpec;
    /// `IRS`, bit 0.
    pub const IRS: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `ILS`, bit 1.
    pub const ILS: &FieldSpec = &super::REGISTERS[19].fields[1];
    /// `IFS`, bit 2.
    pub const IFS: &FieldSpec = &super::REGISTERS[19].fields[2];
    /// `IREN`, bit 3.
    pub const IREN: &FieldSpec = &super::REGISTERS[19].fields[3];
    /// `ILEN`, bit 4.
    pub const ILEN: &FieldSpec = &super::REGISTERS[19].fields[4];
    /// `IFEN`, bit 5.
    pub const IFEN: &FieldSpec = &super::REGISTERS[19].fields[5];
    /// `FEMPT`, bit 6, read-only.
    pub const FEMPT: &FieldSpec = &super::REGISTERS[19].fields[6];
}

/// The fields of `PMEM4`.
pub mod pmem4 {
    use super::FieldSpec;
    /// `MEMSETx`, bits 0..=7.
    pub const MEMSETX: &FieldSpec = &super::REGISTERS[20].fields[0];
    /// `MEMWAITx`, bits 8..=15.
    pub const MEMWAITX: &FieldSpec = &super::REGISTERS[20].fields[1];
    /// `MEMHOLDx`, bits 16..=23.
    pub const MEMHOLDX: &FieldSpec = &super::REGISTERS[20].fields[2];
    /// `MEMHIZx`, bits 24..=31.
    pub const MEMHIZX: &FieldSpec = &super::REGISTERS[20].fields[3];
}

/// The fields of `PATT4`.
pub mod patt4 {
    use super::FieldSpec;
    /// `ATTSETx`, bits 0..=7.
    pub const ATTSETX: &FieldSpec = &super::REGISTERS[21].fields[0];
    /// `ATTWAITx`, bits 8..=15.
    pub const ATTWAITX: &FieldSpec = &super::REGISTERS[21].fields[1];
    /// `ATTHOLDx`, bits 16..=23.
    pub const ATTHOLDX: &FieldSpec = &super::REGISTERS[21].fields[2];
    /// `ATTHIZx`, bits 24..=31.
    pub const ATTHIZX: &FieldSpec = &super::REGISTERS[21].fields[3];
}

/// The fields of `PIO4`.
pub mod pio4 {
    use super::FieldSpec;
    /// `IOSETx`, bits 0..=7.
    pub const IOSETX: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `IOWAITx`, bits 8..=15.
    pub const IOWAITX: &FieldSpec = &super::REGISTERS[22].fields[1];
    /// `IOHOLDx`, bits 16..=23.
    pub const IOHOLDX: &FieldSpec = &super::REGISTERS[22].fields[2];
    /// `IOHIZx`, bits 24..=31.
    pub const IOHIZX: &FieldSpec = &super::REGISTERS[22].fields[3];
}

/// The fields of `BWTR1`.
pub mod bwtr1 {
    use super::FieldSpec;
    /// `ADDSET`, bits 0..=3.
    pub const ADDSET: &FieldSpec = &super::REGISTERS[23].fields[0];
    /// `ADDHLD`, bits 4..=7.
    pub const ADDHLD: &FieldSpec = &super::REGISTERS[23].fields[1];
    /// `DATAST`, bits 8..=15.
    pub const DATAST: &FieldSpec = &super::REGISTERS[23].fields[2];
    /// `BUSTURN`, bits 16..=19.
    pub const BUSTURN: &FieldSpec = &super::REGISTERS[23].fields[3];
    /// `ACCMOD`, bits 28..=29.
    pub const ACCMOD: &FieldSpec = &super::REGISTERS[23].fields[4];
}

/// The fields of `BWTR3`.
pub mod bwtr3 {
    use super::FieldSpec;
    /// `ADDSET`, bits 0..=3.
    pub const ADDSET: &FieldSpec = &super::REGISTERS[24].fields[0];
    /// `ADDHLD`, bits 4..=7.
    pub const ADDHLD: &FieldSpec = &super::REGISTERS[24].fields[1];
    /// `DATAST`, bits 8..=15.
    pub const DATAST: &FieldSpec = &super::REGISTERS[24].fields[2];
    /// `BUSTURN`, bits 16..=19.
    pub const BUSTURN: &FieldSpec = &super::REGISTERS[24].fields[3];
    /// `ACCMOD`, bits 28..=29.
    pub const ACCMOD: &FieldSpec = &super::REGISTERS[24].fields[4];
}

/// The fields of `BWTR2`.
pub mod bwtr2 {
    use super::FieldSpec;
    /// `ADDSET`, bits 0..=3.
    pub const ADDSET: &FieldSpec = &super::REGISTERS[25].fields[0];
    /// `ADDHLD`, bits 4..=7.
    pub const ADDHLD: &FieldSpec = &super::REGISTERS[25].fields[1];
    /// `DATAST`, bits 8..=15.
    pub const DATAST: &FieldSpec = &super::REGISTERS[25].fields[2];
    /// `BUSTURN`, bits 16..=19.
    pub const BUSTURN: &FieldSpec = &super::REGISTERS[25].fields[3];
    /// `ACCMOD`, bits 28..=29.
    pub const ACCMOD: &FieldSpec = &super::REGISTERS[25].fields[4];
}

/// The fields of `BWTR4`.
pub mod bwtr4 {
    use super::FieldSpec;
    /// `ADDSET`, bits 0..=3.
    pub const ADDSET: &FieldSpec = &super::REGISTERS[26].fields[0];
    /// `ADDHLD`, bits 4..=7.
    pub const ADDHLD: &FieldSpec = &super::REGISTERS[26].fields[1];
    /// `DATAST`, bits 8..=15.
    pub const DATAST: &FieldSpec = &super::REGISTERS[26].fields[2];
    /// `BUSTURN`, bits 16..=19.
    pub const BUSTURN: &FieldSpec = &super::REGISTERS[26].fields[3];
    /// `ACCMOD`, bits 28..=29.
    pub const ACCMOD: &FieldSpec = &super::REGISTERS[26].fields[4];
}

/// The fields of `SDCR1`.
pub mod sdcr1 {
    use super::FieldSpec;
    /// `NC`, bits 0..=1.
    pub const NC: &FieldSpec = &super::REGISTERS[27].fields[0];
    /// `NR`, bits 2..=3.
    pub const NR: &FieldSpec = &super::REGISTERS[27].fields[1];
    /// `MWID`, bits 4..=5.
    pub const MWID: &FieldSpec = &super::REGISTERS[27].fields[2];
    /// `NB`, bit 6.
    pub const NB: &FieldSpec = &super::REGISTERS[27].fields[3];
    /// `CAS`, bits 7..=8.
    pub const CAS: &FieldSpec = &super::REGISTERS[27].fields[4];
    /// `WP`, bit 9.
    pub const WP: &FieldSpec = &super::REGISTERS[27].fields[5];
    /// `SDCLK`, bits 10..=11.
    pub const SDCLK: &FieldSpec = &super::REGISTERS[27].fields[6];
    /// `RBURST`, bit 12.
    pub const RBURST: &FieldSpec = &super::REGISTERS[27].fields[7];
    /// `RPIPE`, bits 13..=14.
    pub const RPIPE: &FieldSpec = &super::REGISTERS[27].fields[8];
}

/// The fields of `SDCR2`.
pub mod sdcr2 {
    use super::FieldSpec;
    /// `NC`, bits 0..=1.
    pub const NC: &FieldSpec = &super::REGISTERS[28].fields[0];
    /// `NR`, bits 2..=3.
    pub const NR: &FieldSpec = &super::REGISTERS[28].fields[1];
    /// `MWID`, bits 4..=5.
    pub const MWID: &FieldSpec = &super::REGISTERS[28].fields[2];
    /// `NB`, bit 6.
    pub const NB: &FieldSpec = &super::REGISTERS[28].fields[3];
    /// `CAS`, bits 7..=8.
    pub const CAS: &FieldSpec = &super::REGISTERS[28].fields[4];
    /// `WP`, bit 9.
    pub const WP: &FieldSpec = &super::REGISTERS[28].fields[5];
    /// `CLK`, bits 10..=11.
    pub const CLK: &FieldSpec = &super::REGISTERS[28].fields[6];
}

/// The fields of `SDTR1`.
pub mod sdtr1 {
    use super::FieldSpec;
    /// `TMRD`, bits 0..=3.
    pub const TMRD: &FieldSpec = &super::REGISTERS[29].fields[0];
    /// `TXSR`, bits 4..=7.
    pub const TXSR: &FieldSpec = &super::REGISTERS[29].fields[1];
    /// `TRAS`, bits 8..=11.
    pub const TRAS: &FieldSpec = &super::REGISTERS[29].fields[2];
    /// `TRC`, bits 12..=15.
    pub const TRC: &FieldSpec = &super::REGISTERS[29].fields[3];
    /// `TWR`, bits 16..=19.
    pub const TWR: &FieldSpec = &super::REGISTERS[29].fields[4];
    /// `TRP`, bits 20..=23.
    pub const TRP: &FieldSpec = &super::REGISTERS[29].fields[5];
    /// `TRCD`, bits 24..=27.
    pub const TRCD: &FieldSpec = &super::REGISTERS[29].fields[6];
}

/// The fields of `SDTR2`.
pub mod sdtr2 {
    use super::FieldSpec;
    /// `TMRD`, bits 0..=3.
    pub const TMRD: &FieldSpec = &super::REGISTERS[30].fields[0];
    /// `TXSR`, bits 4..=7.
    pub const TXSR: &FieldSpec = &super::REGISTERS[30].fields[1];
    /// `TRAS`, bits 8..=11.
    pub const TRAS: &FieldSpec = &super::REGISTERS[30].fields[2];
    /// `TRC`, bits 12..=15.
    pub const TRC: &FieldSpec = &super::REGISTERS[30].fields[3];
    /// `TWR`, bits 16..=19.
    pub const TWR: &FieldSpec = &super::REGISTERS[30].fields[4];
    /// `TRP`, bits 20..=23.
    pub const TRP: &FieldSpec = &super::REGISTERS[30].fields[5];
    /// `TRCD`, bits 24..=27.
    pub const TRCD: &FieldSpec = &super::REGISTERS[30].fields[6];
}

/// The fields of `SDCMR`.
pub mod sdcmr {
    use super::FieldSpec;
    /// `MODE`, bits 0..=2, write-only.
    pub const MODE: &FieldSpec = &super::REGISTERS[31].fields[0];
    /// `CTB2`, bit 3, write-only.
    pub const CTB2: &FieldSpec = &super::REGISTERS[31].fields[1];
    /// `CTB1`, bit 4, write-only.
    pub const CTB1: &FieldSpec = &super::REGISTERS[31].fields[2];
    /// `NRFS`, bits 5..=8.
    pub const NRFS: &FieldSpec = &super::REGISTERS[31].fields[3];
    /// `MRD`, bits 9..=21.
    pub const MRD: &FieldSpec = &super::REGISTERS[31].fields[4];
}

/// The fields of `SDRTR`.
pub mod sdrtr {
    use super::FieldSpec;
    /// `CRE`, bit 0, write-only.
    pub const CRE: &FieldSpec = &super::REGISTERS[32].fields[0];
    /// `COUNT`, bits 1..=13.
    pub const COUNT: &FieldSpec = &super::REGISTERS[32].fields[1];
    /// `REIE`, bit 14.
    pub const REIE: &FieldSpec = &super::REGISTERS[32].fields[2];
}

/// The fields of `SDSR`.
pub mod sdsr {
    use super::FieldSpec;
    /// `RE`, bit 0.
    pub const RE: &FieldSpec = &super::REGISTERS[33].fields[0];
    /// `MODES1`, bits 1..=2.
    pub const MODES1: &FieldSpec = &super::REGISTERS[33].fields[1];
    /// `MODES2`, bits 3..=4.
    pub const MODES2: &FieldSpec = &super::REGISTERS[33].fields[2];
    /// `BUSY`, bit 5.
    pub const BUSY: &FieldSpec = &super::REGISTERS[33].fields[3];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 34] = [
    RegisterSpec { name: "BCR1", offset: 0x0, width: Width::W32, reset: 0x0000_30D0, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MBKEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUXEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MTYP", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MWID", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FACCEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BURSTEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITPOL", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WRAPMOD", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITCFG", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WREN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITEN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTMOD", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ASYNCWAIT", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPSIZE", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CBURSTRW", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCLKEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BTR1", offset: 0x4, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDSET", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDHLD", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAST", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSTURN", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLKDIV", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATLAT", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACCMOD", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BCR2", offset: 0x8, width: Width::W32, reset: 0x0000_30D0, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MBKEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUXEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MTYP", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MWID", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FACCEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BURSTEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITPOL", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WRAPMOD", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITCFG", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WREN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITEN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTMOD", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ASYNCWAIT", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPSIZE", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CBURSTRW", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BTR2", offset: 0xC, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDSET", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDHLD", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAST", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSTURN", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLKDIV", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATLAT", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACCMOD", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BCR3", offset: 0x10, width: Width::W32, reset: 0x0000_30D0, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MBKEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUXEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MTYP", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MWID", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FACCEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BURSTEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITPOL", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WRAPMOD", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITCFG", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WREN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITEN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTMOD", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ASYNCWAIT", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPSIZE", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CBURSTRW", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BTR3", offset: 0x14, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDSET", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDHLD", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAST", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSTURN", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLKDIV", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATLAT", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACCMOD", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BCR4", offset: 0x18, width: Width::W32, reset: 0x0000_30D0, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MBKEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUXEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MTYP", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MWID", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FACCEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BURSTEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITPOL", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WRAPMOD", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITCFG", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WREN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAITEN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTMOD", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ASYNCWAIT", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPSIZE", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CBURSTRW", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BTR4", offset: 0x1C, width: Width::W32, reset: 0xFFFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDSET", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDHLD", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAST", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSTURN", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLKDIV", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATLAT", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACCMOD", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PCR2", offset: 0x60, width: Width::W32, reset: 0x0000_0018, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PWAITEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBKEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PTYP", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWID", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCLR", bit: 9, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TAR", bit: 13, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCPS", bit: 17, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR2", offset: 0x64, width: Width::W32, reset: 0x0000_0040, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IRS", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ILS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IREN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ILEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEMPT", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PMEM2", offset: 0x68, width: Width::W32, reset: 0xFCFC_FCFC, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MEMSETx", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEMWAITx", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEMHOLDx", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEMHIZx", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PATT2", offset: 0x6C, width: Width::W32, reset: 0xFCFC_FCFC, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ATTSETx", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATTWAITx", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATTHOLDx", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATTHIZx", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ECCR2", offset: 0x74, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ECCx", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PCR3", offset: 0x80, width: Width::W32, reset: 0x0000_0018, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PWAITEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBKEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PTYP", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWID", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCLR", bit: 9, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TAR", bit: 13, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCPS", bit: 17, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR3", offset: 0x84, width: Width::W32, reset: 0x0000_0040, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IRS", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ILS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IREN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ILEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEMPT", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PMEM3", offset: 0x88, width: Width::W32, reset: 0xFCFC_FCFC, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MEMSETx", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEMWAITx", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEMHOLDx", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEMHIZx", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PATT3", offset: 0x8C, width: Width::W32, reset: 0xFCFC_FCFC, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ATTSETx", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATTWAITx", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATTHOLDx", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATTHIZx", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ECCR3", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ECCx", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PCR4", offset: 0xA0, width: Width::W32, reset: 0x0000_0018, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PWAITEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PBKEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PTYP", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PWID", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCLR", bit: 9, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TAR", bit: 13, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCPS", bit: 17, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR4", offset: 0xA4, width: Width::W32, reset: 0x0000_0040, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IRS", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ILS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IREN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ILEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEMPT", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PMEM4", offset: 0xA8, width: Width::W32, reset: 0xFCFC_FCFC, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MEMSETx", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEMWAITx", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEMHOLDx", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MEMHIZx", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PATT4", offset: 0xAC, width: Width::W32, reset: 0xFCFC_FCFC, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ATTSETx", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATTWAITx", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATTHOLDx", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ATTHIZx", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PIO4", offset: 0xB0, width: Width::W32, reset: 0xFCFC_FCFC, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IOSETx", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IOWAITx", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IOHOLDx", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IOHIZx", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BWTR1", offset: 0x104, width: Width::W32, reset: 0x0FFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDSET", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDHLD", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAST", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSTURN", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACCMOD", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BWTR3", offset: 0x104, width: Width::W32, reset: 0x0FFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDSET", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDHLD", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAST", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSTURN", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACCMOD", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BWTR2", offset: 0x10C, width: Width::W32, reset: 0x0FFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDSET", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDHLD", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAST", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSTURN", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACCMOD", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BWTR4", offset: 0x10C, width: Width::W32, reset: 0x0FFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDSET", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDHLD", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAST", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSTURN", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACCMOD", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SDCR1", offset: 0x140, width: Width::W32, reset: 0x0000_02D0, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NR", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MWID", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NB", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAS", bit: 7, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WP", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SDCLK", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBURST", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RPIPE", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SDCR2", offset: 0x144, width: Width::W32, reset: 0x0000_02D0, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NR", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MWID", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NB", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAS", bit: 7, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WP", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLK", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SDTR1", offset: 0x148, width: Width::W32, reset: 0x0FFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TMRD", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXSR", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRAS", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRC", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TWR", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRP", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRCD", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SDTR2", offset: 0x14C, width: Width::W32, reset: 0x0FFF_FFFF, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TMRD", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXSR", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRAS", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRC", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TWR", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRP", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRCD", bit: 24, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SDCMR", offset: 0x150, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MODE", bit: 0, width: 3, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTB2", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTB1", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NRFS", bit: 5, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MRD", bit: 9, width: 13, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SDRTR", offset: 0x154, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CRE", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COUNT", bit: 1, width: 13, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REIE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SDSR", offset: 0x158, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RE", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODES1", bit: 1, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODES2", bit: 3, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSY", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];