rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32F427.svd, sha256 5eb6bfd30833147f0cb93b74235b602f835fddd78d3795f67a5873804e80d414. Do not edit.
// Copyright (c) 2024 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `SYSCFG` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `MEMRM` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Memrm = 0,
    /// `PMC` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Pmc = 1,
    /// `EXTICR1` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Exticr1 = 2,
    /// `EXTICR2` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Exticr2 = 3,
    /// `EXTICR3` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Exticr3 = 4,
    /// `EXTICR4` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Exticr4 = 5,
    /// `CMPCR` at offset `0x20`, resets to `0x0000_0000`, read-only.
    Cmpcr = 6,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 7] = [Self::Memrm, Self::Pmc, Self::Exticr1, Self::Exticr2, Self::Exticr3, Self::Exticr4, Self::Cmpcr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `MEMRM`.
pub mod memrm {
    use super::FieldSpec;
    /// `MEM_MODE`, bits 0..=2.
    pub const MEM_MODE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `FB_MODE`, bit 8.
    pub const FB_MODE: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `SWP_FMC`, bits 10..=11.
    pub const SWP_FMC: &FieldSpec = &super::REGISTERS[0].fields[2];
}

/// The fields of `PMC`.
pub mod pmc {
    use super::FieldSpec;
    /// `ADC1DC2`, bit 16.
    pub const ADC1DC2: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `ADC2DC2`, bit 17.
    pub const ADC2DC2: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `ADC3DC2`, bit 18.
    pub const ADC3DC2: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `MII_RMII_SEL`, bit 23.
    pub const MII_RMII_SEL: &FieldSpec = &super::REGISTERS[1].fields[3];
}

/// The fields of `EXTICR1`.
pub mod exticr1 {
    use super::FieldSpec;
    /// `EXTI0`, bits 0..=3.
    pub const EXTI0: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `EXTI1`, bits 4..=7.
    pub const EXTI1: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `EXTI2`, bits 8..=11.
    pub const EXTI2: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `EXTI3`, bits 12..=15.
    pub const EXTI3: &FieldSpec = &super::REGISTERS[2].fields[3];
}

/// The fields of `EXTICR2`.
pub mod exticr2 {
    use super::FieldSpec;
    /// `EXTI4`, bits 0..=3.
    pub const EXTI4: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `EXTI5`, bits 4..=7.
    pub const EXTI5: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `EXTI6`, bits 8..=11.
    pub const EXTI6: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `EXTI7`, bits 12..=15.
    pub const EXTI7: &FieldSpec = &super::REGISTERS[3].fields[3];
}

/// The fields of `EXTICR3`.
pub mod exticr3 {
    use super::FieldSpec;
    /// `EXTI8`, bits 0..=3.
    pub const EXTI8: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `EXTI9`, bits 4..=7.
    pub const EXTI9: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `EXTI10`, bits 8..=11.
    pub const EXTI10: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `EXTI11`, bits 12..=15.
    pub const EXTI11: &FieldSpec = &super::REGISTERS[4].fields[3];
}

/// The fields of `EXTICR4`.
pub mod exticr4 {
    use super::FieldSpec;
    /// `EXTI12`, bits 0..=3.
    pub const EXTI12: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `EXTI13`, bits 4..=7.
    pub const EXTI13: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `EXTI14`, bits 8..=11.
    pub const EXTI14: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `EXTI15`, bits 12..=15.
    pub const EXTI15: &FieldSpec = &super::REGISTERS[5].fields[3];
}

/// The fields of `CMPCR`.
pub mod cmpcr {
    use super::FieldSpec;
    /// `CMP_PD`, bit 0.
    pub const CMP_PD: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `READY`, bit 8.
    pub const READY: &FieldSpec = &super::REGISTERS[6].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 7] = [
    RegisterSpec { name: "MEMRM", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MEM_MODE", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FB_MODE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWP_FMC", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PMC", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADC1DC2", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADC2DC2", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADC3DC2", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MII_RMII_SEL", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EXTICR1", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXTI0", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI1", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI2", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI3", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EXTICR2", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXTI4", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI5", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI6", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI7", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EXTICR3", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXTI8", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI9", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI10", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI11", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EXTICR4", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXTI12", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI13", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI14", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI15", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CMPCR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CMP_PD", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "READY", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];