esp32/spi0/
slave.rs

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1#[doc = "Register `SLAVE` reader"]
2pub type R = crate::R<SLAVE_SPEC>;
3#[doc = "Register `SLAVE` writer"]
4pub type W = crate::W<SLAVE_SPEC>;
5#[doc = "Field `SLV_RD_BUF_DONE` reader - The interrupt raw bit for the completion of read-buffer operation in the slave mode."]
6pub type SLV_RD_BUF_DONE_R = crate::BitReader;
7#[doc = "Field `SLV_RD_BUF_DONE` writer - The interrupt raw bit for the completion of read-buffer operation in the slave mode."]
8pub type SLV_RD_BUF_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SLV_WR_BUF_DONE` reader - The interrupt raw bit for the completion of write-buffer operation in the slave mode."]
10pub type SLV_WR_BUF_DONE_R = crate::BitReader;
11#[doc = "Field `SLV_WR_BUF_DONE` writer - The interrupt raw bit for the completion of write-buffer operation in the slave mode."]
12pub type SLV_WR_BUF_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SLV_RD_STA_DONE` reader - The interrupt raw bit for the completion of read-status operation in the slave mode."]
14pub type SLV_RD_STA_DONE_R = crate::BitReader;
15#[doc = "Field `SLV_RD_STA_DONE` writer - The interrupt raw bit for the completion of read-status operation in the slave mode."]
16pub type SLV_RD_STA_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SLV_WR_STA_DONE` reader - The interrupt raw bit for the completion of write-status operation in the slave mode."]
18pub type SLV_WR_STA_DONE_R = crate::BitReader;
19#[doc = "Field `SLV_WR_STA_DONE` writer - The interrupt raw bit for the completion of write-status operation in the slave mode."]
20pub type SLV_WR_STA_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TRANS_DONE` reader - The interrupt raw bit for the completion of any operation in both the master mode and the slave mode."]
22pub type TRANS_DONE_R = crate::BitReader;
23#[doc = "Field `TRANS_DONE` writer - The interrupt raw bit for the completion of any operation in both the master mode and the slave mode."]
24pub type TRANS_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SLV_RD_BUF_INTEN` reader - The interrupt enable bit for the SPI_SLV_RD_BUF_INT interrupt."]
26pub type SLV_RD_BUF_INTEN_R = crate::BitReader;
27#[doc = "Field `SLV_RD_BUF_INTEN` writer - The interrupt enable bit for the SPI_SLV_RD_BUF_INT interrupt."]
28pub type SLV_RD_BUF_INTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SLV_WR_BUF_INTEN` reader - The interrupt enable bit for the SPI_SLV_WR_BUF_INT interrupt."]
30pub type SLV_WR_BUF_INTEN_R = crate::BitReader;
31#[doc = "Field `SLV_WR_BUF_INTEN` writer - The interrupt enable bit for the SPI_SLV_WR_BUF_INT interrupt."]
32pub type SLV_WR_BUF_INTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SLV_RD_STA_INTEN` reader - The interrupt enable bit for the SPI_SLV_RD_STA_INT interrupt."]
34pub type SLV_RD_STA_INTEN_R = crate::BitReader;
35#[doc = "Field `SLV_RD_STA_INTEN` writer - The interrupt enable bit for the SPI_SLV_RD_STA_INT interrupt."]
36pub type SLV_RD_STA_INTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SLV_WR_STA_INTEN` reader - The interrupt enable bit for the SPI_SLV_WR_STA_INT interrupt."]
38pub type SLV_WR_STA_INTEN_R = crate::BitReader;
39#[doc = "Field `SLV_WR_STA_INTEN` writer - The interrupt enable bit for the SPI_SLV_WR_STA_INT interrupt."]
40pub type SLV_WR_STA_INTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `TRANS_INTEN` reader - The interrupt enable bit for the SPI_TRANS_DONE_INT interrupt."]
42pub type TRANS_INTEN_R = crate::BitReader;
43#[doc = "Field `TRANS_INTEN` writer - The interrupt enable bit for the SPI_TRANS_DONE_INT interrupt."]
44pub type TRANS_INTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CS_I_MODE` reader - In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter."]
46pub type CS_I_MODE_R = crate::FieldReader;
47#[doc = "Field `CS_I_MODE` writer - In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter."]
48pub type CS_I_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
49#[doc = "Field `SLV_LAST_COMMAND` reader - In the slave mode it is the value of command."]
50pub type SLV_LAST_COMMAND_R = crate::FieldReader;
51#[doc = "Field `SLV_LAST_STATE` reader - In the slave mode it is the state of spi state machine."]
52pub type SLV_LAST_STATE_R = crate::FieldReader;
53#[doc = "Field `TRANS_CNT` reader - The operations counter in both the master mode and the slave mode. 4: read-status"]
54pub type TRANS_CNT_R = crate::FieldReader;
55#[doc = "Field `SLV_CMD_DEFINE` reader - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer."]
56pub type SLV_CMD_DEFINE_R = crate::BitReader;
57#[doc = "Field `SLV_CMD_DEFINE` writer - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer."]
58pub type SLV_CMD_DEFINE_W<'a, REG> = crate::BitWriter<'a, REG>;
59#[doc = "Field `SLV_WR_RD_STA_EN` reader - write and read status enable in the slave mode"]
60pub type SLV_WR_RD_STA_EN_R = crate::BitReader;
61#[doc = "Field `SLV_WR_RD_STA_EN` writer - write and read status enable in the slave mode"]
62pub type SLV_WR_RD_STA_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
63#[doc = "Field `SLV_WR_RD_BUF_EN` reader - write and read buffer enable in the slave mode"]
64pub type SLV_WR_RD_BUF_EN_R = crate::BitReader;
65#[doc = "Field `SLV_WR_RD_BUF_EN` writer - write and read buffer enable in the slave mode"]
66pub type SLV_WR_RD_BUF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
67#[doc = "Field `MODE` reader - 1: slave mode 0: master mode."]
68pub type MODE_R = crate::BitReader;
69#[doc = "Field `MODE` writer - 1: slave mode 0: master mode."]
70pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
71#[doc = "Field `SYNC_RESET` reader - Software reset enable, reset the spi clock line cs line and data lines."]
72pub type SYNC_RESET_R = crate::BitReader;
73#[doc = "Field `SYNC_RESET` writer - Software reset enable, reset the spi clock line cs line and data lines."]
74pub type SYNC_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
75impl R {
76    #[doc = "Bit 0 - The interrupt raw bit for the completion of read-buffer operation in the slave mode."]
77    #[inline(always)]
78    pub fn slv_rd_buf_done(&self) -> SLV_RD_BUF_DONE_R {
79        SLV_RD_BUF_DONE_R::new((self.bits & 1) != 0)
80    }
81    #[doc = "Bit 1 - The interrupt raw bit for the completion of write-buffer operation in the slave mode."]
82    #[inline(always)]
83    pub fn slv_wr_buf_done(&self) -> SLV_WR_BUF_DONE_R {
84        SLV_WR_BUF_DONE_R::new(((self.bits >> 1) & 1) != 0)
85    }
86    #[doc = "Bit 2 - The interrupt raw bit for the completion of read-status operation in the slave mode."]
87    #[inline(always)]
88    pub fn slv_rd_sta_done(&self) -> SLV_RD_STA_DONE_R {
89        SLV_RD_STA_DONE_R::new(((self.bits >> 2) & 1) != 0)
90    }
91    #[doc = "Bit 3 - The interrupt raw bit for the completion of write-status operation in the slave mode."]
92    #[inline(always)]
93    pub fn slv_wr_sta_done(&self) -> SLV_WR_STA_DONE_R {
94        SLV_WR_STA_DONE_R::new(((self.bits >> 3) & 1) != 0)
95    }
96    #[doc = "Bit 4 - The interrupt raw bit for the completion of any operation in both the master mode and the slave mode."]
97    #[inline(always)]
98    pub fn trans_done(&self) -> TRANS_DONE_R {
99        TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0)
100    }
101    #[doc = "Bit 5 - The interrupt enable bit for the SPI_SLV_RD_BUF_INT interrupt."]
102    #[inline(always)]
103    pub fn slv_rd_buf_inten(&self) -> SLV_RD_BUF_INTEN_R {
104        SLV_RD_BUF_INTEN_R::new(((self.bits >> 5) & 1) != 0)
105    }
106    #[doc = "Bit 6 - The interrupt enable bit for the SPI_SLV_WR_BUF_INT interrupt."]
107    #[inline(always)]
108    pub fn slv_wr_buf_inten(&self) -> SLV_WR_BUF_INTEN_R {
109        SLV_WR_BUF_INTEN_R::new(((self.bits >> 6) & 1) != 0)
110    }
111    #[doc = "Bit 7 - The interrupt enable bit for the SPI_SLV_RD_STA_INT interrupt."]
112    #[inline(always)]
113    pub fn slv_rd_sta_inten(&self) -> SLV_RD_STA_INTEN_R {
114        SLV_RD_STA_INTEN_R::new(((self.bits >> 7) & 1) != 0)
115    }
116    #[doc = "Bit 8 - The interrupt enable bit for the SPI_SLV_WR_STA_INT interrupt."]
117    #[inline(always)]
118    pub fn slv_wr_sta_inten(&self) -> SLV_WR_STA_INTEN_R {
119        SLV_WR_STA_INTEN_R::new(((self.bits >> 8) & 1) != 0)
120    }
121    #[doc = "Bit 9 - The interrupt enable bit for the SPI_TRANS_DONE_INT interrupt."]
122    #[inline(always)]
123    pub fn trans_inten(&self) -> TRANS_INTEN_R {
124        TRANS_INTEN_R::new(((self.bits >> 9) & 1) != 0)
125    }
126    #[doc = "Bits 10:11 - In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter."]
127    #[inline(always)]
128    pub fn cs_i_mode(&self) -> CS_I_MODE_R {
129        CS_I_MODE_R::new(((self.bits >> 10) & 3) as u8)
130    }
131    #[doc = "Bits 17:19 - In the slave mode it is the value of command."]
132    #[inline(always)]
133    pub fn slv_last_command(&self) -> SLV_LAST_COMMAND_R {
134        SLV_LAST_COMMAND_R::new(((self.bits >> 17) & 7) as u8)
135    }
136    #[doc = "Bits 20:22 - In the slave mode it is the state of spi state machine."]
137    #[inline(always)]
138    pub fn slv_last_state(&self) -> SLV_LAST_STATE_R {
139        SLV_LAST_STATE_R::new(((self.bits >> 20) & 7) as u8)
140    }
141    #[doc = "Bits 23:26 - The operations counter in both the master mode and the slave mode. 4: read-status"]
142    #[inline(always)]
143    pub fn trans_cnt(&self) -> TRANS_CNT_R {
144        TRANS_CNT_R::new(((self.bits >> 23) & 0x0f) as u8)
145    }
146    #[doc = "Bit 27 - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer."]
147    #[inline(always)]
148    pub fn slv_cmd_define(&self) -> SLV_CMD_DEFINE_R {
149        SLV_CMD_DEFINE_R::new(((self.bits >> 27) & 1) != 0)
150    }
151    #[doc = "Bit 28 - write and read status enable in the slave mode"]
152    #[inline(always)]
153    pub fn slv_wr_rd_sta_en(&self) -> SLV_WR_RD_STA_EN_R {
154        SLV_WR_RD_STA_EN_R::new(((self.bits >> 28) & 1) != 0)
155    }
156    #[doc = "Bit 29 - write and read buffer enable in the slave mode"]
157    #[inline(always)]
158    pub fn slv_wr_rd_buf_en(&self) -> SLV_WR_RD_BUF_EN_R {
159        SLV_WR_RD_BUF_EN_R::new(((self.bits >> 29) & 1) != 0)
160    }
161    #[doc = "Bit 30 - 1: slave mode 0: master mode."]
162    #[inline(always)]
163    pub fn mode(&self) -> MODE_R {
164        MODE_R::new(((self.bits >> 30) & 1) != 0)
165    }
166    #[doc = "Bit 31 - Software reset enable, reset the spi clock line cs line and data lines."]
167    #[inline(always)]
168    pub fn sync_reset(&self) -> SYNC_RESET_R {
169        SYNC_RESET_R::new(((self.bits >> 31) & 1) != 0)
170    }
171}
172#[cfg(feature = "impl-register-debug")]
173impl core::fmt::Debug for R {
174    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
175        f.debug_struct("SLAVE")
176            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
177            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
178            .field("slv_rd_sta_done", &self.slv_rd_sta_done())
179            .field("slv_wr_sta_done", &self.slv_wr_sta_done())
180            .field("trans_done", &self.trans_done())
181            .field("cs_i_mode", &self.cs_i_mode())
182            .field("slv_last_command", &self.slv_last_command())
183            .field("slv_last_state", &self.slv_last_state())
184            .field("trans_cnt", &self.trans_cnt())
185            .field("slv_cmd_define", &self.slv_cmd_define())
186            .field("slv_wr_rd_sta_en", &self.slv_wr_rd_sta_en())
187            .field("slv_wr_rd_buf_en", &self.slv_wr_rd_buf_en())
188            .field("mode", &self.mode())
189            .field("sync_reset", &self.sync_reset())
190            .field("trans_inten", &self.trans_inten())
191            .field("slv_wr_sta_inten", &self.slv_wr_sta_inten())
192            .field("slv_rd_sta_inten", &self.slv_rd_sta_inten())
193            .field("slv_wr_buf_inten", &self.slv_wr_buf_inten())
194            .field("slv_rd_buf_inten", &self.slv_rd_buf_inten())
195            .finish()
196    }
197}
198impl W {
199    #[doc = "Bit 0 - The interrupt raw bit for the completion of read-buffer operation in the slave mode."]
200    #[inline(always)]
201    pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W<SLAVE_SPEC> {
202        SLV_RD_BUF_DONE_W::new(self, 0)
203    }
204    #[doc = "Bit 1 - The interrupt raw bit for the completion of write-buffer operation in the slave mode."]
205    #[inline(always)]
206    pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W<SLAVE_SPEC> {
207        SLV_WR_BUF_DONE_W::new(self, 1)
208    }
209    #[doc = "Bit 2 - The interrupt raw bit for the completion of read-status operation in the slave mode."]
210    #[inline(always)]
211    pub fn slv_rd_sta_done(&mut self) -> SLV_RD_STA_DONE_W<SLAVE_SPEC> {
212        SLV_RD_STA_DONE_W::new(self, 2)
213    }
214    #[doc = "Bit 3 - The interrupt raw bit for the completion of write-status operation in the slave mode."]
215    #[inline(always)]
216    pub fn slv_wr_sta_done(&mut self) -> SLV_WR_STA_DONE_W<SLAVE_SPEC> {
217        SLV_WR_STA_DONE_W::new(self, 3)
218    }
219    #[doc = "Bit 4 - The interrupt raw bit for the completion of any operation in both the master mode and the slave mode."]
220    #[inline(always)]
221    pub fn trans_done(&mut self) -> TRANS_DONE_W<SLAVE_SPEC> {
222        TRANS_DONE_W::new(self, 4)
223    }
224    #[doc = "Bit 5 - The interrupt enable bit for the SPI_SLV_RD_BUF_INT interrupt."]
225    #[inline(always)]
226    pub fn slv_rd_buf_inten(&mut self) -> SLV_RD_BUF_INTEN_W<SLAVE_SPEC> {
227        SLV_RD_BUF_INTEN_W::new(self, 5)
228    }
229    #[doc = "Bit 6 - The interrupt enable bit for the SPI_SLV_WR_BUF_INT interrupt."]
230    #[inline(always)]
231    pub fn slv_wr_buf_inten(&mut self) -> SLV_WR_BUF_INTEN_W<SLAVE_SPEC> {
232        SLV_WR_BUF_INTEN_W::new(self, 6)
233    }
234    #[doc = "Bit 7 - The interrupt enable bit for the SPI_SLV_RD_STA_INT interrupt."]
235    #[inline(always)]
236    pub fn slv_rd_sta_inten(&mut self) -> SLV_RD_STA_INTEN_W<SLAVE_SPEC> {
237        SLV_RD_STA_INTEN_W::new(self, 7)
238    }
239    #[doc = "Bit 8 - The interrupt enable bit for the SPI_SLV_WR_STA_INT interrupt."]
240    #[inline(always)]
241    pub fn slv_wr_sta_inten(&mut self) -> SLV_WR_STA_INTEN_W<SLAVE_SPEC> {
242        SLV_WR_STA_INTEN_W::new(self, 8)
243    }
244    #[doc = "Bit 9 - The interrupt enable bit for the SPI_TRANS_DONE_INT interrupt."]
245    #[inline(always)]
246    pub fn trans_inten(&mut self) -> TRANS_INTEN_W<SLAVE_SPEC> {
247        TRANS_INTEN_W::new(self, 9)
248    }
249    #[doc = "Bits 10:11 - In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter."]
250    #[inline(always)]
251    pub fn cs_i_mode(&mut self) -> CS_I_MODE_W<SLAVE_SPEC> {
252        CS_I_MODE_W::new(self, 10)
253    }
254    #[doc = "Bit 27 - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer."]
255    #[inline(always)]
256    pub fn slv_cmd_define(&mut self) -> SLV_CMD_DEFINE_W<SLAVE_SPEC> {
257        SLV_CMD_DEFINE_W::new(self, 27)
258    }
259    #[doc = "Bit 28 - write and read status enable in the slave mode"]
260    #[inline(always)]
261    pub fn slv_wr_rd_sta_en(&mut self) -> SLV_WR_RD_STA_EN_W<SLAVE_SPEC> {
262        SLV_WR_RD_STA_EN_W::new(self, 28)
263    }
264    #[doc = "Bit 29 - write and read buffer enable in the slave mode"]
265    #[inline(always)]
266    pub fn slv_wr_rd_buf_en(&mut self) -> SLV_WR_RD_BUF_EN_W<SLAVE_SPEC> {
267        SLV_WR_RD_BUF_EN_W::new(self, 29)
268    }
269    #[doc = "Bit 30 - 1: slave mode 0: master mode."]
270    #[inline(always)]
271    pub fn mode(&mut self) -> MODE_W<SLAVE_SPEC> {
272        MODE_W::new(self, 30)
273    }
274    #[doc = "Bit 31 - Software reset enable, reset the spi clock line cs line and data lines."]
275    #[inline(always)]
276    pub fn sync_reset(&mut self) -> SYNC_RESET_W<SLAVE_SPEC> {
277        SYNC_RESET_W::new(self, 31)
278    }
279}
280#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`slave::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slave::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
281pub struct SLAVE_SPEC;
282impl crate::RegisterSpec for SLAVE_SPEC {
283    type Ux = u32;
284}
285#[doc = "`read()` method returns [`slave::R`](R) reader structure"]
286impl crate::Readable for SLAVE_SPEC {}
287#[doc = "`write(|w| ..)` method takes [`slave::W`](W) writer structure"]
288impl crate::Writable for SLAVE_SPEC {
289    type Safety = crate::Unsafe;
290    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
291    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
292}
293#[doc = "`reset()` method sets SLAVE to value 0x20"]
294impl crate::Resettable for SLAVE_SPEC {
295    const RESET_VALUE: u32 = 0x20;
296}
esp32/spi0/slave.rs

esp32/spi0/
slave.rs
