1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `RXFIFO_FULL` writer - Set this bit to clear the rxfifo_full_int_raw interrupt."]
4pub type RXFIFO_FULL_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `TXFIFO_EMPTY` writer - Set this bit to clear txfifo_empty_int_raw interrupt."]
6pub type TXFIFO_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `PARITY_ERR` writer - Set this bit to clear parity_err_int_raw interrupt."]
8pub type PARITY_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `FRM_ERR` writer - Set this bit to clear frm_err_int_raw interrupt."]
10pub type FRM_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `RXFIFO_OVF` writer - Set this bit to clear rxfifo_ovf_int_raw interrupt."]
12pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `DSR_CHG` writer - Set this bit to clear the dsr_chg_int_raw interrupt."]
14pub type DSR_CHG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `CTS_CHG` writer - Set this bit to clear the cts_chg_int_raw interrupt."]
16pub type CTS_CHG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `BRK_DET` writer - Set this bit to clear the brk_det_int_raw interrupt."]
18pub type BRK_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `RXFIFO_TOUT` writer - Set this bit to clear the rxfifo_tout_int_raw interrupt."]
20pub type RXFIFO_TOUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `SW_XON` writer - Set this bit to clear the sw_xon_int_raw interrupt."]
22pub type SW_XON_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `SW_XOFF` writer - Set this bit to clear the sw_xon_int_raw interrupt."]
24pub type SW_XOFF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `GLITCH_DET` writer - Set this bit to clear the glitch_det_int_raw interrupt."]
26pub type GLITCH_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `TX_BRK_DONE` writer - Set this bit to clear the tx_brk_done_int_raw interrupt.."]
28pub type TX_BRK_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `TX_BRK_IDLE_DONE` writer - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."]
30pub type TX_BRK_IDLE_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `TX_DONE` writer - Set this bit to clear the tx_done_int_raw interrupt."]
32pub type TX_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `RS485_PARITY_ERR` writer - Set this bit to clear the rs485_parity_err_int_raw interrupt."]
34pub type RS485_PARITY_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `RS485_FRM_ERR` writer - Set this bit to clear the rs485_frm_err_int_raw interrupt."]
36pub type RS485_FRM_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `RS485_CLASH` writer - Set this bit to clear the rs485_clash_int_raw interrupt."]
38pub type RS485_CLASH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[doc = "Field `AT_CMD_CHAR_DET` writer - Set this bit to clear the at_cmd_char_det_int_raw interrupt."]
40pub type AT_CMD_CHAR_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[cfg(feature = "impl-register-debug")]
42impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
43 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
44 write!(f, "(not readable)")
45 }
46}
47impl W {
48 #[doc = "Bit 0 - Set this bit to clear the rxfifo_full_int_raw interrupt."]
49 #[inline(always)]
50 pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_CLR_SPEC> {
51 RXFIFO_FULL_W::new(self, 0)
52 }
53 #[doc = "Bit 1 - Set this bit to clear txfifo_empty_int_raw interrupt."]
54 #[inline(always)]
55 pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_CLR_SPEC> {
56 TXFIFO_EMPTY_W::new(self, 1)
57 }
58 #[doc = "Bit 2 - Set this bit to clear parity_err_int_raw interrupt."]
59 #[inline(always)]
60 pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_CLR_SPEC> {
61 PARITY_ERR_W::new(self, 2)
62 }
63 #[doc = "Bit 3 - Set this bit to clear frm_err_int_raw interrupt."]
64 #[inline(always)]
65 pub fn frm_err(&mut self) -> FRM_ERR_W<INT_CLR_SPEC> {
66 FRM_ERR_W::new(self, 3)
67 }
68 #[doc = "Bit 4 - Set this bit to clear rxfifo_ovf_int_raw interrupt."]
69 #[inline(always)]
70 pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
71 RXFIFO_OVF_W::new(self, 4)
72 }
73 #[doc = "Bit 5 - Set this bit to clear the dsr_chg_int_raw interrupt."]
74 #[inline(always)]
75 pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_CLR_SPEC> {
76 DSR_CHG_W::new(self, 5)
77 }
78 #[doc = "Bit 6 - Set this bit to clear the cts_chg_int_raw interrupt."]
79 #[inline(always)]
80 pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_CLR_SPEC> {
81 CTS_CHG_W::new(self, 6)
82 }
83 #[doc = "Bit 7 - Set this bit to clear the brk_det_int_raw interrupt."]
84 #[inline(always)]
85 pub fn brk_det(&mut self) -> BRK_DET_W<INT_CLR_SPEC> {
86 BRK_DET_W::new(self, 7)
87 }
88 #[doc = "Bit 8 - Set this bit to clear the rxfifo_tout_int_raw interrupt."]
89 #[inline(always)]
90 pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_CLR_SPEC> {
91 RXFIFO_TOUT_W::new(self, 8)
92 }
93 #[doc = "Bit 9 - Set this bit to clear the sw_xon_int_raw interrupt."]
94 #[inline(always)]
95 pub fn sw_xon(&mut self) -> SW_XON_W<INT_CLR_SPEC> {
96 SW_XON_W::new(self, 9)
97 }
98 #[doc = "Bit 10 - Set this bit to clear the sw_xon_int_raw interrupt."]
99 #[inline(always)]
100 pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_CLR_SPEC> {
101 SW_XOFF_W::new(self, 10)
102 }
103 #[doc = "Bit 11 - Set this bit to clear the glitch_det_int_raw interrupt."]
104 #[inline(always)]
105 pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_CLR_SPEC> {
106 GLITCH_DET_W::new(self, 11)
107 }
108 #[doc = "Bit 12 - Set this bit to clear the tx_brk_done_int_raw interrupt.."]
109 #[inline(always)]
110 pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_CLR_SPEC> {
111 TX_BRK_DONE_W::new(self, 12)
112 }
113 #[doc = "Bit 13 - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."]
114 #[inline(always)]
115 pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_CLR_SPEC> {
116 TX_BRK_IDLE_DONE_W::new(self, 13)
117 }
118 #[doc = "Bit 14 - Set this bit to clear the tx_done_int_raw interrupt."]
119 #[inline(always)]
120 pub fn tx_done(&mut self) -> TX_DONE_W<INT_CLR_SPEC> {
121 TX_DONE_W::new(self, 14)
122 }
123 #[doc = "Bit 15 - Set this bit to clear the rs485_parity_err_int_raw interrupt."]
124 #[inline(always)]
125 pub fn rs485_parity_err(&mut self) -> RS485_PARITY_ERR_W<INT_CLR_SPEC> {
126 RS485_PARITY_ERR_W::new(self, 15)
127 }
128 #[doc = "Bit 16 - Set this bit to clear the rs485_frm_err_int_raw interrupt."]
129 #[inline(always)]
130 pub fn rs485_frm_err(&mut self) -> RS485_FRM_ERR_W<INT_CLR_SPEC> {
131 RS485_FRM_ERR_W::new(self, 16)
132 }
133 #[doc = "Bit 17 - Set this bit to clear the rs485_clash_int_raw interrupt."]
134 #[inline(always)]
135 pub fn rs485_clash(&mut self) -> RS485_CLASH_W<INT_CLR_SPEC> {
136 RS485_CLASH_W::new(self, 17)
137 }
138 #[doc = "Bit 18 - Set this bit to clear the at_cmd_char_det_int_raw interrupt."]
139 #[inline(always)]
140 pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_CLR_SPEC> {
141 AT_CMD_CHAR_DET_W::new(self, 18)
142 }
143}
144#[doc = "\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
145pub struct INT_CLR_SPEC;
146impl crate::RegisterSpec for INT_CLR_SPEC {
147 type Ux = u32;
148}
149#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
150impl crate::Writable for INT_CLR_SPEC {
151 type Safety = crate::Unsafe;
152 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
153 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0007_ffff;
154}
155#[doc = "`reset()` method sets INT_CLR to value 0"]
156impl crate::Resettable for INT_CLR_SPEC {
157 const RESET_VALUE: u32 = 0;
158}