esp32/gpio/
acpu_int1.rs

1#[doc = "Register `ACPU_INT1` reader"]
2pub type R = crate::R<ACPU_INT1_SPEC>;
3#[doc = "Field `APPCPU_INT_H` reader - GPIO32~39 APP CPU interrupt status"]
4pub type APPCPU_INT_H_R = crate::FieldReader;
5impl R {
6    #[doc = "Bits 0:7 - GPIO32~39 APP CPU interrupt status"]
7    #[inline(always)]
8    pub fn appcpu_int_h(&self) -> APPCPU_INT_H_R {
9        APPCPU_INT_H_R::new((self.bits & 0xff) as u8)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("ACPU_INT1")
16            .field("appcpu_int_h", &self.appcpu_int_h())
17            .finish()
18    }
19}
20#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`acpu_int1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21pub struct ACPU_INT1_SPEC;
22impl crate::RegisterSpec for ACPU_INT1_SPEC {
23    type Ux = u32;
24}
25#[doc = "`read()` method returns [`acpu_int1::R`](R) reader structure"]
26impl crate::Readable for ACPU_INT1_SPEC {}
27#[doc = "`reset()` method sets ACPU_INT1 to value 0"]
28impl crate::Resettable for ACPU_INT1_SPEC {
29    const RESET_VALUE: u32 = 0;
30}
esp32/gpio/acpu_int1.rs

esp32/gpio/
acpu_int1.rs
