1#[doc = "Register `USER` reader"]
2pub type R = crate::R<USER_SPEC>;
3#[doc = "Register `USER` writer"]
4pub type W = crate::W<USER_SPEC>;
5#[doc = "Field `DOUTDIN` reader - Set the bit to enable full duplex communication. 1: enable 0: disable."]
6pub type DOUTDIN_R = crate::BitReader;
7#[doc = "Field `DOUTDIN` writer - Set the bit to enable full duplex communication. 1: enable 0: disable."]
8pub type DOUTDIN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CS_HOLD` reader - spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable."]
10pub type CS_HOLD_R = crate::BitReader;
11#[doc = "Field `CS_HOLD` writer - spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable."]
12pub type CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CS_SETUP` reader - spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable."]
14pub type CS_SETUP_R = crate::BitReader;
15#[doc = "Field `CS_SETUP` writer - spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable."]
16pub type CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CK_I_EDGE` reader - In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits."]
18pub type CK_I_EDGE_R = crate::BitReader;
19#[doc = "Field `CK_I_EDGE` writer - In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits."]
20pub type CK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CK_OUT_EDGE` reader - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode."]
22pub type CK_OUT_EDGE_R = crate::BitReader;
23#[doc = "Field `CK_OUT_EDGE` writer - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode."]
24pub type CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RD_BYTE_ORDER` reader - In read-data (MISO) phase 1: big-endian 0: little_endian"]
26pub type RD_BYTE_ORDER_R = crate::BitReader;
27#[doc = "Field `RD_BYTE_ORDER` writer - In read-data (MISO) phase 1: big-endian 0: little_endian"]
28pub type RD_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `WR_BYTE_ORDER` reader - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian"]
30pub type WR_BYTE_ORDER_R = crate::BitReader;
31#[doc = "Field `WR_BYTE_ORDER` writer - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian"]
32pub type WR_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FWRITE_DUAL` reader - In the write operations read-data phase apply 2 signals"]
34pub type FWRITE_DUAL_R = crate::BitReader;
35#[doc = "Field `FWRITE_DUAL` writer - In the write operations read-data phase apply 2 signals"]
36pub type FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FWRITE_QUAD` reader - In the write operations read-data phase apply 4 signals"]
38pub type FWRITE_QUAD_R = crate::BitReader;
39#[doc = "Field `FWRITE_QUAD` writer - In the write operations read-data phase apply 4 signals"]
40pub type FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FWRITE_DIO` reader - In the write operations address phase and read-data phase apply 2 signals."]
42pub type FWRITE_DIO_R = crate::BitReader;
43#[doc = "Field `FWRITE_DIO` writer - In the write operations address phase and read-data phase apply 2 signals."]
44pub type FWRITE_DIO_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FWRITE_QIO` reader - In the write operations address phase and read-data phase apply 4 signals."]
46pub type FWRITE_QIO_R = crate::BitReader;
47#[doc = "Field `FWRITE_QIO` writer - In the write operations address phase and read-data phase apply 4 signals."]
48pub type FWRITE_QIO_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SIO` reader - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable."]
50pub type SIO_R = crate::BitReader;
51#[doc = "Field `SIO` writer - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable."]
52pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `USR_HOLD_POL` reader - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low"]
54pub type USR_HOLD_POL_R = crate::BitReader;
55#[doc = "Field `USR_HOLD_POL` writer - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low"]
56pub type USR_HOLD_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `USR_DOUT_HOLD` reader - spi is hold at data out state the bit combined with spi_usr_hold_pol bit."]
58pub type USR_DOUT_HOLD_R = crate::BitReader;
59#[doc = "Field `USR_DOUT_HOLD` writer - spi is hold at data out state the bit combined with spi_usr_hold_pol bit."]
60pub type USR_DOUT_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `USR_DIN_HOLD` reader - spi is hold at data in state the bit combined with spi_usr_hold_pol bit."]
62pub type USR_DIN_HOLD_R = crate::BitReader;
63#[doc = "Field `USR_DIN_HOLD` writer - spi is hold at data in state the bit combined with spi_usr_hold_pol bit."]
64pub type USR_DIN_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `USR_DUMMY_HOLD` reader - spi is hold at dummy state the bit combined with spi_usr_hold_pol bit."]
66pub type USR_DUMMY_HOLD_R = crate::BitReader;
67#[doc = "Field `USR_DUMMY_HOLD` writer - spi is hold at dummy state the bit combined with spi_usr_hold_pol bit."]
68pub type USR_DUMMY_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `USR_ADDR_HOLD` reader - spi is hold at address state the bit combined with spi_usr_hold_pol bit."]
70pub type USR_ADDR_HOLD_R = crate::BitReader;
71#[doc = "Field `USR_ADDR_HOLD` writer - spi is hold at address state the bit combined with spi_usr_hold_pol bit."]
72pub type USR_ADDR_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `USR_CMD_HOLD` reader - spi is hold at command state the bit combined with spi_usr_hold_pol bit."]
74pub type USR_CMD_HOLD_R = crate::BitReader;
75#[doc = "Field `USR_CMD_HOLD` writer - spi is hold at command state the bit combined with spi_usr_hold_pol bit."]
76pub type USR_CMD_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `USR_PREP_HOLD` reader - spi is hold at prepare state the bit combined with spi_usr_hold_pol bit."]
78pub type USR_PREP_HOLD_R = crate::BitReader;
79#[doc = "Field `USR_PREP_HOLD` writer - spi is hold at prepare state the bit combined with spi_usr_hold_pol bit."]
80pub type USR_PREP_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `USR_MISO_HIGHPART` reader - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable."]
82pub type USR_MISO_HIGHPART_R = crate::BitReader;
83#[doc = "Field `USR_MISO_HIGHPART` writer - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable."]
84pub type USR_MISO_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `USR_MOSI_HIGHPART` reader - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable."]
86pub type USR_MOSI_HIGHPART_R = crate::BitReader;
87#[doc = "Field `USR_MOSI_HIGHPART` writer - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable."]
88pub type USR_MOSI_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `USR_DUMMY_IDLE` reader - spi clock is disable in dummy phase when the bit is enable."]
90pub type USR_DUMMY_IDLE_R = crate::BitReader;
91#[doc = "Field `USR_DUMMY_IDLE` writer - spi clock is disable in dummy phase when the bit is enable."]
92pub type USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `USR_MOSI` reader - This bit enable the write-data phase of an operation."]
94pub type USR_MOSI_R = crate::BitReader;
95#[doc = "Field `USR_MOSI` writer - This bit enable the write-data phase of an operation."]
96pub type USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `USR_MISO` reader - This bit enable the read-data phase of an operation."]
98pub type USR_MISO_R = crate::BitReader;
99#[doc = "Field `USR_MISO` writer - This bit enable the read-data phase of an operation."]
100pub type USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `USR_DUMMY` reader - This bit enable the dummy phase of an operation."]
102pub type USR_DUMMY_R = crate::BitReader;
103#[doc = "Field `USR_DUMMY` writer - This bit enable the dummy phase of an operation."]
104pub type USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `USR_ADDR` reader - This bit enable the address phase of an operation."]
106pub type USR_ADDR_R = crate::BitReader;
107#[doc = "Field `USR_ADDR` writer - This bit enable the address phase of an operation."]
108pub type USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `USR_COMMAND` reader - This bit enable the command phase of an operation."]
110pub type USR_COMMAND_R = crate::BitReader;
111#[doc = "Field `USR_COMMAND` writer - This bit enable the command phase of an operation."]
112pub type USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>;
113impl R {
114 #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable."]
115 #[inline(always)]
116 pub fn doutdin(&self) -> DOUTDIN_R {
117 DOUTDIN_R::new((self.bits & 1) != 0)
118 }
119 #[doc = "Bit 4 - spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable."]
120 #[inline(always)]
121 pub fn cs_hold(&self) -> CS_HOLD_R {
122 CS_HOLD_R::new(((self.bits >> 4) & 1) != 0)
123 }
124 #[doc = "Bit 5 - spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable."]
125 #[inline(always)]
126 pub fn cs_setup(&self) -> CS_SETUP_R {
127 CS_SETUP_R::new(((self.bits >> 5) & 1) != 0)
128 }
129 #[doc = "Bit 6 - In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits."]
130 #[inline(always)]
131 pub fn ck_i_edge(&self) -> CK_I_EDGE_R {
132 CK_I_EDGE_R::new(((self.bits >> 6) & 1) != 0)
133 }
134 #[doc = "Bit 7 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode."]
135 #[inline(always)]
136 pub fn ck_out_edge(&self) -> CK_OUT_EDGE_R {
137 CK_OUT_EDGE_R::new(((self.bits >> 7) & 1) != 0)
138 }
139 #[doc = "Bit 10 - In read-data (MISO) phase 1: big-endian 0: little_endian"]
140 #[inline(always)]
141 pub fn rd_byte_order(&self) -> RD_BYTE_ORDER_R {
142 RD_BYTE_ORDER_R::new(((self.bits >> 10) & 1) != 0)
143 }
144 #[doc = "Bit 11 - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian"]
145 #[inline(always)]
146 pub fn wr_byte_order(&self) -> WR_BYTE_ORDER_R {
147 WR_BYTE_ORDER_R::new(((self.bits >> 11) & 1) != 0)
148 }
149 #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals"]
150 #[inline(always)]
151 pub fn fwrite_dual(&self) -> FWRITE_DUAL_R {
152 FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0)
153 }
154 #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals"]
155 #[inline(always)]
156 pub fn fwrite_quad(&self) -> FWRITE_QUAD_R {
157 FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0)
158 }
159 #[doc = "Bit 14 - In the write operations address phase and read-data phase apply 2 signals."]
160 #[inline(always)]
161 pub fn fwrite_dio(&self) -> FWRITE_DIO_R {
162 FWRITE_DIO_R::new(((self.bits >> 14) & 1) != 0)
163 }
164 #[doc = "Bit 15 - In the write operations address phase and read-data phase apply 4 signals."]
165 #[inline(always)]
166 pub fn fwrite_qio(&self) -> FWRITE_QIO_R {
167 FWRITE_QIO_R::new(((self.bits >> 15) & 1) != 0)
168 }
169 #[doc = "Bit 16 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable."]
170 #[inline(always)]
171 pub fn sio(&self) -> SIO_R {
172 SIO_R::new(((self.bits >> 16) & 1) != 0)
173 }
174 #[doc = "Bit 17 - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low"]
175 #[inline(always)]
176 pub fn usr_hold_pol(&self) -> USR_HOLD_POL_R {
177 USR_HOLD_POL_R::new(((self.bits >> 17) & 1) != 0)
178 }
179 #[doc = "Bit 18 - spi is hold at data out state the bit combined with spi_usr_hold_pol bit."]
180 #[inline(always)]
181 pub fn usr_dout_hold(&self) -> USR_DOUT_HOLD_R {
182 USR_DOUT_HOLD_R::new(((self.bits >> 18) & 1) != 0)
183 }
184 #[doc = "Bit 19 - spi is hold at data in state the bit combined with spi_usr_hold_pol bit."]
185 #[inline(always)]
186 pub fn usr_din_hold(&self) -> USR_DIN_HOLD_R {
187 USR_DIN_HOLD_R::new(((self.bits >> 19) & 1) != 0)
188 }
189 #[doc = "Bit 20 - spi is hold at dummy state the bit combined with spi_usr_hold_pol bit."]
190 #[inline(always)]
191 pub fn usr_dummy_hold(&self) -> USR_DUMMY_HOLD_R {
192 USR_DUMMY_HOLD_R::new(((self.bits >> 20) & 1) != 0)
193 }
194 #[doc = "Bit 21 - spi is hold at address state the bit combined with spi_usr_hold_pol bit."]
195 #[inline(always)]
196 pub fn usr_addr_hold(&self) -> USR_ADDR_HOLD_R {
197 USR_ADDR_HOLD_R::new(((self.bits >> 21) & 1) != 0)
198 }
199 #[doc = "Bit 22 - spi is hold at command state the bit combined with spi_usr_hold_pol bit."]
200 #[inline(always)]
201 pub fn usr_cmd_hold(&self) -> USR_CMD_HOLD_R {
202 USR_CMD_HOLD_R::new(((self.bits >> 22) & 1) != 0)
203 }
204 #[doc = "Bit 23 - spi is hold at prepare state the bit combined with spi_usr_hold_pol bit."]
205 #[inline(always)]
206 pub fn usr_prep_hold(&self) -> USR_PREP_HOLD_R {
207 USR_PREP_HOLD_R::new(((self.bits >> 23) & 1) != 0)
208 }
209 #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable."]
210 #[inline(always)]
211 pub fn usr_miso_highpart(&self) -> USR_MISO_HIGHPART_R {
212 USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0)
213 }
214 #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable."]
215 #[inline(always)]
216 pub fn usr_mosi_highpart(&self) -> USR_MOSI_HIGHPART_R {
217 USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0)
218 }
219 #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable."]
220 #[inline(always)]
221 pub fn usr_dummy_idle(&self) -> USR_DUMMY_IDLE_R {
222 USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0)
223 }
224 #[doc = "Bit 27 - This bit enable the write-data phase of an operation."]
225 #[inline(always)]
226 pub fn usr_mosi(&self) -> USR_MOSI_R {
227 USR_MOSI_R::new(((self.bits >> 27) & 1) != 0)
228 }
229 #[doc = "Bit 28 - This bit enable the read-data phase of an operation."]
230 #[inline(always)]
231 pub fn usr_miso(&self) -> USR_MISO_R {
232 USR_MISO_R::new(((self.bits >> 28) & 1) != 0)
233 }
234 #[doc = "Bit 29 - This bit enable the dummy phase of an operation."]
235 #[inline(always)]
236 pub fn usr_dummy(&self) -> USR_DUMMY_R {
237 USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0)
238 }
239 #[doc = "Bit 30 - This bit enable the address phase of an operation."]
240 #[inline(always)]
241 pub fn usr_addr(&self) -> USR_ADDR_R {
242 USR_ADDR_R::new(((self.bits >> 30) & 1) != 0)
243 }
244 #[doc = "Bit 31 - This bit enable the command phase of an operation."]
245 #[inline(always)]
246 pub fn usr_command(&self) -> USR_COMMAND_R {
247 USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0)
248 }
249}
250#[cfg(feature = "impl-register-debug")]
251impl core::fmt::Debug for R {
252 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
253 f.debug_struct("USER")
254 .field("doutdin", &self.doutdin())
255 .field("cs_hold", &self.cs_hold())
256 .field("cs_setup", &self.cs_setup())
257 .field("ck_i_edge", &self.ck_i_edge())
258 .field("ck_out_edge", &self.ck_out_edge())
259 .field("rd_byte_order", &self.rd_byte_order())
260 .field("wr_byte_order", &self.wr_byte_order())
261 .field("fwrite_dual", &self.fwrite_dual())
262 .field("fwrite_quad", &self.fwrite_quad())
263 .field("fwrite_dio", &self.fwrite_dio())
264 .field("fwrite_qio", &self.fwrite_qio())
265 .field("sio", &self.sio())
266 .field("usr_hold_pol", &self.usr_hold_pol())
267 .field("usr_dout_hold", &self.usr_dout_hold())
268 .field("usr_din_hold", &self.usr_din_hold())
269 .field("usr_dummy_hold", &self.usr_dummy_hold())
270 .field("usr_addr_hold", &self.usr_addr_hold())
271 .field("usr_cmd_hold", &self.usr_cmd_hold())
272 .field("usr_prep_hold", &self.usr_prep_hold())
273 .field("usr_miso_highpart", &self.usr_miso_highpart())
274 .field("usr_mosi_highpart", &self.usr_mosi_highpart())
275 .field("usr_dummy_idle", &self.usr_dummy_idle())
276 .field("usr_mosi", &self.usr_mosi())
277 .field("usr_miso", &self.usr_miso())
278 .field("usr_dummy", &self.usr_dummy())
279 .field("usr_addr", &self.usr_addr())
280 .field("usr_command", &self.usr_command())
281 .finish()
282 }
283}
284impl W {
285 #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable."]
286 #[inline(always)]
287 pub fn doutdin(&mut self) -> DOUTDIN_W<USER_SPEC> {
288 DOUTDIN_W::new(self, 0)
289 }
290 #[doc = "Bit 4 - spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable."]
291 #[inline(always)]
292 pub fn cs_hold(&mut self) -> CS_HOLD_W<USER_SPEC> {
293 CS_HOLD_W::new(self, 4)
294 }
295 #[doc = "Bit 5 - spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable."]
296 #[inline(always)]
297 pub fn cs_setup(&mut self) -> CS_SETUP_W<USER_SPEC> {
298 CS_SETUP_W::new(self, 5)
299 }
300 #[doc = "Bit 6 - In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits."]
301 #[inline(always)]
302 pub fn ck_i_edge(&mut self) -> CK_I_EDGE_W<USER_SPEC> {
303 CK_I_EDGE_W::new(self, 6)
304 }
305 #[doc = "Bit 7 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode."]
306 #[inline(always)]
307 pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
308 CK_OUT_EDGE_W::new(self, 7)
309 }
310 #[doc = "Bit 10 - In read-data (MISO) phase 1: big-endian 0: little_endian"]
311 #[inline(always)]
312 pub fn rd_byte_order(&mut self) -> RD_BYTE_ORDER_W<USER_SPEC> {
313 RD_BYTE_ORDER_W::new(self, 10)
314 }
315 #[doc = "Bit 11 - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian"]
316 #[inline(always)]
317 pub fn wr_byte_order(&mut self) -> WR_BYTE_ORDER_W<USER_SPEC> {
318 WR_BYTE_ORDER_W::new(self, 11)
319 }
320 #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals"]
321 #[inline(always)]
322 pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<USER_SPEC> {
323 FWRITE_DUAL_W::new(self, 12)
324 }
325 #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals"]
326 #[inline(always)]
327 pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<USER_SPEC> {
328 FWRITE_QUAD_W::new(self, 13)
329 }
330 #[doc = "Bit 14 - In the write operations address phase and read-data phase apply 2 signals."]
331 #[inline(always)]
332 pub fn fwrite_dio(&mut self) -> FWRITE_DIO_W<USER_SPEC> {
333 FWRITE_DIO_W::new(self, 14)
334 }
335 #[doc = "Bit 15 - In the write operations address phase and read-data phase apply 4 signals."]
336 #[inline(always)]
337 pub fn fwrite_qio(&mut self) -> FWRITE_QIO_W<USER_SPEC> {
338 FWRITE_QIO_W::new(self, 15)
339 }
340 #[doc = "Bit 16 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable."]
341 #[inline(always)]
342 pub fn sio(&mut self) -> SIO_W<USER_SPEC> {
343 SIO_W::new(self, 16)
344 }
345 #[doc = "Bit 17 - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low"]
346 #[inline(always)]
347 pub fn usr_hold_pol(&mut self) -> USR_HOLD_POL_W<USER_SPEC> {
348 USR_HOLD_POL_W::new(self, 17)
349 }
350 #[doc = "Bit 18 - spi is hold at data out state the bit combined with spi_usr_hold_pol bit."]
351 #[inline(always)]
352 pub fn usr_dout_hold(&mut self) -> USR_DOUT_HOLD_W<USER_SPEC> {
353 USR_DOUT_HOLD_W::new(self, 18)
354 }
355 #[doc = "Bit 19 - spi is hold at data in state the bit combined with spi_usr_hold_pol bit."]
356 #[inline(always)]
357 pub fn usr_din_hold(&mut self) -> USR_DIN_HOLD_W<USER_SPEC> {
358 USR_DIN_HOLD_W::new(self, 19)
359 }
360 #[doc = "Bit 20 - spi is hold at dummy state the bit combined with spi_usr_hold_pol bit."]
361 #[inline(always)]
362 pub fn usr_dummy_hold(&mut self) -> USR_DUMMY_HOLD_W<USER_SPEC> {
363 USR_DUMMY_HOLD_W::new(self, 20)
364 }
365 #[doc = "Bit 21 - spi is hold at address state the bit combined with spi_usr_hold_pol bit."]
366 #[inline(always)]
367 pub fn usr_addr_hold(&mut self) -> USR_ADDR_HOLD_W<USER_SPEC> {
368 USR_ADDR_HOLD_W::new(self, 21)
369 }
370 #[doc = "Bit 22 - spi is hold at command state the bit combined with spi_usr_hold_pol bit."]
371 #[inline(always)]
372 pub fn usr_cmd_hold(&mut self) -> USR_CMD_HOLD_W<USER_SPEC> {
373 USR_CMD_HOLD_W::new(self, 22)
374 }
375 #[doc = "Bit 23 - spi is hold at prepare state the bit combined with spi_usr_hold_pol bit."]
376 #[inline(always)]
377 pub fn usr_prep_hold(&mut self) -> USR_PREP_HOLD_W<USER_SPEC> {
378 USR_PREP_HOLD_W::new(self, 23)
379 }
380 #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable."]
381 #[inline(always)]
382 pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<USER_SPEC> {
383 USR_MISO_HIGHPART_W::new(self, 24)
384 }
385 #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable."]
386 #[inline(always)]
387 pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<USER_SPEC> {
388 USR_MOSI_HIGHPART_W::new(self, 25)
389 }
390 #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable."]
391 #[inline(always)]
392 pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
393 USR_DUMMY_IDLE_W::new(self, 26)
394 }
395 #[doc = "Bit 27 - This bit enable the write-data phase of an operation."]
396 #[inline(always)]
397 pub fn usr_mosi(&mut self) -> USR_MOSI_W<USER_SPEC> {
398 USR_MOSI_W::new(self, 27)
399 }
400 #[doc = "Bit 28 - This bit enable the read-data phase of an operation."]
401 #[inline(always)]
402 pub fn usr_miso(&mut self) -> USR_MISO_W<USER_SPEC> {
403 USR_MISO_W::new(self, 28)
404 }
405 #[doc = "Bit 29 - This bit enable the dummy phase of an operation."]
406 #[inline(always)]
407 pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
408 USR_DUMMY_W::new(self, 29)
409 }
410 #[doc = "Bit 30 - This bit enable the address phase of an operation."]
411 #[inline(always)]
412 pub fn usr_addr(&mut self) -> USR_ADDR_W<USER_SPEC> {
413 USR_ADDR_W::new(self, 30)
414 }
415 #[doc = "Bit 31 - This bit enable the command phase of an operation."]
416 #[inline(always)]
417 pub fn usr_command(&mut self) -> USR_COMMAND_W<USER_SPEC> {
418 USR_COMMAND_W::new(self, 31)
419 }
420}
421#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`user::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
422pub struct USER_SPEC;
423impl crate::RegisterSpec for USER_SPEC {
424 type Ux = u32;
425}
426#[doc = "`read()` method returns [`user::R`](R) reader structure"]
427impl crate::Readable for USER_SPEC {}
428#[doc = "`write(|w| ..)` method takes [`user::W`](W) writer structure"]
429impl crate::Writable for USER_SPEC {
430 type Safety = crate::Unsafe;
431 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
432 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
433}
434#[doc = "`reset()` method sets USER to value 0x8000_0040"]
435impl crate::Resettable for USER_SPEC {
436 const RESET_VALUE: u32 = 0x8000_0040;
437}