esp32/spi0/
cache_fctrl.rs

1#[doc = "Register `CACHE_FCTRL` reader"]
2pub type R = crate::R<CACHE_FCTRL_SPEC>;
3#[doc = "Register `CACHE_FCTRL` writer"]
4pub type W = crate::W<CACHE_FCTRL_SPEC>;
5#[doc = "Field `CACHE_REQ_EN` reader - For SPI0 Cache access enable 1: enable 0:disable."]
6pub type CACHE_REQ_EN_R = crate::BitReader;
7#[doc = "Field `CACHE_REQ_EN` writer - For SPI0 Cache access enable 1: enable 0:disable."]
8pub type CACHE_REQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CACHE_USR_CMD_4BYTE` reader - For SPI0 cache read flash with 4 bytes command 1: enable 0:disable."]
10pub type CACHE_USR_CMD_4BYTE_R = crate::BitReader;
11#[doc = "Field `CACHE_USR_CMD_4BYTE` writer - For SPI0 cache read flash with 4 bytes command 1: enable 0:disable."]
12pub type CACHE_USR_CMD_4BYTE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CACHE_FLASH_USR_CMD` reader - For SPI0 cache read flash for user define command 1: enable 0:disable."]
14pub type CACHE_FLASH_USR_CMD_R = crate::BitReader;
15#[doc = "Field `CACHE_FLASH_USR_CMD` writer - For SPI0 cache read flash for user define command 1: enable 0:disable."]
16pub type CACHE_FLASH_USR_CMD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CACHE_FLASH_PES_EN` reader - For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable."]
18pub type CACHE_FLASH_PES_EN_R = crate::BitReader;
19#[doc = "Field `CACHE_FLASH_PES_EN` writer - For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable."]
20pub type CACHE_FLASH_PES_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - For SPI0 Cache access enable 1: enable 0:disable."]
23    #[inline(always)]
24    pub fn cache_req_en(&self) -> CACHE_REQ_EN_R {
25        CACHE_REQ_EN_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - For SPI0 cache read flash with 4 bytes command 1: enable 0:disable."]
28    #[inline(always)]
29    pub fn cache_usr_cmd_4byte(&self) -> CACHE_USR_CMD_4BYTE_R {
30        CACHE_USR_CMD_4BYTE_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - For SPI0 cache read flash for user define command 1: enable 0:disable."]
33    #[inline(always)]
34    pub fn cache_flash_usr_cmd(&self) -> CACHE_FLASH_USR_CMD_R {
35        CACHE_FLASH_USR_CMD_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable."]
38    #[inline(always)]
39    pub fn cache_flash_pes_en(&self) -> CACHE_FLASH_PES_EN_R {
40        CACHE_FLASH_PES_EN_R::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CACHE_FCTRL")
47            .field("cache_req_en", &self.cache_req_en())
48            .field("cache_usr_cmd_4byte", &self.cache_usr_cmd_4byte())
49            .field("cache_flash_usr_cmd", &self.cache_flash_usr_cmd())
50            .field("cache_flash_pes_en", &self.cache_flash_pes_en())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bit 0 - For SPI0 Cache access enable 1: enable 0:disable."]
56    #[inline(always)]
57    pub fn cache_req_en(&mut self) -> CACHE_REQ_EN_W<CACHE_FCTRL_SPEC> {
58        CACHE_REQ_EN_W::new(self, 0)
59    }
60    #[doc = "Bit 1 - For SPI0 cache read flash with 4 bytes command 1: enable 0:disable."]
61    #[inline(always)]
62    pub fn cache_usr_cmd_4byte(&mut self) -> CACHE_USR_CMD_4BYTE_W<CACHE_FCTRL_SPEC> {
63        CACHE_USR_CMD_4BYTE_W::new(self, 1)
64    }
65    #[doc = "Bit 2 - For SPI0 cache read flash for user define command 1: enable 0:disable."]
66    #[inline(always)]
67    pub fn cache_flash_usr_cmd(&mut self) -> CACHE_FLASH_USR_CMD_W<CACHE_FCTRL_SPEC> {
68        CACHE_FLASH_USR_CMD_W::new(self, 2)
69    }
70    #[doc = "Bit 3 - For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable."]
71    #[inline(always)]
72    pub fn cache_flash_pes_en(&mut self) -> CACHE_FLASH_PES_EN_W<CACHE_FCTRL_SPEC> {
73        CACHE_FLASH_PES_EN_W::new(self, 3)
74    }
75}
76#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_fctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_fctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct CACHE_FCTRL_SPEC;
78impl crate::RegisterSpec for CACHE_FCTRL_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`cache_fctrl::R`](R) reader structure"]
82impl crate::Readable for CACHE_FCTRL_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`cache_fctrl::W`](W) writer structure"]
84impl crate::Writable for CACHE_FCTRL_SPEC {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets CACHE_FCTRL to value 0"]
90impl crate::Resettable for CACHE_FCTRL_SPEC {
91    const RESET_VALUE: u32 = 0;
92}
esp32/spi0/cache_fctrl.rs

esp32/spi0/
cache_fctrl.rs
