esp32/emac_ext/
ex_oscclk_conf.rs

1#[doc = "Register `EX_OSCCLK_CONF` reader"]
2pub type R = crate::R<EX_OSCCLK_CONF_SPEC>;
3#[doc = "Register `EX_OSCCLK_CONF` writer"]
4pub type W = crate::W<EX_OSCCLK_CONF_SPEC>;
5#[doc = "Field `DIV_NUM_10M` reader - "]
6pub type DIV_NUM_10M_R = crate::FieldReader;
7#[doc = "Field `DIV_NUM_10M` writer - "]
8pub type DIV_NUM_10M_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `H_DIV_NUM_10M` reader - "]
10pub type H_DIV_NUM_10M_R = crate::FieldReader;
11#[doc = "Field `H_DIV_NUM_10M` writer - "]
12pub type H_DIV_NUM_10M_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `DIV_NUM_100M` reader - "]
14pub type DIV_NUM_100M_R = crate::FieldReader;
15#[doc = "Field `DIV_NUM_100M` writer - "]
16pub type DIV_NUM_100M_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `H_DIV_NUM_100M` reader - "]
18pub type H_DIV_NUM_100M_R = crate::FieldReader;
19#[doc = "Field `H_DIV_NUM_100M` writer - "]
20pub type H_DIV_NUM_100M_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
21#[doc = "Field `CLK_SEL` reader - "]
22pub type CLK_SEL_R = crate::BitReader;
23#[doc = "Field `CLK_SEL` writer - "]
24pub type CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bits 0:5"]
27    #[inline(always)]
28    pub fn div_num_10m(&self) -> DIV_NUM_10M_R {
29        DIV_NUM_10M_R::new((self.bits & 0x3f) as u8)
30    }
31    #[doc = "Bits 6:11"]
32    #[inline(always)]
33    pub fn h_div_num_10m(&self) -> H_DIV_NUM_10M_R {
34        H_DIV_NUM_10M_R::new(((self.bits >> 6) & 0x3f) as u8)
35    }
36    #[doc = "Bits 12:17"]
37    #[inline(always)]
38    pub fn div_num_100m(&self) -> DIV_NUM_100M_R {
39        DIV_NUM_100M_R::new(((self.bits >> 12) & 0x3f) as u8)
40    }
41    #[doc = "Bits 18:23"]
42    #[inline(always)]
43    pub fn h_div_num_100m(&self) -> H_DIV_NUM_100M_R {
44        H_DIV_NUM_100M_R::new(((self.bits >> 18) & 0x3f) as u8)
45    }
46    #[doc = "Bit 24"]
47    #[inline(always)]
48    pub fn clk_sel(&self) -> CLK_SEL_R {
49        CLK_SEL_R::new(((self.bits >> 24) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("EX_OSCCLK_CONF")
56            .field("div_num_10m", &self.div_num_10m())
57            .field("h_div_num_10m", &self.h_div_num_10m())
58            .field("div_num_100m", &self.div_num_100m())
59            .field("h_div_num_100m", &self.h_div_num_100m())
60            .field("clk_sel", &self.clk_sel())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bits 0:5"]
66    #[inline(always)]
67    pub fn div_num_10m(&mut self) -> DIV_NUM_10M_W<EX_OSCCLK_CONF_SPEC> {
68        DIV_NUM_10M_W::new(self, 0)
69    }
70    #[doc = "Bits 6:11"]
71    #[inline(always)]
72    pub fn h_div_num_10m(&mut self) -> H_DIV_NUM_10M_W<EX_OSCCLK_CONF_SPEC> {
73        H_DIV_NUM_10M_W::new(self, 6)
74    }
75    #[doc = "Bits 12:17"]
76    #[inline(always)]
77    pub fn div_num_100m(&mut self) -> DIV_NUM_100M_W<EX_OSCCLK_CONF_SPEC> {
78        DIV_NUM_100M_W::new(self, 12)
79    }
80    #[doc = "Bits 18:23"]
81    #[inline(always)]
82    pub fn h_div_num_100m(&mut self) -> H_DIV_NUM_100M_W<EX_OSCCLK_CONF_SPEC> {
83        H_DIV_NUM_100M_W::new(self, 18)
84    }
85    #[doc = "Bit 24"]
86    #[inline(always)]
87    pub fn clk_sel(&mut self) -> CLK_SEL_W<EX_OSCCLK_CONF_SPEC> {
88        CLK_SEL_W::new(self, 24)
89    }
90}
91#[doc = "RMII clock half and whole divider settings\n\nYou can [`read`](crate::Reg::read) this register and get [`ex_oscclk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ex_oscclk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct EX_OSCCLK_CONF_SPEC;
93impl crate::RegisterSpec for EX_OSCCLK_CONF_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`ex_oscclk_conf::R`](R) reader structure"]
97impl crate::Readable for EX_OSCCLK_CONF_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`ex_oscclk_conf::W`](W) writer structure"]
99impl crate::Writable for EX_OSCCLK_CONF_SPEC {
100    type Safety = crate::Unsafe;
101    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets EX_OSCCLK_CONF to value 0"]
105impl crate::Resettable for EX_OSCCLK_CONF_SPEC {
106    const RESET_VALUE: u32 = 0;
107}
esp32/emac_ext/ex_oscclk_conf.rs

esp32/emac_ext/
ex_oscclk_conf.rs
