1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `CH_TX_END(0-7)` reader - The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s."]
4pub type CH_TX_END_R = crate::BitReader;
5#[doc = "Field `CH_RX_END(0-7)` reader - The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s."]
6pub type CH_RX_END_R = crate::BitReader;
7#[doc = "Field `CH_ERR(0-7)` reader - The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s."]
8pub type CH_ERR_R = crate::BitReader;
9#[doc = "Field `CH_TX_THR_EVENT(0-7)` reader - The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1."]
10pub type CH_TX_THR_EVENT_R = crate::BitReader;
11impl R {
12 #[doc = "The interrupt state bit for channel (0-7)'s mt_ch(0-7)_tx_end_int_raw when mt_ch(0-7)_tx_end_int_ena is set to (0-7)."]
13 #[doc = ""]
14 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
15 #[inline(always)]
16 pub fn ch_tx_end(&self, n: u8) -> CH_TX_END_R {
17 #[allow(clippy::no_effect)]
18 [(); 8][n as usize];
19 CH_TX_END_R::new(((self.bits >> (n * 3)) & 1) != 0)
20 }
21 #[doc = "Iterator for array of:"]
22 #[doc = "The interrupt state bit for channel (0-7)'s mt_ch(0-7)_tx_end_int_raw when mt_ch(0-7)_tx_end_int_ena is set to (0-7)."]
23 #[inline(always)]
24 pub fn ch_tx_end_iter(&self) -> impl Iterator<Item = CH_TX_END_R> + '_ {
25 (0..8).map(move |n| CH_TX_END_R::new(((self.bits >> (n * 3)) & 1) != 0))
26 }
27 #[doc = "Bit 0 - The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0."]
28 #[inline(always)]
29 pub fn ch0_tx_end(&self) -> CH_TX_END_R {
30 CH_TX_END_R::new((self.bits & 1) != 0)
31 }
32 #[doc = "Bit 3 - The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1."]
33 #[inline(always)]
34 pub fn ch1_tx_end(&self) -> CH_TX_END_R {
35 CH_TX_END_R::new(((self.bits >> 3) & 1) != 0)
36 }
37 #[doc = "Bit 6 - The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 2."]
38 #[inline(always)]
39 pub fn ch2_tx_end(&self) -> CH_TX_END_R {
40 CH_TX_END_R::new(((self.bits >> 6) & 1) != 0)
41 }
42 #[doc = "Bit 9 - The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 3."]
43 #[inline(always)]
44 pub fn ch3_tx_end(&self) -> CH_TX_END_R {
45 CH_TX_END_R::new(((self.bits >> 9) & 1) != 0)
46 }
47 #[doc = "Bit 12 - The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 4."]
48 #[inline(always)]
49 pub fn ch4_tx_end(&self) -> CH_TX_END_R {
50 CH_TX_END_R::new(((self.bits >> 12) & 1) != 0)
51 }
52 #[doc = "Bit 15 - The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 5."]
53 #[inline(always)]
54 pub fn ch5_tx_end(&self) -> CH_TX_END_R {
55 CH_TX_END_R::new(((self.bits >> 15) & 1) != 0)
56 }
57 #[doc = "Bit 18 - The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 6."]
58 #[inline(always)]
59 pub fn ch6_tx_end(&self) -> CH_TX_END_R {
60 CH_TX_END_R::new(((self.bits >> 18) & 1) != 0)
61 }
62 #[doc = "Bit 21 - The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 7."]
63 #[inline(always)]
64 pub fn ch7_tx_end(&self) -> CH_TX_END_R {
65 CH_TX_END_R::new(((self.bits >> 21) & 1) != 0)
66 }
67 #[doc = "The interrupt state bit for channel (0-7)'s rmt_ch(0-7)_rx_end_int_raw when rmt_ch(0-7)_rx_end_int_ena is set to (0-7)."]
68 #[doc = ""]
69 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field.</div>"]
70 #[inline(always)]
71 pub fn ch_rx_end(&self, n: u8) -> CH_RX_END_R {
72 #[allow(clippy::no_effect)]
73 [(); 8][n as usize];
74 CH_RX_END_R::new(((self.bits >> (n * 3 + 1)) & 1) != 0)
75 }
76 #[doc = "Iterator for array of:"]
77 #[doc = "The interrupt state bit for channel (0-7)'s rmt_ch(0-7)_rx_end_int_raw when rmt_ch(0-7)_rx_end_int_ena is set to (0-7)."]
78 #[inline(always)]
79 pub fn ch_rx_end_iter(&self) -> impl Iterator<Item = CH_RX_END_R> + '_ {
80 (0..8).map(move |n| CH_RX_END_R::new(((self.bits >> (n * 3 + 1)) & 1) != 0))
81 }
82 #[doc = "Bit 1 - The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0."]
83 #[inline(always)]
84 pub fn ch0_rx_end(&self) -> CH_RX_END_R {
85 CH_RX_END_R::new(((self.bits >> 1) & 1) != 0)
86 }
87 #[doc = "Bit 4 - The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1."]
88 #[inline(always)]
89 pub fn ch1_rx_end(&self) -> CH_RX_END_R {
90 CH_RX_END_R::new(((self.bits >> 4) & 1) != 0)
91 }
92 #[doc = "Bit 7 - The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 2."]
93 #[inline(always)]
94 pub fn ch2_rx_end(&self) -> CH_RX_END_R {
95 CH_RX_END_R::new(((self.bits >> 7) & 1) != 0)
96 }
97 #[doc = "Bit 10 - The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 3."]
98 #[inline(always)]
99 pub fn ch3_rx_end(&self) -> CH_RX_END_R {
100 CH_RX_END_R::new(((self.bits >> 10) & 1) != 0)
101 }
102 #[doc = "Bit 13 - The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 4."]
103 #[inline(always)]
104 pub fn ch4_rx_end(&self) -> CH_RX_END_R {
105 CH_RX_END_R::new(((self.bits >> 13) & 1) != 0)
106 }
107 #[doc = "Bit 16 - The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 5."]
108 #[inline(always)]
109 pub fn ch5_rx_end(&self) -> CH_RX_END_R {
110 CH_RX_END_R::new(((self.bits >> 16) & 1) != 0)
111 }
112 #[doc = "Bit 19 - The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 6."]
113 #[inline(always)]
114 pub fn ch6_rx_end(&self) -> CH_RX_END_R {
115 CH_RX_END_R::new(((self.bits >> 19) & 1) != 0)
116 }
117 #[doc = "Bit 22 - The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 7."]
118 #[inline(always)]
119 pub fn ch7_rx_end(&self) -> CH_RX_END_R {
120 CH_RX_END_R::new(((self.bits >> 22) & 1) != 0)
121 }
122 #[doc = "The interrupt state bit for channel (0-7)'s rmt_ch(0-7)_err_int_raw when rmt_ch(0-7)_err_int_ena is set to (0-7)."]
123 #[doc = ""]
124 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field.</div>"]
125 #[inline(always)]
126 pub fn ch_err(&self, n: u8) -> CH_ERR_R {
127 #[allow(clippy::no_effect)]
128 [(); 8][n as usize];
129 CH_ERR_R::new(((self.bits >> (n * 3 + 2)) & 1) != 0)
130 }
131 #[doc = "Iterator for array of:"]
132 #[doc = "The interrupt state bit for channel (0-7)'s rmt_ch(0-7)_err_int_raw when rmt_ch(0-7)_err_int_ena is set to (0-7)."]
133 #[inline(always)]
134 pub fn ch_err_iter(&self) -> impl Iterator<Item = CH_ERR_R> + '_ {
135 (0..8).map(move |n| CH_ERR_R::new(((self.bits >> (n * 3 + 2)) & 1) != 0))
136 }
137 #[doc = "Bit 2 - The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0."]
138 #[inline(always)]
139 pub fn ch0_err(&self) -> CH_ERR_R {
140 CH_ERR_R::new(((self.bits >> 2) & 1) != 0)
141 }
142 #[doc = "Bit 5 - The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1."]
143 #[inline(always)]
144 pub fn ch1_err(&self) -> CH_ERR_R {
145 CH_ERR_R::new(((self.bits >> 5) & 1) != 0)
146 }
147 #[doc = "Bit 8 - The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 2."]
148 #[inline(always)]
149 pub fn ch2_err(&self) -> CH_ERR_R {
150 CH_ERR_R::new(((self.bits >> 8) & 1) != 0)
151 }
152 #[doc = "Bit 11 - The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 3."]
153 #[inline(always)]
154 pub fn ch3_err(&self) -> CH_ERR_R {
155 CH_ERR_R::new(((self.bits >> 11) & 1) != 0)
156 }
157 #[doc = "Bit 14 - The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 4."]
158 #[inline(always)]
159 pub fn ch4_err(&self) -> CH_ERR_R {
160 CH_ERR_R::new(((self.bits >> 14) & 1) != 0)
161 }
162 #[doc = "Bit 17 - The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 5."]
163 #[inline(always)]
164 pub fn ch5_err(&self) -> CH_ERR_R {
165 CH_ERR_R::new(((self.bits >> 17) & 1) != 0)
166 }
167 #[doc = "Bit 20 - The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 6."]
168 #[inline(always)]
169 pub fn ch6_err(&self) -> CH_ERR_R {
170 CH_ERR_R::new(((self.bits >> 20) & 1) != 0)
171 }
172 #[doc = "Bit 23 - The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 7."]
173 #[inline(always)]
174 pub fn ch7_err(&self) -> CH_ERR_R {
175 CH_ERR_R::new(((self.bits >> 23) & 1) != 0)
176 }
177 #[doc = "The interrupt state bit for channel (0-7)'s rmt_ch(0-7)_tx_thr_event_int_raw when mt_ch(0-7)_tx_thr_event_int_ena is set to 1."]
178 #[doc = ""]
179 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
180 #[inline(always)]
181 pub fn ch_tx_thr_event(&self, n: u8) -> CH_TX_THR_EVENT_R {
182 #[allow(clippy::no_effect)]
183 [(); 8][n as usize];
184 CH_TX_THR_EVENT_R::new(((self.bits >> (n + 24)) & 1) != 0)
185 }
186 #[doc = "Iterator for array of:"]
187 #[doc = "The interrupt state bit for channel (0-7)'s rmt_ch(0-7)_tx_thr_event_int_raw when mt_ch(0-7)_tx_thr_event_int_ena is set to 1."]
188 #[inline(always)]
189 pub fn ch_tx_thr_event_iter(&self) -> impl Iterator<Item = CH_TX_THR_EVENT_R> + '_ {
190 (0..8).map(move |n| CH_TX_THR_EVENT_R::new(((self.bits >> (n + 24)) & 1) != 0))
191 }
192 #[doc = "Bit 24 - The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1."]
193 #[inline(always)]
194 pub fn ch0_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
195 CH_TX_THR_EVENT_R::new(((self.bits >> 24) & 1) != 0)
196 }
197 #[doc = "Bit 25 - The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1."]
198 #[inline(always)]
199 pub fn ch1_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
200 CH_TX_THR_EVENT_R::new(((self.bits >> 25) & 1) != 0)
201 }
202 #[doc = "Bit 26 - The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1."]
203 #[inline(always)]
204 pub fn ch2_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
205 CH_TX_THR_EVENT_R::new(((self.bits >> 26) & 1) != 0)
206 }
207 #[doc = "Bit 27 - The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1."]
208 #[inline(always)]
209 pub fn ch3_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
210 CH_TX_THR_EVENT_R::new(((self.bits >> 27) & 1) != 0)
211 }
212 #[doc = "Bit 28 - The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1."]
213 #[inline(always)]
214 pub fn ch4_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
215 CH_TX_THR_EVENT_R::new(((self.bits >> 28) & 1) != 0)
216 }
217 #[doc = "Bit 29 - The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1."]
218 #[inline(always)]
219 pub fn ch5_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
220 CH_TX_THR_EVENT_R::new(((self.bits >> 29) & 1) != 0)
221 }
222 #[doc = "Bit 30 - The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1."]
223 #[inline(always)]
224 pub fn ch6_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
225 CH_TX_THR_EVENT_R::new(((self.bits >> 30) & 1) != 0)
226 }
227 #[doc = "Bit 31 - The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1."]
228 #[inline(always)]
229 pub fn ch7_tx_thr_event(&self) -> CH_TX_THR_EVENT_R {
230 CH_TX_THR_EVENT_R::new(((self.bits >> 31) & 1) != 0)
231 }
232}
233#[cfg(feature = "impl-register-debug")]
234impl core::fmt::Debug for R {
235 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
236 f.debug_struct("INT_ST")
237 .field("ch0_tx_end", &self.ch0_tx_end())
238 .field("ch1_tx_end", &self.ch1_tx_end())
239 .field("ch2_tx_end", &self.ch2_tx_end())
240 .field("ch3_tx_end", &self.ch3_tx_end())
241 .field("ch4_tx_end", &self.ch4_tx_end())
242 .field("ch5_tx_end", &self.ch5_tx_end())
243 .field("ch6_tx_end", &self.ch6_tx_end())
244 .field("ch7_tx_end", &self.ch7_tx_end())
245 .field("ch0_rx_end", &self.ch0_rx_end())
246 .field("ch1_rx_end", &self.ch1_rx_end())
247 .field("ch2_rx_end", &self.ch2_rx_end())
248 .field("ch3_rx_end", &self.ch3_rx_end())
249 .field("ch4_rx_end", &self.ch4_rx_end())
250 .field("ch5_rx_end", &self.ch5_rx_end())
251 .field("ch6_rx_end", &self.ch6_rx_end())
252 .field("ch7_rx_end", &self.ch7_rx_end())
253 .field("ch0_err", &self.ch0_err())
254 .field("ch1_err", &self.ch1_err())
255 .field("ch2_err", &self.ch2_err())
256 .field("ch3_err", &self.ch3_err())
257 .field("ch4_err", &self.ch4_err())
258 .field("ch5_err", &self.ch5_err())
259 .field("ch6_err", &self.ch6_err())
260 .field("ch7_err", &self.ch7_err())
261 .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
262 .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
263 .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
264 .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
265 .field("ch4_tx_thr_event", &self.ch4_tx_thr_event())
266 .field("ch5_tx_thr_event", &self.ch5_tx_thr_event())
267 .field("ch6_tx_thr_event", &self.ch6_tx_thr_event())
268 .field("ch7_tx_thr_event", &self.ch7_tx_thr_event())
269 .finish()
270 }
271}
272#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
273pub struct INT_ST_SPEC;
274impl crate::RegisterSpec for INT_ST_SPEC {
275 type Ux = u32;
276}
277#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
278impl crate::Readable for INT_ST_SPEC {}
279#[doc = "`reset()` method sets INT_ST to value 0"]
280impl crate::Resettable for INT_ST_SPEC {
281 const RESET_VALUE: u32 = 0;
282}