esp32/rtc_i2c/
debug_status.rs

1#[doc = "Register `DEBUG_STATUS` reader"]
2pub type R = crate::R<DEBUG_STATUS_SPEC>;
3#[doc = "Register `DEBUG_STATUS` writer"]
4pub type W = crate::W<DEBUG_STATUS_SPEC>;
5#[doc = "Field `ACK_VAL` reader - The value of an acknowledge signal on the bus"]
6pub type ACK_VAL_R = crate::BitReader;
7#[doc = "Field `ACK_VAL` writer - The value of an acknowledge signal on the bus"]
8pub type ACK_VAL_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SLAVE_RW` reader - When working as a slave, the value of R/W bit received"]
10pub type SLAVE_RW_R = crate::BitReader;
11#[doc = "Field `SLAVE_RW` writer - When working as a slave, the value of R/W bit received"]
12pub type SLAVE_RW_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TIMED_OUT` reader - Transfer has timed out"]
14pub type TIMED_OUT_R = crate::BitReader;
15#[doc = "Field `TIMED_OUT` writer - Transfer has timed out"]
16pub type TIMED_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `ARB_LOST` reader - When working as a master, lost control of I2C bus"]
18pub type ARB_LOST_R = crate::BitReader;
19#[doc = "Field `ARB_LOST` writer - When working as a master, lost control of I2C bus"]
20pub type ARB_LOST_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `BUS_BUSY` reader - operation is in progress"]
22pub type BUS_BUSY_R = crate::BitReader;
23#[doc = "Field `BUS_BUSY` writer - operation is in progress"]
24pub type BUS_BUSY_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SLAVE_ADDR_MATCH` reader - When working as a slave, whether address was matched"]
26pub type SLAVE_ADDR_MATCH_R = crate::BitReader;
27#[doc = "Field `SLAVE_ADDR_MATCH` writer - When working as a slave, whether address was matched"]
28pub type SLAVE_ADDR_MATCH_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `BYTE_TRANS` reader - 8 bit transmit done"]
30pub type BYTE_TRANS_R = crate::BitReader;
31#[doc = "Field `BYTE_TRANS` writer - 8 bit transmit done"]
32pub type BYTE_TRANS_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `MAIN_STATE` reader - state of the main state machine"]
34pub type MAIN_STATE_R = crate::FieldReader;
35#[doc = "Field `MAIN_STATE` writer - state of the main state machine"]
36pub type MAIN_STATE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
37#[doc = "Field `SCL_STATE` reader - state of SCL state machine"]
38pub type SCL_STATE_R = crate::FieldReader;
39#[doc = "Field `SCL_STATE` writer - state of SCL state machine"]
40pub type SCL_STATE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
41impl R {
42    #[doc = "Bit 0 - The value of an acknowledge signal on the bus"]
43    #[inline(always)]
44    pub fn ack_val(&self) -> ACK_VAL_R {
45        ACK_VAL_R::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bit 1 - When working as a slave, the value of R/W bit received"]
48    #[inline(always)]
49    pub fn slave_rw(&self) -> SLAVE_RW_R {
50        SLAVE_RW_R::new(((self.bits >> 1) & 1) != 0)
51    }
52    #[doc = "Bit 2 - Transfer has timed out"]
53    #[inline(always)]
54    pub fn timed_out(&self) -> TIMED_OUT_R {
55        TIMED_OUT_R::new(((self.bits >> 2) & 1) != 0)
56    }
57    #[doc = "Bit 3 - When working as a master, lost control of I2C bus"]
58    #[inline(always)]
59    pub fn arb_lost(&self) -> ARB_LOST_R {
60        ARB_LOST_R::new(((self.bits >> 3) & 1) != 0)
61    }
62    #[doc = "Bit 4 - operation is in progress"]
63    #[inline(always)]
64    pub fn bus_busy(&self) -> BUS_BUSY_R {
65        BUS_BUSY_R::new(((self.bits >> 4) & 1) != 0)
66    }
67    #[doc = "Bit 5 - When working as a slave, whether address was matched"]
68    #[inline(always)]
69    pub fn slave_addr_match(&self) -> SLAVE_ADDR_MATCH_R {
70        SLAVE_ADDR_MATCH_R::new(((self.bits >> 5) & 1) != 0)
71    }
72    #[doc = "Bit 6 - 8 bit transmit done"]
73    #[inline(always)]
74    pub fn byte_trans(&self) -> BYTE_TRANS_R {
75        BYTE_TRANS_R::new(((self.bits >> 6) & 1) != 0)
76    }
77    #[doc = "Bits 25:27 - state of the main state machine"]
78    #[inline(always)]
79    pub fn main_state(&self) -> MAIN_STATE_R {
80        MAIN_STATE_R::new(((self.bits >> 25) & 7) as u8)
81    }
82    #[doc = "Bits 28:30 - state of SCL state machine"]
83    #[inline(always)]
84    pub fn scl_state(&self) -> SCL_STATE_R {
85        SCL_STATE_R::new(((self.bits >> 28) & 7) as u8)
86    }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("DEBUG_STATUS")
92            .field("ack_val", &self.ack_val())
93            .field("slave_rw", &self.slave_rw())
94            .field("timed_out", &self.timed_out())
95            .field("arb_lost", &self.arb_lost())
96            .field("bus_busy", &self.bus_busy())
97            .field("slave_addr_match", &self.slave_addr_match())
98            .field("byte_trans", &self.byte_trans())
99            .field("main_state", &self.main_state())
100            .field("scl_state", &self.scl_state())
101            .finish()
102    }
103}
104impl W {
105    #[doc = "Bit 0 - The value of an acknowledge signal on the bus"]
106    #[inline(always)]
107    pub fn ack_val(&mut self) -> ACK_VAL_W<DEBUG_STATUS_SPEC> {
108        ACK_VAL_W::new(self, 0)
109    }
110    #[doc = "Bit 1 - When working as a slave, the value of R/W bit received"]
111    #[inline(always)]
112    pub fn slave_rw(&mut self) -> SLAVE_RW_W<DEBUG_STATUS_SPEC> {
113        SLAVE_RW_W::new(self, 1)
114    }
115    #[doc = "Bit 2 - Transfer has timed out"]
116    #[inline(always)]
117    pub fn timed_out(&mut self) -> TIMED_OUT_W<DEBUG_STATUS_SPEC> {
118        TIMED_OUT_W::new(self, 2)
119    }
120    #[doc = "Bit 3 - When working as a master, lost control of I2C bus"]
121    #[inline(always)]
122    pub fn arb_lost(&mut self) -> ARB_LOST_W<DEBUG_STATUS_SPEC> {
123        ARB_LOST_W::new(self, 3)
124    }
125    #[doc = "Bit 4 - operation is in progress"]
126    #[inline(always)]
127    pub fn bus_busy(&mut self) -> BUS_BUSY_W<DEBUG_STATUS_SPEC> {
128        BUS_BUSY_W::new(self, 4)
129    }
130    #[doc = "Bit 5 - When working as a slave, whether address was matched"]
131    #[inline(always)]
132    pub fn slave_addr_match(&mut self) -> SLAVE_ADDR_MATCH_W<DEBUG_STATUS_SPEC> {
133        SLAVE_ADDR_MATCH_W::new(self, 5)
134    }
135    #[doc = "Bit 6 - 8 bit transmit done"]
136    #[inline(always)]
137    pub fn byte_trans(&mut self) -> BYTE_TRANS_W<DEBUG_STATUS_SPEC> {
138        BYTE_TRANS_W::new(self, 6)
139    }
140    #[doc = "Bits 25:27 - state of the main state machine"]
141    #[inline(always)]
142    pub fn main_state(&mut self) -> MAIN_STATE_W<DEBUG_STATUS_SPEC> {
143        MAIN_STATE_W::new(self, 25)
144    }
145    #[doc = "Bits 28:30 - state of SCL state machine"]
146    #[inline(always)]
147    pub fn scl_state(&mut self) -> SCL_STATE_W<DEBUG_STATUS_SPEC> {
148        SCL_STATE_W::new(self, 28)
149    }
150}
151#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct DEBUG_STATUS_SPEC;
153impl crate::RegisterSpec for DEBUG_STATUS_SPEC {
154    type Ux = u32;
155}
156#[doc = "`read()` method returns [`debug_status::R`](R) reader structure"]
157impl crate::Readable for DEBUG_STATUS_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`debug_status::W`](W) writer structure"]
159impl crate::Writable for DEBUG_STATUS_SPEC {
160    type Safety = crate::Unsafe;
161    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
163}
164#[doc = "`reset()` method sets DEBUG_STATUS to value 0"]
165impl crate::Resettable for DEBUG_STATUS_SPEC {
166    const RESET_VALUE: u32 = 0;
167}
esp32/rtc_i2c/debug_status.rs

esp32/rtc_i2c/
debug_status.rs
