pub struct UHCI0 { /* private fields */ }
Implementations§
Source§impl UHCI0
impl UHCI0
Sourcepub const PTR: *const <UHCI0 as Deref>::Target = {0x60005000 as *const <esp32c6::UHCI0 as core::ops::Deref>::Target}
pub const PTR: *const <UHCI0 as Deref>::Target = {0x60005000 as *const <esp32c6::UHCI0 as core::ops::Deref>::Target}
Pointer to the register block
Methods from Deref<Target = RegisterBlock>§
Sourcepub fn conf0(&self) -> &Reg<CONF0_SPEC>
pub fn conf0(&self) -> &Reg<CONF0_SPEC>
0x00 - UHCI Configuration Register0
Sourcepub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>
pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>
0x04 - UHCI Interrupt Raw Register
Sourcepub fn int_st(&self) -> &Reg<INT_ST_SPEC>
pub fn int_st(&self) -> &Reg<INT_ST_SPEC>
0x08 - UHCI Interrupt Status Register
Sourcepub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>
pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>
0x0c - UHCI Interrupt Enable Register
Sourcepub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>
pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>
0x10 - UHCI Interrupt Clear Register
Sourcepub fn conf1(&self) -> &Reg<CONF1_SPEC>
pub fn conf1(&self) -> &Reg<CONF1_SPEC>
0x14 - UHCI Configuration Register1
Sourcepub fn state0(&self) -> &Reg<STATE0_SPEC>
pub fn state0(&self) -> &Reg<STATE0_SPEC>
0x18 - UHCI Receive Status Register
Sourcepub fn state1(&self) -> &Reg<STATE1_SPEC>
pub fn state1(&self) -> &Reg<STATE1_SPEC>
0x1c - UHCI Transmit Status Register
Sourcepub fn escape_conf(&self) -> &Reg<ESCAPE_CONF_SPEC>
pub fn escape_conf(&self) -> &Reg<ESCAPE_CONF_SPEC>
0x20 - UHCI Escapes Configuration Register0
Sourcepub fn hung_conf(&self) -> &Reg<HUNG_CONF_SPEC>
pub fn hung_conf(&self) -> &Reg<HUNG_CONF_SPEC>
0x24 - UHCI Hung Configuration Register0
Sourcepub fn ack_num(&self) -> &Reg<ACK_NUM_SPEC>
pub fn ack_num(&self) -> &Reg<ACK_NUM_SPEC>
0x28 - UHCI Ack Value Configuration Register0
Sourcepub fn rx_head(&self) -> &Reg<RX_HEAD_SPEC>
pub fn rx_head(&self) -> &Reg<RX_HEAD_SPEC>
0x2c - UHCI Head Register
Sourcepub fn quick_sent(&self) -> &Reg<QUICK_SENT_SPEC>
pub fn quick_sent(&self) -> &Reg<QUICK_SENT_SPEC>
0x30 - UCHI Quick send Register
Sourcepub fn reg_q0_word0(&self) -> &Reg<REG_Q0_WORD0_SPEC>
pub fn reg_q0_word0(&self) -> &Reg<REG_Q0_WORD0_SPEC>
0x34 - UHCI Q0_WORD0 Quick Send Register
Sourcepub fn reg_q0_word1(&self) -> &Reg<REG_Q0_WORD1_SPEC>
pub fn reg_q0_word1(&self) -> &Reg<REG_Q0_WORD1_SPEC>
0x38 - UHCI Q0_WORD1 Quick Send Register
Sourcepub fn reg_q1_word0(&self) -> &Reg<REG_Q1_WORD0_SPEC>
pub fn reg_q1_word0(&self) -> &Reg<REG_Q1_WORD0_SPEC>
0x3c - UHCI Q1_WORD0 Quick Send Register
Sourcepub fn reg_q1_word1(&self) -> &Reg<REG_Q1_WORD1_SPEC>
pub fn reg_q1_word1(&self) -> &Reg<REG_Q1_WORD1_SPEC>
0x40 - UHCI Q1_WORD1 Quick Send Register
Sourcepub fn reg_q2_word0(&self) -> &Reg<REG_Q2_WORD0_SPEC>
pub fn reg_q2_word0(&self) -> &Reg<REG_Q2_WORD0_SPEC>
0x44 - UHCI Q2_WORD0 Quick Send Register
Sourcepub fn reg_q2_word1(&self) -> &Reg<REG_Q2_WORD1_SPEC>
pub fn reg_q2_word1(&self) -> &Reg<REG_Q2_WORD1_SPEC>
0x48 - UHCI Q2_WORD1 Quick Send Register
Sourcepub fn reg_q3_word0(&self) -> &Reg<REG_Q3_WORD0_SPEC>
pub fn reg_q3_word0(&self) -> &Reg<REG_Q3_WORD0_SPEC>
0x4c - UHCI Q3_WORD0 Quick Send Register
Sourcepub fn reg_q3_word1(&self) -> &Reg<REG_Q3_WORD1_SPEC>
pub fn reg_q3_word1(&self) -> &Reg<REG_Q3_WORD1_SPEC>
0x50 - UHCI Q3_WORD1 Quick Send Register
Sourcepub fn reg_q4_word0(&self) -> &Reg<REG_Q4_WORD0_SPEC>
pub fn reg_q4_word0(&self) -> &Reg<REG_Q4_WORD0_SPEC>
0x54 - UHCI Q4_WORD0 Quick Send Register
Sourcepub fn reg_q4_word1(&self) -> &Reg<REG_Q4_WORD1_SPEC>
pub fn reg_q4_word1(&self) -> &Reg<REG_Q4_WORD1_SPEC>
0x58 - UHCI Q4_WORD1 Quick Send Register
Sourcepub fn reg_q5_word0(&self) -> &Reg<REG_Q5_WORD0_SPEC>
pub fn reg_q5_word0(&self) -> &Reg<REG_Q5_WORD0_SPEC>
0x5c - UHCI Q5_WORD0 Quick Send Register
Sourcepub fn reg_q5_word1(&self) -> &Reg<REG_Q5_WORD1_SPEC>
pub fn reg_q5_word1(&self) -> &Reg<REG_Q5_WORD1_SPEC>
0x60 - UHCI Q5_WORD1 Quick Send Register
Sourcepub fn reg_q6_word0(&self) -> &Reg<REG_Q6_WORD0_SPEC>
pub fn reg_q6_word0(&self) -> &Reg<REG_Q6_WORD0_SPEC>
0x64 - UHCI Q6_WORD0 Quick Send Register
Sourcepub fn reg_q6_word1(&self) -> &Reg<REG_Q6_WORD1_SPEC>
pub fn reg_q6_word1(&self) -> &Reg<REG_Q6_WORD1_SPEC>
0x68 - UHCI Q6_WORD1 Quick Send Register
Sourcepub fn esc_conf0(&self) -> &Reg<ESC_CONF0_SPEC>
pub fn esc_conf0(&self) -> &Reg<ESC_CONF0_SPEC>
0x6c - UHCI Escapes Sequence Configuration Register0
Sourcepub fn esc_conf1(&self) -> &Reg<ESC_CONF1_SPEC>
pub fn esc_conf1(&self) -> &Reg<ESC_CONF1_SPEC>
0x70 - UHCI Escapes Sequence Configuration Register1
Sourcepub fn esc_conf2(&self) -> &Reg<ESC_CONF2_SPEC>
pub fn esc_conf2(&self) -> &Reg<ESC_CONF2_SPEC>
0x74 - UHCI Escapes Sequence Configuration Register2
Sourcepub fn esc_conf3(&self) -> &Reg<ESC_CONF3_SPEC>
pub fn esc_conf3(&self) -> &Reg<ESC_CONF3_SPEC>
0x78 - UHCI Escapes Sequence Configuration Register3
Sourcepub fn pkt_thres(&self) -> &Reg<PKT_THRES_SPEC>
pub fn pkt_thres(&self) -> &Reg<PKT_THRES_SPEC>
0x7c - UCHI Packet Length Configuration Register