pub struct GPIO_SD { /* private fields */ }
Implementations§
Source§impl GPIO_SD
impl GPIO_SD
Sourcepub const PTR: *const <GPIO_SD as Deref>::Target = {0x60091f00 as *const <esp32c6::GPIO_SD as core::ops::Deref>::Target}
pub const PTR: *const <GPIO_SD as Deref>::Target = {0x60091f00 as *const <esp32c6::GPIO_SD as core::ops::Deref>::Target}
Pointer to the register block
Methods from Deref<Target = RegisterBlock>§
Sourcepub fn sigmadelta(&self, n: usize) -> &Reg<SIGMADELTA_SPEC>
pub fn sigmadelta(&self, n: usize) -> &Reg<SIGMADELTA_SPEC>
0x00..0x10 - Duty Cycle Configure Register of SDM%s
Sourcepub fn sigmadelta_iter(&self) -> impl Iterator<Item = &Reg<SIGMADELTA_SPEC>>
pub fn sigmadelta_iter(&self) -> impl Iterator<Item = &Reg<SIGMADELTA_SPEC>>
Iterator for array of: 0x00..0x10 - Duty Cycle Configure Register of SDM%s
Sourcepub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>
pub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>
0x20 - Clock Gating Configure Register
Sourcepub fn sigmadelta_misc(&self) -> &Reg<SIGMADELTA_MISC_SPEC>
pub fn sigmadelta_misc(&self) -> &Reg<SIGMADELTA_MISC_SPEC>
0x24 - MISC Register
Sourcepub fn glitch_filter_ch(&self, n: usize) -> &Reg<GLITCH_FILTER_CH_SPEC>
pub fn glitch_filter_ch(&self, n: usize) -> &Reg<GLITCH_FILTER_CH_SPEC>
0x30..0x50 - Glitch Filter Configure Register of Channel%s
Sourcepub fn glitch_filter_ch_iter(
&self,
) -> impl Iterator<Item = &Reg<GLITCH_FILTER_CH_SPEC>>
pub fn glitch_filter_ch_iter( &self, ) -> impl Iterator<Item = &Reg<GLITCH_FILTER_CH_SPEC>>
Iterator for array of: 0x30..0x50 - Glitch Filter Configure Register of Channel%s
Sourcepub fn etm_event_ch_cfg(&self, n: usize) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
pub fn etm_event_ch_cfg(&self, n: usize) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
0x60..0x80 - Etm Config register of Channel%s
Sourcepub fn etm_event_ch_cfg_iter(
&self,
) -> impl Iterator<Item = &Reg<ETM_EVENT_CH_CFG_SPEC>>
pub fn etm_event_ch_cfg_iter( &self, ) -> impl Iterator<Item = &Reg<ETM_EVENT_CH_CFG_SPEC>>
Iterator for array of: 0x60..0x80 - Etm Config register of Channel%s
Sourcepub fn etm_event_ch0_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
pub fn etm_event_ch0_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
0x60 - Etm Config register of Channel0
Sourcepub fn etm_event_ch1_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
pub fn etm_event_ch1_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
0x64 - Etm Config register of Channel1
Sourcepub fn etm_event_ch2_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
pub fn etm_event_ch2_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
0x68 - Etm Config register of Channel2
Sourcepub fn etm_event_ch3_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
pub fn etm_event_ch3_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
0x6c - Etm Config register of Channel3
Sourcepub fn etm_event_ch4_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
pub fn etm_event_ch4_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
0x70 - Etm Config register of Channel4
Sourcepub fn etm_event_ch5_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
pub fn etm_event_ch5_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
0x74 - Etm Config register of Channel5
Sourcepub fn etm_event_ch6_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
pub fn etm_event_ch6_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
0x78 - Etm Config register of Channel6
Sourcepub fn etm_event_ch7_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
pub fn etm_event_ch7_cfg(&self) -> &Reg<ETM_EVENT_CH_CFG_SPEC>
0x7c - Etm Config register of Channel7
Sourcepub fn etm_task_p0_cfg(&self) -> &Reg<ETM_TASK_P0_CFG_SPEC>
pub fn etm_task_p0_cfg(&self) -> &Reg<ETM_TASK_P0_CFG_SPEC>
0xa0 - Etm Configure Register to decide which GPIO been chosen
Sourcepub fn etm_task_p1_cfg(&self) -> &Reg<ETM_TASK_P1_CFG_SPEC>
pub fn etm_task_p1_cfg(&self) -> &Reg<ETM_TASK_P1_CFG_SPEC>
0xa4 - Etm Configure Register to decide which GPIO been chosen
Sourcepub fn etm_task_p2_cfg(&self) -> &Reg<ETM_TASK_P2_CFG_SPEC>
pub fn etm_task_p2_cfg(&self) -> &Reg<ETM_TASK_P2_CFG_SPEC>
0xa8 - Etm Configure Register to decide which GPIO been chosen
Sourcepub fn etm_task_p3_cfg(&self) -> &Reg<ETM_TASK_P3_CFG_SPEC>
pub fn etm_task_p3_cfg(&self) -> &Reg<ETM_TASK_P3_CFG_SPEC>
0xac - Etm Configure Register to decide which GPIO been chosen
Sourcepub fn etm_task_p4_cfg(&self) -> &Reg<ETM_TASK_P4_CFG_SPEC>
pub fn etm_task_p4_cfg(&self) -> &Reg<ETM_TASK_P4_CFG_SPEC>
0xb0 - Etm Configure Register to decide which GPIO been chosen
Sourcepub fn etm_task_p5_cfg(&self) -> &Reg<ETM_TASK_P5_CFG_SPEC>
pub fn etm_task_p5_cfg(&self) -> &Reg<ETM_TASK_P5_CFG_SPEC>
0xb4 - Etm Configure Register to decide which GPIO been chosen
Sourcepub fn etm_task_p6_cfg(&self) -> &Reg<ETM_TASK_P6_CFG_SPEC>
pub fn etm_task_p6_cfg(&self) -> &Reg<ETM_TASK_P6_CFG_SPEC>
0xb8 - Etm Configure Register to decide which GPIO been chosen
Sourcepub fn etm_task_p7_cfg(&self) -> &Reg<ETM_TASK_P7_CFG_SPEC>
pub fn etm_task_p7_cfg(&self) -> &Reg<ETM_TASK_P7_CFG_SPEC>
0xbc - Etm Configure Register to decide which GPIO been chosen
Sourcepub fn version(&self) -> &Reg<VERSION_SPEC>
pub fn version(&self) -> &Reg<VERSION_SPEC>
0xfc - Version Control Register