Struct SPI1

pub struct SPI1 { /* private fields */ }

Implementations

impl SPI1

pub const PTR: *const <SPI1 as Deref>::Target = {0x60003000 as *const <esp32c6::SPI1 as core::ops::Deref>::Target}

Pointer to the register block

pub unsafe fn steal() -> SPI1

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const fn ptr() -> *const <SPI1 as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn spi_mem_cmd(&self) -> &Reg<SPI_MEM_CMD_SPEC>

0x00 - SPI1 memory command register

pub fn spi_mem_addr(&self) -> &Reg<SPI_MEM_ADDR_SPEC>

0x04 - SPI1 address register

pub fn spi_mem_ctrl(&self) -> &Reg<SPI_MEM_CTRL_SPEC>

0x08 - SPI1 control register.

pub fn spi_mem_ctrl1(&self) -> &Reg<SPI_MEM_CTRL1_SPEC>

0x0c - SPI1 control1 register.

pub fn spi_mem_ctrl2(&self) -> &Reg<SPI_MEM_CTRL2_SPEC>

0x10 - SPI1 control2 register.

pub fn spi_mem_clock(&self) -> &Reg<SPI_MEM_CLOCK_SPEC>

0x14 - SPI1 clock division control register.

pub fn spi_mem_user(&self) -> &Reg<SPI_MEM_USER_SPEC>

0x18 - SPI1 user register.

pub fn spi_mem_user1(&self) -> &Reg<SPI_MEM_USER1_SPEC>

0x1c - SPI1 user1 register.

pub fn spi_mem_user2(&self) -> &Reg<SPI_MEM_USER2_SPEC>

0x20 - SPI1 user2 register.

pub fn spi_mem_mosi_dlen(&self) -> &Reg<SPI_MEM_MOSI_DLEN_SPEC>

0x24 - SPI1 send data bit length control register.

pub fn spi_mem_miso_dlen(&self) -> &Reg<SPI_MEM_MISO_DLEN_SPEC>

0x28 - SPI1 receive data bit length control register.

pub fn spi_mem_rd_status(&self) -> &Reg<SPI_MEM_RD_STATUS_SPEC>

0x2c - SPI1 status register.

pub fn spi_mem_misc(&self) -> &Reg<SPI_MEM_MISC_SPEC>

0x34 - SPI1 misc register

pub fn spi_mem_tx_crc(&self) -> &Reg<SPI_MEM_TX_CRC_SPEC>

0x38 - SPI1 TX CRC data register.

pub fn spi_mem_cache_fctrl(&self) -> &Reg<SPI_MEM_CACHE_FCTRL_SPEC>

0x3c - SPI1 bit mode control register.

pub fn spi_mem_w0(&self) -> &Reg<SPI_MEM_W0_SPEC>

0x58 - SPI1 memory data buffer0

pub fn spi_mem_w1(&self) -> &Reg<SPI_MEM_W1_SPEC>

0x5c - SPI1 memory data buffer1

pub fn spi_mem_w2(&self) -> &Reg<SPI_MEM_W2_SPEC>

0x60 - SPI1 memory data buffer2

pub fn spi_mem_w3(&self) -> &Reg<SPI_MEM_W3_SPEC>

0x64 - SPI1 memory data buffer3

pub fn spi_mem_w4(&self) -> &Reg<SPI_MEM_W4_SPEC>

0x68 - SPI1 memory data buffer4

pub fn spi_mem_w5(&self) -> &Reg<SPI_MEM_W5_SPEC>

0x6c - SPI1 memory data buffer5

pub fn spi_mem_w6(&self) -> &Reg<SPI_MEM_W6_SPEC>

0x70 - SPI1 memory data buffer6

pub fn spi_mem_w7(&self) -> &Reg<SPI_MEM_W7_SPEC>

0x74 - SPI1 memory data buffer7

pub fn spi_mem_w8(&self) -> &Reg<SPI_MEM_W8_SPEC>

0x78 - SPI1 memory data buffer8

pub fn spi_mem_w9(&self) -> &Reg<SPI_MEM_W9_SPEC>

0x7c - SPI1 memory data buffer9

pub fn spi_mem_w10(&self) -> &Reg<SPI_MEM_W10_SPEC>

0x80 - SPI1 memory data buffer10

pub fn spi_mem_w11(&self) -> &Reg<SPI_MEM_W11_SPEC>

0x84 - SPI1 memory data buffer11

pub fn spi_mem_w12(&self) -> &Reg<SPI_MEM_W12_SPEC>

0x88 - SPI1 memory data buffer12

pub fn spi_mem_w13(&self) -> &Reg<SPI_MEM_W13_SPEC>

0x8c - SPI1 memory data buffer13

pub fn spi_mem_w14(&self) -> &Reg<SPI_MEM_W14_SPEC>

0x90 - SPI1 memory data buffer14

pub fn spi_mem_w15(&self) -> &Reg<SPI_MEM_W15_SPEC>

0x94 - SPI1 memory data buffer15

pub fn spi_mem_flash_waiti_ctrl(&self) -> &Reg<SPI_MEM_FLASH_WAITI_CTRL_SPEC>

0x98 - SPI1 wait idle control register

pub fn spi_mem_flash_sus_ctrl(&self) -> &Reg<SPI_MEM_FLASH_SUS_CTRL_SPEC>

0x9c - SPI1 flash suspend control register

pub fn spi_mem_flash_sus_cmd(&self) -> &Reg<SPI_MEM_FLASH_SUS_CMD_SPEC>

0xa0 - SPI1 flash suspend command register

pub fn spi_mem_sus_status(&self) -> &Reg<SPI_MEM_SUS_STATUS_SPEC>

0xa4 - SPI1 flash suspend status register

pub fn spi_mem_int_ena(&self) -> &Reg<SPI_MEM_INT_ENA_SPEC>

0xc0 - SPI1 interrupt enable register

pub fn spi_mem_int_clr(&self) -> &Reg<SPI_MEM_INT_CLR_SPEC>

0xc4 - SPI1 interrupt clear register

pub fn spi_mem_int_raw(&self) -> &Reg<SPI_MEM_INT_RAW_SPEC>

0xc8 - SPI1 interrupt raw register

pub fn spi_mem_int_st(&self) -> &Reg<SPI_MEM_INT_ST_SPEC>

0xcc - SPI1 interrupt status register

pub fn spi_mem_ddr(&self) -> &Reg<SPI_MEM_DDR_SPEC>

0xd4 - SPI1 DDR control register

pub fn spi_mem_timing_cali(&self) -> &Reg<SPI_MEM_TIMING_CALI_SPEC>

0x180 - SPI1 timing control register

pub fn spi_mem_clock_gate(&self) -> &Reg<SPI_MEM_CLOCK_GATE_SPEC>

0x200 - SPI1 clk_gate register

pub fn spi_mem_date(&self) -> &Reg<SPI_MEM_DATE_SPEC>

0x3fc - Version control register

Trait Implementations

impl Debug for SPI1

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for SPI1

type Target = <SPI1 as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<SPI1 as Deref>::Target

Dereferences the value.

impl DerefMut for SPI1

fn deref_mut(&mut self) -> &mut <SPI1 as Deref>::Target

Mutably dereferences the value.

impl Peripheral for SPI1

type P = SPI1

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <SPI1 as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.